Attorney Docket No. APL-P2766-C2
`
`/ ’
`
`
`
`
`12, \-
`
` f TERMJNAL DISCLAINIER TO OBVIATE A PROVISIONAL DOUBLE
`
`‘--FEB' 172 2007
`
`
`
`PATENTING REJECTION OVER AN ISSUED PATENT
`
`In re Application of: Lynn R. Youngs
`Application No.:
`l 1/213,215
`Filing Date:
`25 August 2005
`Title:
`Conserving Power by Reducing Voltage Supplied to an
`Instruction—Processing Portion of a Processor
`
`The owner*, Apple Inc. of a m percent interest in the above-identified instant application hereby
`disclaims, except as provided below, the terminal part of the statutory term of any patent granted on the
`instant application, which would extend beyond the expiration date of the full statutory term defined in 35
`
`U.S.C. §§154 to 156 and 173, as presently shortened by any terminal of prior Patent No. 6 920 574. The
`owner hereby agrees that any patent so granted on the instant application shall be enforceable only for and
`during such period that it and the prior patent are commonly owned. This agreement runs with any patent
`granted on the instant application and is binding upon the grantee, its successors or assigns.
`In making the above disclaimer, the owner does not disclaim the terminal part of any patent
`granted on the instant application that would extend to the expiration date of the full statutory term as
`defined in 35 U.S.C. 154 to 156 and 173 of the prior patent, as presently shortened by any terminal
`disclaimer, in the event that it later: expires for failure to pay a maintenance fee, is held unenforceable, is
`found invalid by a court of competentjurisdiction, is statutorily disclaimed in whole or terminally
`disclaimed under 37 C.F.R. 1.321, has all claims canceled by a reexamination certificate, is reissued, in is
`in any manner terminated prior to expiration of its full statutory term as presently shortened by any terminal
`disclaimer.
`
`[x]
`
`A terminal disclaimer fee of $130 under 37 C.F.R. §1.20(d) is included herewith.
`
`As I am not a person registered to practice before the Office, I hereby declare that all statements
`[ ]
`made herein of my own knowledge are true and that all statements made on information and believe are
`believed to be true; and further, that these statements were made with the knowledge that willful false
`statement and the like so made are punishable by fine or imprisonment, or both, under Section 1001 of
`Title 18 of the United States Code, and that such willful false statements mayjeopardize the validity of the
`application or any patent issuing thereon.
`
`Respectfully submitted,
`
`By ' flShun Yao (A omey)
`
`Registration No. 59,242
`
`Date:
`
`5 February 2007
`
`PARK, VAUGHAN & FLEMING LLP
`2820 Fifth Street
`
`Davis, CA 95618-7759
`(530) 759-1661
`
`*Certification under 37 CFR 3.73(b) is required if terminal disclaimer is signed by the assignee (owner).
`
`02/13/2007 HVUONBI
`
`00000026 11213215
`
`01 FC:1814
`
`130.00 0p
`
`1
`
`Qualcomm, Ex. 1019, Page 1
`
`Qualcomm, Ex. 1019, Page 1
`
`

`

` Certificate Under 37 CFR 3.73(b)
`
`
`aaAAV“
`atent Owner: Lynn R. Youngs
`
`Application No./Patent No.2 1 1 / 2 1 3 , 2 1 5
`
`Filed/Issue Date: 2 5 August 2 0 0 5
`
`Entitled: Conserving Power by Reducing Voltage Supplied to an Instruction Processing Portion of
`a Processor
`
`film—m a Cor oration
`'
`(Name of Assigme)
`,
`(Type of ”Sign“, e.g. WWW“, Pame'Shin uniVmi‘)’, govemmem agency. etc.)
`
`certifies that it is the assignee of the entire right, title and interest in the patent application/patent identified above by virtue of either:
`
`A. [X] An assignment from the inventor(s) of the patent application/patent identified above. The assignment was recorded'in the
`
`Patent and Trademark Office at Reel 012856, Frame 0922, or for which a copy thereof is attached.
`
`OR
`
`B. []
`
`A chain of title from the inventor(s), of the patent application/patent identified above, to the current assignee as shown
`below:
`
`1. From:
`
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`
`2. From:
`
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`
`3. From:
`
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`
`[ ] Additional documents in the chain of title are listed on a supplemental sheet.
`
`[ ] Copies of assignments or other documents in the chain of title are attached.
`
`The undersigned has reviewed all the documents in the chain of title of the patent application/patent identified above and, to the
`best of undersigned's knowledge and belief, title is in the assignee identified above.
`
`The undersigned (whose title is supplied below) is empowered to sign this certificate on behalf of the assignee.
`
`I hereby declare that all statements made herein of my own knowledge are true, and that all statements made on information and
`belief are believed to be true; and further, that these statements are made with the knowledge that willful false statements, and the
`like so made, are punishable by fine or imprisonment, or both, under Section 1001 , Title 18 of the United States Code, and that such
`willful false statements may jeopardize the validity of the application/patent or any patent issuing thereon.
`
`Date: 5 February 2007
`
`____.—____
`
`Name: Shun Yao (Reg. No. 59,242)
`
`Title: Attorney
`
`————————————————
`
`Signature: :;%
`
`Qualcomm, Ex. 1019, Page 2
`
`Qualcomm, Ex. 1019, Page 2
`
`

`

`
`
`Certificate Under 3'7 CFR 3.7300)
`
`nt Owner: Lynn R. Youngs
`
`Application No./Patent No.2 6, 920, 574
`
`Filed/Issue Date: 29 April 2002
`
`lied to an Instruction Processin Portion of
`Power b Reducin Volta e Su
`EnfifledZConservin
`
`a Processor
`
`
`A
`1e Inc-
`(Name m. Assigme)
`
`,agggor_a§_mn_______
`(Type of Assigme. e.g. corporation. partnership. university, govemmem agency. etc.)
`
`certifies that it is the assignee of the entire right, title and interest in the patent application/patent identified above by virtue of either:
`
`A. [X] An assignment from the inventor(s) of the patent application/patent identified above. The assigmnent was recorded in the
`
`Patent and Trademark Office at Reel 012856, Frame 0922, or for which a copy thereof is attached.
`
`OR
`
`B.
`
`[ ]
`
`A chain of title from the inventor(s), of the patent application/patent identified above, to the current assignee as shown
`below:
`
`1. From:
`
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`
`2. From:
`
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`3. From:
`To:
`
`The document was recorded in the patent and Trademark Office at
`Reel _, Frame _, or for which a copy thereof is attached
`
`[ ] Additional documents in the chain of title are listed on a supplemental sheet.
`
`[ ] Copies of assigmnents or other documents in the chain of title are attached.
`
`The undersigned has reviewed all the documents in the chain of title of the patent application/patent identified above and, to the
`best of undersigned's knowledge and belief, title is in the assignee identified above.
`
`The undersigned (whose title is supplied below) is empowered to sign this certificate on behalf of the assignee.
`
`I hereby declare that all statements made herein of my own knowledge are true, and that all statements made on information and
`belief are believed to be true; and further, that these statements are made with the knowledge that willful false statements, and the
`like so made, are punishable by fine or imprisonment, or both, under Section 1001, Title 18 of the United States Code, and that such
`willful false statements may jeopardize the validity of the application/patent or any patent issuing thereon.
`
`Dam: 5 February 2007
`
`Name: Shun Yao (Reg. No. 59,242)
`
`TitleimL—__________——__——————
`
`Signature: é@ ——————————-———————————-
`
`Quamonun,Ex.1019,Page3
`
`Qualcomm, Ex. 1019, Page 3
`
`

`

`"
`
`Applicant(s)lPatent under ., I:
`Reexamination
`,2
`
`
`Application/Control No.
`
`
`Application Number
`
`
`
`
`
`
`11/213,215
`YOUNGS, LYNN R.
`
`
`
`Document Code - DISQ
`
`Internal Document — DO NOT MAIL
`
`
`
`
`
`TERMINAL
`DISCLAIMER
`
`E APPROVED
`
`[I DISAPPROVED
`
`
`Date Filed : 021207
`
`
`
`This patent is subject
`to a Terminal
`
`Disclaimer
`
`
`
`Approved/Disapproved by:
`
`US. Patent and Trademark Office
`
`Qualcomm, Ex. 1019, Page 4
`
`Qualcomm, Ex. 1019, Page 4
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 7,383,453 B2
`: 11/213215
`
`DATED
`INVENTOR(S)
`
`: June 3, 2008
`: Lynn R Youngs
`
`Page 1 of 1
`
`ItIs certified that error appears in the above-identified patent and that said Letters Patent'Is
`hereby corrected as shown below.
`
`i
`Title Page item [73]
`
`In the Assignee Name (on page 1), please delete“‘Apple, Inc.”.
`
`In the Assignee name (on page 1), please insert --APPLE 1NC.--.
`
`
`
`Signed and Sealed this
`
`Thirteenth Day of January, 2009
`
`, wgi
`
`JON W. DUDAS
`Director ofthe United States Patent and Trademark Ofi‘ice
`
`Qualcomm, Ex. 1019, Page 5
`
`Qualcomm, Ex. 1019, Page 5
`
`

`

`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`APPLICATION NO.
`
`: 7,383,453 32
`: 11/213215
`
`-
`
`Page 1 of 1
`
`DATED
`INVENTOR(S)
`
`: June 3, 2008
`: Lynn R Youngs
`
`It is certified that error appears in the above-identified patent and that said Letters Patent is
`hereby corrected as shown below:
`
`Acting Director ofthe United States Patent and Trademark Ofiice _
`
`Title page Item [73]
`In the Assignee Name (on page 1), please delete “Apple, Inc.”.
`
`Title page Item [73]
`In the Assignee Name (on page 1), please insert --APPLE 1NC.--.
`
`Signed and Sealed this
`
`Seventeenth Day of February, 2009'
`
`-
`
`-
`
`.
`
`'
`
`'
`
`,AQM
`
`JOHN DOLL
`
`Qualcomm, Ex. i019,,..Page 6f :'
`
`
`
`Qualcomm, Ex. 1019, Page 6
`
`

`

`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`In re Application of:
`US. Patent No.:
`
`Youngs
`7,383,453
`
`Issued:
`
`Group Art Unit:
`Serial No:
`Examiner:
`
`Filed:
`For:
`
`June 3, 2008
`
`21 16
`11/213,215
`Rehana Perveen
`
`August 25, 2005
`CONSERVING POWER BY REDUCING VOLTAGE
`
`SUPPLIED TO AN INSTRUCTION-PROCESSING
`
`PORTION OF A PROCESSOR
`
`Attorney Docket No.
`
`0919/01034
`
`Mail Stop Ex Parte Reexamination
`Commissioner for Patents
`
`PO. Box 1450
`
`Alexandria, VA 22313-1450
`
`Sir:
`
`April 28, 20 1 0
`
`REQUEST FOR REEXAMINATION
`
`Reexamination of United States Patent 7,383,453 (hereinafter, “the ’453 patent”),
`
`which issued June 3, 2008 to Youngs is requested under 35 U.S.C. §§ 302-307, and under
`
`37 CPR. § 1.510. This patent is still in force.1 A copy of the patent in accordance with
`
`37 CPR. § 1.510(b)(4) is submitted herewith as Exhibit A. Related applications remain
`
`pending or have issued as patents.2
`
`1.
`
`Claims for which Reexamination is Requested
`
`The ’453 patent is for a system, method, and apparatus for facilitating the
`
`reduction of static power consumption of a processor. The patent recognizes that known
`
`processes directed to stopping the clock to the core region of the processor reduce
`
`1 A lawsuit for alleged infringement of the ’453 patent has been filed in the US. District Court for the
`District of Delaware, Nokz'a Corp. v. Apple Inc, Case No. 09-791 (D. Del.). That litigation is in its early
`stages and no discovery has taken place. If the litigation proceeds, Third Party Requester expects there will
`be a challenge to the validity of the ’453 patent therein.
`2 Issued patents include 6,920,574 (from grandparent application 10/135,116), 6,973,585 (from parent
`application 11/103,911), 7,370,216 (from continuation application 11/715,092), and 7,694,162 (from
`continuation application 11/515,315). Continuation application 12/103,104 remains pending. The
`prosecution files are available on Public PAIR.
`
`Qualcomm, Ex. 1019, Page 7
`
`Qualcomm, Ex. 1019, Page 7
`
`

`

`dynamic power consumption without significantly affecting the static power
`
`consumption. In a disclosed embodiment, the static power consumption is reduced by
`
`decreasing the core voltage while the core region of the processor is idle and its clock is
`
`stopped. Reexamination is requested of all Claims 1-21 of the ’453 patent.
`
`During prosecution of the ’453 patent, an Examiner’s amendment failed to be
`
`entered, and the ’453 patent issued without amending the claims as recited in the
`
`Examiner’s amendment. Accordingly, the Patent Owner filed a Request for Certificate
`
`of Correction seeking replacement of the allowed claims with those listed in the
`
`Examiner’s amendment. A minor error was made by the Patent Owner, however,
`
`causing the Art Unit to approve the request only in part and return it to the Certificate of
`
`Corrections Branch in August 2008. The Office has not acted on the Request for
`
`Certificate of Correction as far as the Requester can determine from Public PAIR. For
`
`completeness, the Requester presents alternative Grounds for Rejections of both the
`
`claims as issued and the claims as proposed in the Certificate of Correction.
`
`11.
`
`Statement of Substantial New Questions of Patentability
`
`A. The Subject Matter of Claims 1-21
`
`i. Claims as Published
`
`Claims 1-21 as they currently stand published in the granted ’453 patent recite:
`
`I. An instruction-processing system with minimal static power leakage, the instruction-
`
`processing system comprising:
`
`a core with instruction-processing circuitry; an area coupled to the core; a core
`
`voltage provided to the core; and an area voltage provided to the area;
`
`Qualcomm, Ex. 1019, Page 8
`
`Qualcomm, Ex. 1019, Page 8
`
`

`

`wherein in a normal operation mode.‘ a clock signal to the core is active; the core
`
`voltage is a first value; the core is active; the area voltage is a second value; and the
`
`area is active;
`
`wherein in a first power-saving mode that is exited upon receipt ofan interrupt
`
`signal.‘ the clock signal to the core is inactive; the core voltage is equal to or greater
`
`than the first value; and the area voltage is equal to or greater than the second value;
`
`wherein in a second power-saving mode that can be exited upon receipt ofa signal
`
`that is not an interrupt signal.‘ the clock signal to the core is inactive; the core voltage
`
`is less than thefirst value; and the area voltage is equal to or greater than the second
`
`value.
`
`2. The instruction-processing system ofclaim I, wherein thefirst power-saving mode can
`
`be exited upon receipt ofa signal that is not an interrupt signal.
`
`3. The instruction-processing system ofclaim I, wherein the area comprises a cache.
`
`4. The instruction-processing system ofclaim 3, wherein the area further comprises
`
`cache tags.
`
`5. The instruction-processing system ofclaim I, wherein prior to entering the second
`
`power-saving mode, the state of the core is saved to a memory.
`
`6. The instruction-processing system ofclaim I, wherein upon exiting the second power-
`
`saving mode, the state of the core is restored.
`
`7. The instruction-processing system ofclaim I, wherein in the second power-saving
`
`mode, the core voltage is at zero.
`
`8. A methodfor minimizing static power leakage in an instruction-processing system,
`
`wherein the instruction-processing system comprises a core with instruction-
`
`Qualcomm, Ex. 1019, Page 9
`
`Qualcomm, Ex. 1019, Page 9
`
`

`

`processing circuitry, an area coupled to the core, a core voltage provided to the core,
`
`and an area voltage provided to the area, the method comprising:
`
`entering a normal operation mode by: providing a clock signal to the core; providing
`
`the core with a core voltage that is equal to a first value; providing the area with an
`
`area voltage that is equal to a second value;
`
`entering a first power-saving mode by: disabling the clock signal to the core;
`
`providing the core with a core voltage that is equal to or greater than the first value;
`
`and providing the area with an area voltage that is equal to or greater than the
`
`second value; exiting the first power-saving mode upon receipt ofan interrupt signal;
`
`entering a second power-saving mode by: disabling the clock signal to the core;
`
`setting the core voltage to a value less than thefirst value; and providing the area
`
`with an area voltage that is equal to or greater than the second value; and exiting the
`
`second power-saving mode upon receipt ofa signal that is not an interrupt signal.
`
`9. The method ofclaim 8, further comprising exiting the first power-saving mode upon
`
`receipt ofa signal that is not an interrupt signal.
`
`10. The instruction-processing system ofclaim 8, wherein the area comprises a cache.
`
`1 I. The method ofclaim 10, wherein the area further comprises cache tags.
`
`12. The method ofclaim 8, further comprising saving the state of the core to a memory
`
`prior to entering the second power-saving mode.
`
`13. The method ofclaim 8, further comprising restoring the state of the core upon exiting
`
`the second power-saving mode.
`
`14. The method ofclaim 8, wherein in the second power-saving mode, setting the core
`
`voltage to the value less than the first value comprises setting the core voltage to
`
`Z670.
`
`Qualcomm, Ex. 1019, Page 10
`
`Qualcomm, Ex. 1019, Page 10
`
`

`

`15. A computer-readable medium containing data representing an instruction-processing
`
`system with minimal static power leakage, the instruction- processing system
`
`comprising: a core with instruction-processing circuitry; an area coupled to the core;
`
`a core voltage provided to the core; and an area voltage provided to the area;
`
`wherein in a normal operation mode: a clock signal to the core is active; the core
`
`voltage is a first value; the core is active; the area voltage is a second value; and the
`
`area is active;
`
`wherein in a first power-saving mode that is exited upon receipt ofan interrupt
`
`signal: the clock signal to the core is inactive; the core voltage is equal to or greater
`
`than the first value; and the area voltage is equal to or greater than the second value;
`
`wherein in a second power-saving mode that can be exited upon receipt ofa signal
`
`that is not an interrupt signal: the clock signal to the core is inactive; the core voltage
`
`is less than thefirst value; and the area voltage is equal to or greater than the second
`
`value.
`
`I 6. The computer-readable medium ofclaim 15, wherein thefirst power-saving mode can
`
`be exited upon receipt ofa signal that is not an interrupt signal.
`
`I 7. The computer-readable medium ofclaim 15, wherein the area comprises a cache.
`
`18. The computer-readable medium ofclaim I 7, wherein the area further comprises
`
`cache tags.
`
`19. The computer-readable medium ofclaim 15, wherein prior to entering the second
`
`power-saving mode, the state of the core is saved to a memory.
`
`20. The computer-readable medium ofclaim 15, wherein upon exiting the second power-
`
`saving mode, the state of the core is restored.
`
`Qualcomm, Ex. 1019, Page 11
`
`Qualcomm, Ex. 1019, Page 11
`
`

`

`21. The computer-readable medium stem ofclaim 15, wherein in the second power-
`
`saving mode, the core voltage is at zero.
`
`Each of the independent claims 1, 8, and 15 recite: a normal power mode, a first
`
`power saving mode that can be exited upon receipt of an interrupt signal, and a second
`
`power-saving mode that can be exited upon receipt of a signal that is not an interrupt
`
`signal. Dependent claims 2, 9, and 16 all recite that the first power-saving mode can be
`
`exited upon receipt of a signal that is not an interrupt signal. Requester notes that nothing
`
`in the ’453 patent discloses what type of signals other than interrupts may be used to exit
`
`a power-saving mode. Instead, the ’453 patent at best discloses that the power-saving
`
`modes are exited “[u]pon receiving an interrupt or other signal” (the ’453 patent, col. 4,
`
`lines 27-28; col. 4, lines 66-67; and col. 5, lines 11-12).
`
`ii. Claims 1, 8, 10, 15, and 21 as Amended in the Certificate of Correction
`
`As noted above, there exists ambiguity as to the correct claim language for certain
`
`claims. In particular, during prosecution of the ’453 patent, Applicant filed a Request for
`
`Certificate of Correction based on an Examiner’s amendment that was not entered.
`
`Should the amendments in the Request for Certificate of Correction be entered, the
`
`affected claims would read as follows:
`
`1. (Certificate of Correction) An instruction-processing system with minimized static
`
`power leakage, the instruction-processing system comprising:
`
`a core with instruction-processing circuitry; an area coupled to the core; a core
`
`voltage provided to the core; and an area voltage provided to the area;
`
`wherein in a normal operation mode: a clock signal to the core is active; the core
`
`voltage is a first value that is sufiicient to maintain the state information ofthe
`
`Qualcomm, Ex. 1019, Page 12
`
`Qualcomm, Ex. 1019, Page 12
`
`

`

`instruction processing-circuitry; the core is active; the area voltage is a second value
`
`that is sufiicient to maintain the data stored in the area; and the area is active;
`
`wherein in a first power-saving mode that can be exited upon receipt ofan interrupt
`
`signal: the clock signal to the core is inactive; the core voltage is sufiicient to
`
`maintain the state information of the instruction processing-circuitry; and the area
`
`voltage is sufiicient to maintain the data stored in the area;
`
`wherein in a second power-saving mode that can be exited upon receipt ofa signal
`
`that is not an interrupt signal: the clock signal to the core is inactive; the core voltage
`
`is less than thefirst value; and the area voltage is sufiicient to maintain the data
`
`stored in the area.
`
`8. (Certificate of Correction) A methodfor minimizing static power leakage in an
`
`instruction-processing system, wherein the instruction-processing system comprises a
`
`core with instruction-processing circuitry, an area coupled to the core, a core voltage
`
`provided to the core, and an area voltage provided to the area, the method
`
`comprising:
`
`entering a normal operation mode by: providing a clock signal to the core; providing
`
`the core with a core voltage equal to a first value that is sufiicient to maintain the
`
`state information ofthe instruction processing-circuitry; providing the area with an
`
`area voltage equal to a second value that is sufiicient to maintain the data stored in
`
`the area;
`
`entering a first power-saving mode by: disabling the clock signal to the core;
`
`providing the core with a core voltage that is sufiicient to maintain the state
`
`information ofthe instruction processing-circuitry; and providing the area with an
`
`area voltage that is that is sufiicient to maintain the data stored in the area;
`
`Qualcomm, Ex. 1019, Page 13
`
`Qualcomm, Ex. 1019, Page 13
`
`

`

`exiting the first power-saving mode upon receipt ofan interrupt signal;
`
`entering a second power-saving mode by: disabling the clock signal to the core;
`
`setting the core voltage to a value less than thefirst value; and providing the area
`
`with an area voltage that is sufiicient to maintain the data stored in the area; and
`
`exiting the second power-saving mode upon receipt ofa signal that is not an interrupt
`
`signal.
`
`10.
`
`I5.
`
`(Certificate of Correction) The method ofclaim 8, wherein the area comprises a
`
`cache.
`
`(Certificate of Correction) A computer-readable medium storing code which
`
`represents an instruction-processing system with minimized static power leakage, the
`
`instruction- processing system comprising: a core with instruction-processing
`
`circuitry; an area coupled to the core; a core voltage provided to the core; and an
`
`area voltage provided to the area;
`
`wherein in a normal operation mode: a clock signal to the core is active; the core
`
`voltage is a first value that is sufiicient to maintain the state information ofthe
`
`instruction processing-circuitry; the core is active; the area voltage is a second value
`
`that is sufiicient to maintain the data stored in the area; and the area is active;
`
`wherein in a first power-saving mode that can be exited upon receipt ofan interrupt
`
`signal: the clock signal to the core is inactive; the core voltage is sufiicient to
`
`maintain the state information of the instruction processing-circuitry; and the area
`
`voltage is sufiicient to maintain the data stored in the area;
`
`wherein in a second power-saving mode that can be exited upon receipt ofa signal
`
`that is not an interrupt signal: the clock signal to the core is inactive; the core voltage
`
`Qualcomm, Ex. 1019, Page 14
`
`Qualcomm, Ex. 1019, Page 14
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`is less than thefirst value; and the area voltage is sufiicient to maintain the data
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`stored in the area.
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`21. (Certificate of Correction) The computer-readable medium ofclaim 15, wherein in
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`the second power-saving mode, the core voltage is at zero.
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`Claims 1, 8, 10, 15, and 21 as they appear in amended form in the Request for
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`Certificate of Correction will be addressed in the fourth, fifth, and sixth grounds for
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`rejection below.
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`In reexamination, as with any proceeding before the US. Patent and Trademark
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`Office (“USPTO”), the terms and phrases of a claim are given their broadest reasonable
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`construction. E.g., In re American Academy ofScience Tech Center, 367 F.3d 1359, 70
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`USPQ2d 1827, 1830 (Fed. Cir. 2004) (“During examination, ‘claims
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`are to be given
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`their broadest reasonable interpretation .
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`. ..” (quoting In re Bond, 910 F.2d 831, 833, 15
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`USPQ2d 1566 (Fed. Cir. 1990))).
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`B. Newly cited Prior Art
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`The ’453 patent matured from a US. patent application filed on August 25, 2005,
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`and purports to claim priority to US. patent application no. 1 1/ 103,91 1, now US. patent
`
`no. 6,973,585, filed April 11, 2005. The ‘453 patent further notes that US. patent
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`application no. 11/103,911 is a continuation of US. patent application no. 10/135,116,
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`now US. patent no. 6,920,574, filed April 29, 2002. Therefore, the earliest possible
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`effective filing date for the ’453 patent is April 29, 2002. The following references are
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`relied upon in the various grounds for rejection discussed below:
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`0 Patent Cooperation Treaty (PCT) Patent Application Publication No. WO
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`01/27728 A1 to Qureshi et al. (“the Qureshi application”), published April 19,
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`2001 (Exhibit B)
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`Qualcomm, Ex. 1019, Page 15
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`Qualcomm, Ex. 1019, Page 15
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`o Applicant’s Admitted Prior Art (“AAPA”) in US. Patent No. 7,383,453 to
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`Youngs (Exhibit A)
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`0 United States Patent Number 6,792,551 to Dai (“the Dai patent”), filed
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`November 26, 2001 (Exhibit C)
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`The Qureshi application was published more than one year before the earliest
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`possible effective filing date of the ‘453 patent and is, therefore, prior art under at least 35
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`U.S.C. § lO2(b). The Dai patent was filed prior to the earliest possible effective filing
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`date of the ‘453 patent and is, therefore, prior art under at least 35 U.S.C. § lO2(e). The
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`Requester notes that the Qureshi application was not considered during prosecution of the
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`’453 patent, nor is it cumulative of any of the references considered during prosecution.
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`The Dai patent was applied against the claims during prosecution of the ‘453 patent,
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`though never in combination with Qureshi as relied upon in the third and sixth grounds of
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`rejection described below. Consequently, the Qureshi application is newly applied and
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`the grounds of unpatentability raised herein unquestionably raise new questions of
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`patentability.
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`C. Basis for Substantial New Questions of Patentability
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`Claims 1-2, 5-9, 12-16, 19-21 of the ’453 patent do not patentably distinguish over
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`the above-noted newly cited Qureshi application. Additionally, claims 1-21 of the ’453
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`patent do not patentably distinguish over the combination of the Qureshi application and
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`the Dai patent. Furthermore, claims 1-21 do not patentably distinguish over the
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`combination of the Qureshi application and the AAPA. The following bases for
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`substantial new questions of patentability apply to both versions of the ’453 claims, that
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`is, both the set of claims as published and the set of claims recited in the Request for
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`Certificate of Correction.
`
`-10-
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`Qualcomm, Ex. 1019, Page 16
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`Qualcomm, Ex. 1019, Page 16
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`In summary, Qureshi discloses a known power-saving mode involving disabling a
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`clock to a portion of the processor to reduce dynamic power consumption. The
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`disclosure teaches an additional power-saving mode, which involves reducing the core
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`voltage of the processor to a minimum value necessary to maintain state information
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`while the clock is stopped. The power-saving modes of Qureshi may be exited using an
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`interrupt signal or any other wake-up event.
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`The AAPA discloses dividing the processor into separate regions, which can each
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`be controlled independently. The disclosure fiarther describes a known method for
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`reducing power consumption by stopping the clock signal to portions of an idle processor
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`that do not contain the cache memory, interrupt circuitry, or real-time clock circuitry.
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`This method is recognized as only reducing dynamic power consumption, not static
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`power consumption.
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`The Dai patent discloses a processor with both a core region and a memory region,
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`which comprises a cache memory, each with its own separate voltage source. The
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`disclosure fiarther teaches a low-power mode involving saving the processor context to
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`the memory region, stopping a clock to the core region, and reducing the voltage of the
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`core region, in some embodiments to zero volts. Upon exiting the low-power mode using
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`a power status signal or a snoop control circuit, the state of the processor saved in the
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`memory region (cache) is restored and the clock and voltage to the core are returned to
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`normal operating modes.
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`Thus, the Qureshi application alone anticipates claims l-2, 5-9, 12-16, and 19-21
`
`of the ’453 patent under 35 U.S.C. § 102. Additionally, claims l-21 would have been
`
`obvious and, therefore, unpatentable over the combination of Qureshi and Dai under 35
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`U.S.C. § 103. In particular, Dai provides additional support for the teachings of Qureshi,
`
`-11-
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`Qualcomm, Ex. 1019, Page 17
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`Qualcomm, Ex. 1019, Page 17
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`and Dai also explicitly discloses an area (the memory region) coupled to the core
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`comprising a cache. One skilled in the art would have found motivation to combine
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`Qureshi with Dai, which both not only seek to solve the same problem (i.e. reducing
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`power consumption of a processor) but provide the same solution (i.e. reducing core
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`voltage and stopping the clock signal to the processor core when it is not in use).
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`Furthermore, the AAPA discloses each element of claims 1-21 except for
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`providing separate voltages to the separate regions of the processor, reducing the core
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`voltage while the clock signal to the core is inactive, and exiting the power-saving modes
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`upon receipt of an interrupt or other signal. As described above, Qureshi discloses all of
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`these missing recitations of the AAPA. Both the AAPA and Qureshi seek to reduce
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`power consumption of a processor while it is not in use. One of ordinary skill in the art
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`would have found motivation to modify the AAPA, which describes a power-saving
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`mode limited to reducing dynamic power consumption, with the teachings of Qureshi,
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`which describes an additional power-saving mode for reducing static power consumption
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`as well as dynamic power consumption. Therefore, claims 1-21 would have been
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`unpatentable over the combination of the AAPA in view of Qureshi under 35 U.S.C. §
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`1 03 .
`
`With respect to claims 1-21, modifying Qureshi in view of Dai would have been
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`obvious because such a modification would have involved using a known technique to
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`improve a similar device in the same way to achieve predictable results. Namely, Dai
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`discloses the known technique of including a cache memory in an area of a processor.
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`This technique could have been used to improve the device in Qureshi to provide a cache
`
`-12-
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`Qualcomm, Ex. 1019, Page 18
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`Qualcomm, Ex. 1019, Page 18
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`memory in an area associated with the processor to predictably store state information in
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`a cache as claimed in the ’453 patent.3
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`With respect to claims 1-21, modifying the AAPA in view of the Qureshi
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`application would have been obvious because such a modification would have involved
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`the mere combination of prior art elements according to known methods to yield
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`predictable results. In particular, the AAPA describes a power-saving mode where
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`dynamic power consumption is decreased by stopping the clock to a core region of the
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`processor. Qureshi teaches a power-saving mode where both dynamic and static power
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`consumption are decreased by stopping the clock to a core region of the processor and
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`reducing the core voltage. Combining these two power-saving modes in the same system
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`would result, predictably, in the two-mode system described in the ’453 patent.4
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`Furthermore, modifying the AAPA in view of the Qureshi application would have
`
`been obvious because such a modification would have involved using a known technique
`
`to improve a s