UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`Qualcomm Inc. and Qualcomm Technologies, Inc.,
`Petitioners,
`
`v.
`
`Apple Inc.,
`Patent Owner.
`
`U.S. PATENT NO. 8,433,940
`Filing Date: March 28, 2012
`Issue Date: April 30, 2013
`
`Title: CONSERVING POWER BY REDUCING VOLTAGE SUPPLIED TO AN
`INSTRUCTION-PROCESSING PORTION OF A PROCESSOR
`
`DECLARATION OF RICHARD BELGARD
`
`Qualcomm, Ex. 1002, Page 1
`
`

`

`Contents
`I.
`Introduction............................................................................................................................. 1
`II. Qualifications.......................................................................................................................... 1
`III. Materials Considered ........................................................................................................... 4
`IV.
`Relevant Legal Standards .................................................................................................... 4
`V. Summary of Opinions ............................................................................................................. 7
`Relevant Technology and ʼ940 Patent ................................................................................. 7
`VI.
`A.
`Dynamic vs. Static Power Consumption.......................................................................... 7
`B.
`Cache, Cache Tags, Cache Coherency & Snooping ........................................................ 9
`C.
`Processors, Microprocessors, Microcontrollers and CPUs ............................................ 13
`VII. Claim Construction ............................................................................................................ 13
`“power area”................................................................................................................... 13
`A.
`VIII.
`Person of Ordinary Skill in the Art ................................................................................ 14
`The ʼ940 Patent .................................................................................................................. 14
`IX.
`X. Overview of the Prior Art ..................................................................................................... 16
`A.
`Ober (U.S. 6,665,802) .................................................................................................... 16
`B.
`Dai (U.S. 6,792,551) ...................................................................................................... 21
`Analysis of the ’940 Claims at Issue.................................................................................. 22
`XI.
`XII. Analysis of the Prior Art against the ‘940 Claims at Issue ................................................ 24
`Claims 9-11 and 15 Are Obvious Over Ober in View of Dai ’551 ........................... 24
`A.
`Motivation to Combine Ober with Dai....................................................................... 24
`Independent Claim 9 is Obvious over Ober in View of Dai ....................................... 26
`9.
`Independent Claim 9................................................................................................... 26
`9a. – “a non-core power area, comprising:” ......................................................................... 26
`9a1 – “an interrupt processor;” ............................................................................................. 27
`9a2 – “a real-time clock; and” .............................................................................................. 27
`9a3 – “clock distribution circuitry; and”............................................................................... 28
`9a4 – “an L2 cache;”............................................................................................................. 29
`9a5 – “cache tags;”................................................................................................................ 30
`9a6 – “snoop circuitry;” ........................................................................................................ 31
`9b. “a core power area coupled to the non-core power area, comprising:” .......................... 32
`9b1. “one or more L1 caches;” ............................................................................................. 33
`9b2. “an arithmetic logic unit;”............................................................................................. 33
`9b3. “one or more register files; and” ................................................................................... 34
`
`B.
`
`1.
`
`-ii-
`
`Qualcomm, Ex. 1002, Page 2
`
`

`

`9b4. “one or more pipelines;” ............................................................................................... 35
`9c. “wherein, in predetermined operating modes, the non-core power area is configured to
`be operable while the core power area is halted.” ................................................................ 36
`Dependent Claim 10 – “The processor of claim 9, wherein the core power area is
`10.
`configured to perform instruction processing for the processor.” ........................................ 37
`Dependent Claim 11 – “The processor of claim 10, wherein, in predetermined
`11.
`operating modes, the non-core power area is configured to be operable while instruction
`processing is halted in the core power area.”........................................................................ 38
`Dependent Claim 15 – “The processor of claim 9, wherein the clock distribution
`15.
`circuitry is configured to distribute clock signals to the core power area and the non-core
`power area, wherein the clock signals are conditionally haltable to at least one of core
`power area and non-core power area.” ................................................................................. 40
`Claim Chart................................................................................................................... 42
`Conclusion...................................................................................................................... 61
`Other Matters.................................................................................................................. 61
`
`C.
`XIII.
`XIV.
`
`-iii-
`
`Qualcomm, Ex. 1002, Page 3
`
`

`

`TABLE OF EXHIBITS1
`
`EXHIBIT
`NO.
`
`TITLE
`
`1001
`
`U.S. Patent No. 8,433,940 (’940 Patent)
`
`1003
`
`U.S. Patent No. 6,792,551 (Dai)
`
`1005
`
`’940 Patent Prosecution History
`
`1006
`
`Order Construing Claims, Doc. 404, Qualcomm Inc. v. Apple Inc.,
`No. 3:17-cv-1375 (S.D. Cal. Oct. 11, 2018)
`
`1007
`
`U.S. Patent No. 6,665,802 (Ober)
`
`1008
`
`Alan J. Smith, Cache Memories, 14 COMPUTING SURVEYS 473-530
`(1982)
`
`1009
`
`Hennessy, John L. & Patterson, David A., COMPUTER
`ARCHITECTURE – A QUANTITATIVE APPROACH at 408-425, 467-474
`(1990).
`
`1 Counsel has provided me with numbers corresponding to the exhibits in the
`petition requesting inter partes review of the ’940 Patent. For consistency, I’ve
`used those exhibit numbers.
`
`1
`
`Qualcomm, Ex. 1002, Page 4
`
`

`

`I, Richard A. Belgard, declare and state as follows:
`Introduction
`
`I.
`
`I am making this declaration at the request of Qualcomm Incorporated
`1.
`and Qualcomm Technologies, Inc. (collectively, “Qualcomm”) in connection with
`Qualcomm’s petitions for inter partes review of U.S. Patent No. 8,433,940 (the
`“ʼ940 Patent”) to inventor Lynn Youngs, and assigned to Apple, Inc. I have
`previously worked with Qualcomm, and may continue to do so, in its district court
`case related to the ʼ940 Patent, Case Number 3:17-cv-01375-DMS-MDD.
`2.
`I make this declaration based upon my personal knowledge. I am
`
`over the age of twenty-one and competent to make this declaration. In this
`declaration, I provide an overview of the ʼ940 Patent, the level of ordinary skill in
`the art of the ʼ940 Patent, an overview of certain prior art that discloses the
`elements of the claims of the ʼ940 Patent, and my opinion as to invalidity of the
`ʼ940 Patent. I have been asked by Qualcomm to consider claims 1-4 and 8-11 and
`provide my opinions as to whether these claims (i) were disclosed in certain prior
`art references that predate the earliest effective filing date of the ʼ940 Patent,
`and/or (ii) would have been obvious to a person of ordinary skill in the art at the
`
`time of the invention in view of certain prior art references that predate the
`effective filing date of the ʼ940 Patent.
`3.
`I am being compensated for my time at the usual rate of $650 per
`
`hour. My compensation does not depend in any way on the substance of my
`
`testimony or the outcome of this inter partes review.
`II. Qualifications
`
`4.
`
`I have been active in the computer industry for over 40 years. During
`
`this period, I have designed and/or managed the development of computer
`
`hardware, software and firmware at Burroughs Corporation (now UNISYS), Data
`
`1
`
`Qualcomm, Ex. 1002, Page 5
`
`

`

`General (now part of EMC), Tandem Computers (now part of Hewlett Packard)
`
`and Rational Software (now part of IBM).
`
`5.
`
`I received a Bachelor of Arts degree in Computer Science (1973) and
`
`a Master of Science degree in Electrical Engineering and Computer Science (1974)
`
`from the State University of New York at Buffalo. I attended the University of
`
`Utah in pursuit of a Ph.D. in Computer Science, and completed all necessary
`
`course work, but I chose to join Data General before completing my dissertation.
`
`6.
`
`In 1975, I was appointed a Lecturer in Computer Science at the
`
`University of California at Santa Barbara, where I taught a graduate sequence in
`
`computer architecture. During this same time period, I also worked on the design
`
`of a minicomputer at Burroughs Corporation.
`
`7.
`
`I am now an independent consultant in the computer industry. I
`
`consult primarily with professional and prospective investors, large and small
`
`computer companies, and law firms. As an independent consultant, I have
`
`contributed to the design of at least four microprocessors and additional
`
`microprocessor chipset designs.
`
`8.
`
`I have experience in the field of hardware, software, firmware,
`
`computers, and microprocessors. In addition to many others, I have consulted or
`
`currently consult to: 3Com, Altitude Capital, AT&T, Atmel, Broadcom, Cadence,
`
`Chiaro, Chips and Technologies, Cisco, Dell, EMachines, U.S. Federal Trade
`
`Commission, Gateway, Intergraph, NCR Corporation, NEC Corporation, Micron
`Technology, MicroUnity Systems Engineering, Packard Bell – NEC, Palm
`Computing, Research in Motion, Transmeta, VIA Technologies and Xerox
`
`Corporation. My current resume is attached to this declaration as Appendix 1.
`
`Attached to this declaration as Appendix 2 is a list of trial and deposition testimony
`
`that I have given over the past 7 years to the best of my recollection. Attached as
`
`2
`
`Qualcomm, Ex. 1002, Page 6
`
`

`

`Appendix 3 is a list of my publications, to the best of my recollection, for the last
`
`10 years.
`
`I have been a Fellow of the Institute of Electrical and Electronic
`9.
`Engineers (IEEE) since 2003. My nomination was “[f]or leadership in the
`computer engineering community and contributions to computer micro
`architectures.” I have also been a member of the Association for Computing
`Machinery (ACM) since 1974.
`
`10.
`
`I am a named inventor on 18 U.S. Patents for computer design work I
`
`did at Data General Corporation. I also have been granted 6 patents in the
`
`microprocessor area for work that I have done as an independent consultant.
`
`11.
`
`I have been an invited speaker at seminars on the topic of reverse
`
`engineering in computer-related technology and clean room design, including how
`
`to perform reverse engineering, and how to prevent it. I have also published
`
`articles in both engineering journals and legal publications. I have been a
`
`contributing editor of The Microprocessor Report, an award-winning computer
`
`industry publication, for over 30 years. The Office of Technology Assessment, an
`
`agency chartered by the U.S. Congress, invited me to provide ideas and comments
`
`on issues of intellectual property protection of software.
`
`12.
`
`I have been qualified in court cases and have given testimony as an
`
`expert in computer systems (hardware and software) in the U.S., Hong Kong,
`
`Canada, the U.K., and Germany.
`I have been a “Rule 706” court-appointed expert witness in a
`computer-technology patent case. I have also been a court-appointed expert in the
`
`13.
`
`Superior Court of California, San Mateo County in a computer software trade-
`
`secret case.
`
`3
`
`Qualcomm, Ex. 1002, Page 7
`
`

`

`III. Materials Considered
`
`14.
`
`In forming my opinions, I have relied on my personal knowledge and
`
`experience, including the experience described above in Section II.
`15. My opinions are also based on my review of the ʼ940 Patent (Ex.
`1001), its prosecution history (Ex. 1005), and the following patents and printed
`
`publications:
` U.S. Patent No. 6,665,802 to Robert E. Ober (“Ober”), which was
`filed on February 29, 2000 and issued on December 16, 2003 (Ex.
`
`1007); and
` U.S. Patent No. 6,792,551 to Xia Dai (“Dai”), which was filed on
`November 26, 2001 and issued on September 14, 2004. (Ex. 1003.)
`
`16. Additionally, I have identified documents within this declaration that
`
`confirm my understanding of the state of the art. Those publications include the
`
`following:
` Cache Memories, by Alan J. Smith, Computing Surveys, Vol. 14, No.
`3, September 1982, pp. 473-530 (Ex. 1008); and
` Computer Architecture – A Quantitative Approach, by John L.
`Hennessy and David A. Patterson, © 1990 Morgan Kaufman
`
`Publishers, pp. 408-425 and 467-474. (Ex. 1009.)
`
`I have also considered certain documents from the related litigation
`17.
`concerning the ʼ940 Patent, including the Order Construing Claims, Dkt. 404,
`Qualcomm Inc. v. Apple Inc., No. 3:17-cv-1375 (Oct. 11, 2018). Ex. 1006.
`IV. Relevant Legal Standards
`
`18.
`
`I have requested the attorneys from Jones Day, who represent
`
`Qualcomm, to provide me with guidance as to the applicable patent law in this
`
`matter, and they have done so. The paragraphs below express my understanding as
`
`4
`
`Qualcomm, Ex. 1002, Page 8
`
`

`

`gleaned from their guidance of how to apply current principles related to
`
`patentability to my analysis.
`
`I have been informed that I should assume that April 29, 2002 is the
`19.
`effective filing date of the ʼ940 Patent.
`20.
`I understand that in an inter partes review, the prior art that may be
`
`considered is limited to patents and printed publications.
`
`I understand that, for the purposes of this inter partes review, the
`21.
`terms and phrases of the claims of the ʼ940 Patent should be given their broadest
`reasonable interpretation in light of the claims and the specification of the patent in
`
`which they appear. For the purposes of my analysis, I have interpreted the terms
`and phrases of the claims of the ʼ940 Patent in accordance with their their broadest
`reasonable interpretation.
`
`22.
`
`I understand that a claim is invalid, and unpatentable, as anticipated
`
`under 35 U.S.C. § 102 if the claimed invention was described in a patent or printed
`publication before the invention by the patentee (i.e., is “prior art”). In order to
`anticipate the claimed invention, a single prior art reference must disclose each and
`
`every element of the claim, explicitly or inherently, and it must disclose those
`
`elements arranged as in the claim. I understand that a claim element is disclosed
`
`inherently when the prior art reference must necessarily include or disclose the
`
`unstated element.
`
`23.
`
`It is my understanding that a claim is unpatentable under 35 U.S.C.
`
`§ 103 if the claimed subject matter as a whole would have been obvious to a
`
`person of ordinary skill in the art at the time of invention. I also understand that an
`
`obviousness analysis takes into account the scope and content of the prior art, the
`
`differences between the claimed subject matter and the prior art, and the level of
`
`ordinary skill in the art at the time of the invention.
`
`5
`
`Qualcomm, Ex. 1002, Page 9
`
`

`

`24.
`
`In determining the scope and content of the prior art, it is my
`
`understanding that a reference is considered appropriate prior art for obviousness if
`it falls within the field of the inventor’s endeavor. In addition, a reference is prior
`art if it is reasonably pertinent to the particular problem with which the inventor
`
`was involved. A reference is reasonably pertinent if it logically would have
`presented itself to an inventor’s attention in considering his problem. If a reference
`relates to the same problem as the claimed invention, that supports use of the
`
`reference as prior art in an obviousness analysis.
`
`25.
`
`To assess the differences between prior art and the claimed subject
`
`matter, it is my understanding that 35 U.S.C. § 103 requires the claimed invention
`to be considered as a whole. This “as a whole” assessment requires showing that
`one of ordinary skill in the art at the time of invention, confronted by the same
`
`problems as the inventor and with no knowledge of the claimed invention, would
`
`have selected the elements from the prior art and combined them in the claimed
`
`manner.
`
`26.
`
`It is my further understanding that the law recognizes several
`
`rationales for combining references or modifying a reference to show obviousness
`
`of claimed subject matter. Some of these rationales include: combining prior art
`
`elements according to known methods to yield predictable results; simple
`
`substitution of one known element for another to obtain predictable results; a
`
`predictable use of prior art elements according to their established functions;
`
`applying a known technique to a known device (method or product) ready for
`
`improvement to yield predictable results; choosing from a finite number of
`
`identified, predictable solutions, with a reasonable expectation of success; and
`
`some teaching, suggestion, or motivation in the prior art that would have led a
`
`person of ordinary skill in the art to modify the prior art reference or to combine
`
`prior art reference teachings to arrive at the claimed invention. I further
`
`6
`
`Qualcomm, Ex. 1002, Page 10
`
`

`

`understand that choosing between a small number of predictable solutions requires
`
`only ordinary skill in the art and common sense, rather than innovation.
`
`27.
`
`I understand that when a patent incorporates another patent by
`
`reference, it is to be treated as if the referenced patent is included within the
`
`referencing patent just as if it were attached to the referencing specification.
`
`28.
`
`I have been informed that any relevant differences between the prior
`
`art and the claimed invention are to be analyzed from the view of a person of
`
`ordinary skill in the art at the time of the invention. As such, in forming my
`
`opinions below, I have placed myself in the position of a person of ordinary skill in
`
`the art are as of the time of the invention: April 29, 2002. Considering the state of
`
`the art and the knowledge of a person of ordinary skill in the art at the time of
`
`invention prevents improper reconstruction of the claimed invention with the
`
`benefit of hindsight.
`V.
`Summary of Opinions
`
`29.
`
`In my opinion, the claims at issue here, claims 9-11 and 15 are
`
`rendered obvious by Ober in view of Dai.
`VI. Relevant Technology and ʼ940 Patent
`
`A.
`
`30.
`
`Dynamic vs. Static Power Consumption
`
`The hardware circuitry of typical computer processors and processing
`
`systems operates by a combination of millions, hundreds of millions, or even
`
`billions of transistors, each operating as an electronic switch. A combination of
`
`these transistors, with additional electrical circuits and additional software, controls
`
`the switches to perform binary (i.e., off, represented by 0, or on, represented by 1)
`
`operations. Together, these binary operations are combined to perform logic
`
`functions and circuits, called logic gates. These logic gates are then combined to
`
`form arithmetic units, registers, memories, instruction processing pipelines and
`
`7
`
`Qualcomm, Ex. 1002, Page 11
`
`

`

`input/output, among many others. Virtually all circuitry in a computer processor
`
`involved and continues to utilize these switches.
`In the early 1960’s, a switch technology that utilized two
`complementary technology transistors to form a switch. The technology was
`
`31.
`
`called CMOS technology, standing for Complementary Metal Oxide
`
`Semiconductor. CMOS was a great improvement in lowering power over earlier
`
`switch technology. Power is the arithmetic product of current and voltage.
`
`32. CMOS, in theory, only required current to flow when the switches
`
`were changing state, i.e., from on-to-off or from off-to-on. The earlier switch
`
`technology (using technologies called NMOS and PMOS) consumed power all the
`time – whether the switches were changing state or not. Because of the
`tremendous savings in electrical power, CMOS technology is still used today in
`
`almost every processor and processing system.
`
`33. When CMOS switches change state, from off-to-on (zero to one), or
`
`vice versa, they consume electric power because current momentarily flows
`
`through the transistors. This current causes power dissipation and this power is
`
`known as dynamic power.
`
`34. However, due to the CMOS arrangement of two complementary-
`
`technology transistors in each switch, when the switches are not changing state,
`
`theoretically no current flows, and the switches consume (theoretically) no power.
`
`However, these transistors actually do consume some power, although extremely
`
`small compared to dynamic power, due to physics and the physical implementation
`
`of the transistors themselves. The power that is dissipated when the transistors
`
`(and circuits) of CMOS switches when not switching is called static power.
`
`35. At any point in time in a processor many, and sometimes most,
`
`transistors are not switching. Therefore, reducing static power becomes important,
`
`especially as the number of transistors in the processors increases dramatically
`
`8
`
`Qualcomm, Ex. 1002, Page 12
`
`

`

`over generations of processors. Furthermore, as the scaling of transistor and circuit
`
`size has gotten smaller and smaller, static power dissipation becomes an important
`
`factor, especially in portable, battery-operated devices (such as laptops and cell
`
`phones). Static power consumption continues to be a problem today.
`B.
`Cache, Cache Tags, Cache Coherency & Snooping
`
`36.
`
`A cache, or more accurately, cache memory, is a small, fast memory
`
`structure located close to the core of a processor that is used to hold the most-
`
`recently accessed data, typically for subsequent use. Caches have been a
`cornerstone of computer processors since the 1960s.2 When the logic in a core
`requests data from memory, it consults the cache to see if that data has already
`
`been encached. If it has, then the cache delivers the data quickly to the core. If it
`has not, a so-called “cache-miss” occurs, and the data has to be retrieved from the
`next level of memory further from the core.
`
`37. Caches copy (or move) data from larger, slower memory locations
`into a smaller, faster memory that is called “closer to the processor” because
`caches, and therefore cached data, are more easily accessible to the processing
`
`elements that need it than the next further-away level of memory. The situation is
`similar to the relationship between a computer’s main memory and its hard disk
`drive – the hard disk can hold more information than main memory, but it is slower
`and “further away” from the processing elements that need the information than
`the main memory.
`
`2 For an early treatise on caches, see “Cache Memories” by Alan J. Smith,
`Computing Surveys, Vol. 14, No. 3, September 1982, pp. 473-530; Alternatively,
`see: Computer Architecture – A Quantative Approach, by John L. Hennessy and
`David A. Patterson, © 1990 Morgan Kaufman Publishers, pp. 408-425 and 467-
`474.
`
`9
`
`Qualcomm, Ex. 1002, Page 13
`
`

`

`38.
`
`There are many types and organizations of caches. However, because
`
`cache memories are inherently smaller than the memories whose data they
`
`encache, and the encached data is not generally linear, but scattered, there needs to
`
`be a way to address data in the cache, and, as well, determine if the requested data
`
`is in the cache at all. This checking and locating is done through an auxiliary
`structure common to, and inherent in, every cache, called “cache tags.”
`39. Cache memories, due to their nature of being smaller than the next
`
`level of memory that they encache, cannot hold data from all memory addresses.
`
`So, when a block of memory is encached in a cache, a location in the cache
`
`memory must be chosen to hold it. That position, called the block or line in the
`
`cache, is typically located by using at least some of the lower portion of the full
`
`memory address. So, for example, data with a full memory location of 12345600
`could be cached in the cache at block address 456.
`40. However, different data with a different full memory location of, for
`
`example, 78945600 would also be cached in the cache at block address 456. The
`way to determine whether the cached data corresponds to the first data (i.e., with
`
`an address of 12345600), or the second data (i.e., with an address of 78945600), or
`
`some other data with yet a different address is via a cache tag comparison.
`
`41. Cache tags are ancillary memory inherent to all caches. Cache tags
`
`contain the remainder of the address of the memory location contained at a line or
`
`block in the cache, given that the index of the address determines its location in the
`
`cache, and is the remainder of the salient portion of the memory address. In the
`
`examples above, the cache tag for the cache location 456 would contain 123 if the
`
`first data was encached there, and would contain 789 if the second data was
`
`encached there. It could also be the case that the tag could contain something
`
`different from each if the cache were encaching different data than either. Further,
`
`10
`
`Qualcomm, Ex. 1002, Page 14
`
`

`

`the location in the cache could also not have any valid data, and caches also have
`
`an additional single bit, a valid bit, associated with the block location in the cache.
`
`42.
`
`It is important to note that there are various organizations of cache
`
`memories, where, for instance, multiple addresses with the identical index portion
`
`(in the examples above, 456) could be encached simultaneously, in different so-
`called “sets” of the cache. In order determine whether these caches encache
`specific memory locations, the cache tags (and valid bits) of each set must be
`
`compared to the tag memory address portion. Regardless of specific cache
`
`organization, every cache inherently has cache tags.
`
`43.
`
`In some processor organizations, caches hold copies of data from the
`
`main memory. When the cache is filled with data, the data from memory is copied
`
`into the cache. When the data is subsequently changed by the processor core, it is
`
`written immediately to the cache, and, simultaneously, but more slowly, written
`
`back to the memory. These types of caches are called write-through caches,
`because the data is “written through” the cache to the memory.
`44. Other processor organizations prefer to use what are called a “write-
`back” scheme for caching. In a write-back cache organization, data is copied into
`the cache when the cache is filled with data, just as in the write-through scheme.
`
`However, when the data is changed by the processor core, the data is only changed
`in the cache, and not written “through” into the memory. If and when necessary,
`such as when the locations in the cache are needed for caching different data, the
`
`data block from the cache is written back to the memory all at once. Hence the
`name “write-back” cache. In such a scheme, it is obvious that at certain points in
`time, data in the cache will be the correct data, but the data in the memory
`
`corresponding to the locations encached will be stale, and contain inconsistent and
`
`incorrect data.
`
`11
`
`Qualcomm, Ex. 1002, Page 15
`
`

`

`45. Cache coherency is the situation which ensures that the changes in the
`
`values of cached data are propagated throughout the system so that it is correct
`
`when it is used. It is particularly important in systems that have multiple
`
`processors, each with its own cache[s], but sharing a single common memory.
`
`46.
`
`Suppose that some processor has a cached copy of memory location
`
`12345600, and suppose that a different agent, either a different processor sharing
`
`the same memory, or an input-output device, changes the memory. Somehow, the
`
`initial processor (with the cached version) must be notified that the copy of the
`
`memory it has is incorrect, and stale. Similarly, if the different agent attempts to
`
`read a location of memory that is encached by a different processor, the agent must
`
`somehow be notified that it cannot read the data from memory because it is stale,
`and the current version of the data is in the other processor’s cache. One method
`of guaranteeing that all agents in a system that supports caching will maintain
`
`coherency is via a method called cache snooping.
`
`In the method of cache snooping, when an agent writes to the shared
`47.
`memory, the memory address that is being written is “snooped” among all the
`other sharers of the memory. The protocol provides a query, essentially stating, “if
`you have this address cached, invalidate your entry because I just changed the data
`at that address.”
`48.
`Similarly, in a system with multiple agents sharing a memory, before
`
`one agent can encache data from the memory, it must essentially ask all other
`sharing agents, “do you have this data encached, and is it dirty, because, I want a
`copy of the most recent data?” Again, this is part of the snooping protocol to cache
`coherency.
`
`49. All of the cache organizations, tagging and coherency protocols
`
`described above would have been very well known to a person of ordinary skill in
`
`the art as of April, 2002.
`
`12
`
`Qualcomm, Ex. 1002, Page 16
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`

`

`C.
`
`Processors, Microprocessors, Microcontrollers and CPUs
`
`50. As noted above, the specification of the ʼ940 Patent describes
`conserving power by reducing the voltage to a portion of the processor that
`processes instructions. The term “Processor” is generic, and a person of ordinary
`skill in the art in 2002 would generally understand “processor” to include
`mainframe computers, minicomputers, microcomputers, microprocessors, and
`
`microcontrollers.
`
`51.
`
`In essence, the evolution of the processors described above was based
`
`primarily on the increase of the integration of elements of the processors into fewer
`and fewer packages. Indeed, the processors that are contained within today’s cell
`phones have integrated much, if not all of the functional component parts of the
`
`mainframe computers of the 1960s.
`52. Central Processing Units, or “CPUs,” are at the center of the
`processors, and are the “brains” of those processors. As of 2002, they invariably
`included subcomponents that processed arithmetic, logic, control and often
`
`specialized instructions. The components that processed instructions were in the
`“execution units” of the processors and were called, among others, arithmetic logic
`units (or “ALUs”), register files, control logic, and pipelines.
`53. By 2002, most processors also included at least level 1 caches (“L1
`caches”), and sometimes also included level 2 caches (although the placement of
`L2 caches may have varied from processor to processor).
`VII. Claim Construction
`
`A.
`
`“power area”
`
`I understand that the district court in the related litigation determined
`54.
`that the term “power area” should be given its plain and ordinary meaning.
`
`13
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`Qualcomm, Ex. 1002, Page 17
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`

`

`55. While I understand that the district court’s construction is not binding
`in this inter partes review, I have applied this construction in my analysis.
`VIII. Person of Ordinary Skill in the Art
`
`56.
`
`I understand that a patent claim should be interpreted based on what it
`
`would mean to a person of ordinary skill in the art as of the filing date of the
`
`patent.
`
`57.
`
`The ʼ940 Patent is in the electrical engineering discipline, and directed
`primarily to the minimization of power consumption in a processor. A familiarity
`
`with hardware components of a processor, general processor power management,
`
`processor microarchitecture and at least a general familiarity with static and
`dynamic power consumption are necessary to understand the ʼ940 Patent.
`58. Accordingly, in my opinion, the ʼ940 Patent was addressed to a
`person having a bachelor’s degree in electrical engineering or computer science
`and having at least a few years of experience in, or knowledge of, processor design
`
`in the 2002 time-frame. Additional education could substitute for less work
`
`experience, and, likewise, subs