Paper No. 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`__________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`__________________
`
`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES,
`INC.
`
`Petitioners
`
`v.
`
`APPLE INC.
`
`Patent Owner
`
`U.S. PATENT NO. 8,433,940
`
`TITLE: CONSERVING POWER BY REDUCING VOLTAGE
`SUPPLIED TO AN INSTRUCTION-PROCESSING PORTION
`OF A PROCESSOR
`
`Issue Date: April 30, 2013
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. § 312
`
`-i-
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`TABLE OF CONTENTS
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`Page
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`B.
`
`
`Introduction ................................................................................................... 1
`I.
`II. Mandatory Notices........................................................................................ 4
`A. Real Party in Interest (37 C.F.R. § 42.8(b)(1)) ................................ 4
`B. Related Matters (37 C.F.R. § 42.8(b)(2)) .......................................... 4
`C.
`Lead and Back-Up Counsel and Service Information (37
`C.F.R. § 42.8(b)(3) and (b)(4)) ........................................................... 5
`Fees (37 C.F.R. § 42.103) ................................................................... 6
`D.
`III. Grounds for Standing (37 C.F.R. § 104(a)) ................................................ 6
`IV. Statement of Precise Relief Requested for Each Challenged Claim ........ 6
`A.
`The Claims for Which Review Is Requested (37 C.F.R.
`§ 42.104(b)(1)) .................................................................................... 6
`The Specific Statutory Grounds on Which the Challenge Is
`Based and Prior Art Relied Upon for Each Ground (37
`C.F.R. § 42.104(b)(2)) ......................................................................... 7
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2)
`and 42.104(b)(4) ............................................................................................ 8
`A. Overview of the ’940 Patent and its Technology ............................. 8
`B.
`The Prosecution History of the ’940 Patent ................................... 10
`C.
`37 C.F.R. § 42.104(b)(3): Claim Construction .............................. 13
`1.
`A Person of Ordinary Skill in the Art .................................. 13
`2.
`Construction of Claim Terms ............................................... 14
`3.
`“Power area” .......................................................................... 15
`D. Detailed Overview of the Prior Art ................................................ 15
`1.
`Ober ......................................................................................... 15
`2.
`Dai ............................................................................................ 18
`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable ..................................................................................... 19
`37 C.F.R. § 42.104(b)(5): Supporting Evidence ............................ 20
`
`E.
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`F.
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`TABLE OF CONTENTS
`(continued)
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`Page
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`VI. There Is a Reasonable Likelihood That Claims 9-11 and 15 of the
`’940 Patent Are Unpatentable ................................................................... 20
`A. Ground 1: Claims 9-11 and 15 are Obvious over Ober in
`view of Dai ......................................................................................... 20
`Reasons to Combine Ober and Dai ................................................. 20
`VII. Conclusion ................................................................................................... 46
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`I.
`
`Introduction
`
`Pursuant to 35 U.S.C. § 312 and 37 C.F.R. § 42.100 et seq., Qualcomm Inc.
`
`and Qualcomm Technologies, Inc. (collectively, “Petitioners” or “Qualcomm”)
`
`request inter partes review of claims 9-11 and 15 (the “Challenged Claims”) of U.S.
`
`Patent No. 8,433,940 (“the ʼ940 Patent,” Ex. 1001), which issued on April 30, 2013
`
`and is assigned to Apple, Inc. (“Patent Owner” or “Apple”).
`
`The ’940 Patent is directed to a processor with two separate “power areas.” Ex.
`
`1001 at cl. 9. The claims require separate “core power” and “non-core power” areas
`
`within the processor, and the claims recite various components in the architecture
`
`within each area. Id. at cl. 9. Figure 1A of the ’940 Patent depicts the “core power
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`area” and “non-core power area” of the Challenged Claims:
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`The specification of the ’940 Patent purports to describe an invention in which
`
`voltage is reduced in the core power area in order to reduce the processor’s static
`
`power leakage. Ex. 1001 at Abstract. Nevertheless, the Challenged Claims of the
`
`’940 Patent do not recite or require any reduction in voltage. Ex. 1001 at cls. 9-11,
`
`15. Instead, the Challenged Claims recite only that “the non-core power area is
`
`configured to be operable while instruction processing is halted in the core power
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`area.” Ex. 1001 at cl. 11.
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`Halting a portion of a processor while the remaining portion of that processor
`
`remains operable was well known in the art as of the earliest effective filing date. For
`
`one, the specification of the ’940 Patent recognizes that halting a portion of a
`
`processor was a well-known technique for reducing power consumption:
`
` “Designers have taken advantage of this fact by reducing the frequency
`of (or halting) clock signals to certain portions of a processor when the
`processor is idle.” Ex. 1001 at 1:43-45.
` “[C]lock distribution to core power area 126 can be stopped while the
`clock signals to non-core power area 124 continue. The acts of starting
`and stopping these clock signals are known in the art and will not be
`described further.” Ex. 1001 at 3:43-45.
`Indeed, independent control of the clock to separate power areas is described
`
`in many prior art references, including U.S. Patent No. 6,665,802 to Robert E. Ober
`
`(“Ober”), which was not of record during prosecution of the ’940 Patent. Moreover,
`
`the partitioning of a processor into power areas with independent clock control was
`
`also disclosed by U.S. Patent No. 6,792,551 (“Dai”) (Ex. 1003). As explained in more
`
`detail below, Dai was considered during prosecution of related U.S. Patent No.
`
`7,383,453 (“’453 Patent”), but was not cited during prosecution of the ’940 Patent.1
`
`
`1 Moreover, the grounds on which Dai was overcome with respect to the ʼ453
`Patent (i.e., the assertion Dai does not disclose multiple power-saving modes in a
`single embodiment) are not applicable to the claims of the ʼ940 Patent (which only
`requires a single power-saving mode).
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`The other aspects of the Challenged Claims, which recite conventional
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`elements of a processor, likewise were well known in the art as of the April 2002. In
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`fact, the Examiner rejected the claims of the application leading to the ʼ940 Patent on
`
`the grounds that the configuration of the described components would have been
`
`obvious to a person of ordinary skill in the art over U.S. Patent No. 7,539,878 to
`
`Vaglica (“Vaglica”) (Ex. 1004). Ex. 1005 at 103-10. Notably, the Applicant’s claims
`
`to the processor configuration recited in claim 9 were not allowed until he amended
`
`the claim to include the “halting” limitation described above—the very limitation that
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`the ʼ940 Patent describes as “known in the art.” Ex. 1001 at 3:43-45.
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`Furthermore, as explained herein, the Challenged Claims are unpatentable
`
`based upon Ober and Dai. See Section VI, infra. Because the Challenged Claims are
`
`unpatentable, inter partes review should be instituted and the Challenged Claims
`
`should be cancelled.
`
`II. Mandatory Notices
`
` Real Party in Interest (37 C.F.R. § 42.8(b)(1))
`Qualcomm Inc. and Qualcomm Technologies, Inc. are the real parties-in-
`
`interest.
`
` Related Matters (37 C.F.R. § 42.8(b)(2))
`The ’940 Patent and a related patent are involved in the following proceeding
`
`that may affect or be affected by a decision in this proceeding: Qualcomm Inc. et al.
`
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`v. Apple Inc., Case No. 3:17-cv-1375 (S.D. Cal.) (“’1375 Case”). Qualcomm is
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`concurrently filing a separate petition challenging claims of U.S. Patent No.
`
`7,383,453, which is in the same family, and shares a specification with, the
`
`ʼ940 Patent.
`
` Lead and Back-Up Counsel and Service Information (37 C.F.R.
`§ 42.8(b)(3) and (b)(4))
`Lead Counsel
`John A. Marlott,
`jamarlott@jonesday.com
`Reg. No. 37,031
`JONES DAY
`77 West Wacker Dr.
`Chicago, IL 60601
`(312) 269-4240
`
`
`Back-up Counsel
`John M. Michalik,
`jmichalik@jonesday.com
`Reg. No. 56,914
`Thomas W. Ritchie,
`twritchie@jonesday.com
`Reg. No. 65,505
`JONES DAY
`77 West Wacker Dr.
`Chicago, IL 60601
`(312) 269-4215
`
`Matthew W. Johnson,
`mwjohnson@jonesday.com
`Reg. No. 59,108
`JONES DAY
`One Mellon Center
`500 Grant Street
`Pittsburgh, PA 15219
`(412) 394-9524
`
`Pursuant to 37 C.F.R. § 42.10(b), a Power of Attorney accompanies this
`
`
`
`Petition. Please address all correspondence to lead and back-up counsel at the address
`
`above. Qualcomm also consents to electronic service by email at the email addresses
`
`listed above.
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`
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`Fees (37 C.F.R. § 42.103)
`The undersigned representative of Petitioners authorizes the Board to charge
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`the $15,500 Petition Fee, as well as any additional fees, to Deposit Account 501432,
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`ref: 178774-680001. Four claims are being reviewed, so $15,000 in post institution
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`fees are due for a total of $30,500.
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`III. Grounds for Standing (37 C.F.R. § 104(a))
`
`Petitioners certify that the ʼ940 Patent is available for inter partes review, and
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`that Petitioners are not barred or estopped from requesting inter partes review of the
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`Challenged Claims on the grounds identified in this Petition. Apple filed and served
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`its first amended answer and counterclaims in the ’1375 Case, first asserting
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`infringement of the ʼ940 Patent by Petitioners, on November 29, 2017. This petition
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`is being filed within one year of service of Apple’s first amended answer and
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`counterclaims, and shortly after the District Court issued a claim construction order
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`adopting certain of Apple’s positions regarding the breadth of the ʼ940 Patent.
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`IV. Statement of Precise Relief Requested for Each Challenged Claim
`
` The Claims for Which Review Is Requested (37 C.F.R.
`§ 42.104(b)(1))
`Petitioners request review and cancellation of claims 9-11 and 15 of the ʼ940
`
`Patent (the “Challenged Claims”).
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`-6-
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`The Specific Statutory Grounds on Which the Challenge Is Based
`B.
`and Prior Art Relied Upon for Each Ground (37 C.F.R. § 42.104(b)(2))
`
`Petitioners request interpartes review ofthe Challenged Claims on the grounds
`
`set forth below and request that the Challenged Claims be found unpatentable- An
`
`explanation of how the Challenged Claims are unpatentable under the statutory
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`identified grounds is provided in the form of the detailed description that follows,
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`indicating where each of the claim elements can be found and the relevance of the
`
`prior art. Additional explanation and support for each ground of rejection is set forth
`
`in Ex. 1002, referenced throughout this Petition.
`
`Ground
`
`9-11, 15
`
`’940 Patent Claims —
`
`35 U.S.C- § 103(a) based on Ober in View of
`Dai.
`
`The ’940 Patent
`
`issued on April 13, 2013 from US. Application No.
`
`13/433,246 (“’246 App”), filed March 28, 2012. The ’940 Patent is a continuation
`
`ofUS. Application No. 12/ 103,349 (filed on April 15, 2008), which was subsequently
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`granted as US. Patent No. 8,166,324 (“’324 Patent”).
`
`The ’324 Patent
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`is a
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`continuation of US. Application No. 11/213,215 (filed on August 25, 2005), which
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`was subsequently granted as the ’453 Patent. The ’453 Patent is a continuation of
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`US. Application No. 11/ 103,911 (filed on April 11, 2005), which was subsequently
`
`granted as US. Patent No. 6,973,585 (“the ’585 Patent”)- The ’585 Patent is a
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`continuation of US. Application No. 10/1 35,] 16 (filed on April 29, 2002), which was
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`subsequently granted as US. Patent No. 6,920,574. Accordingly, the earliest date to
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`

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`which the ʼ940 Patent could claim priority (hereinafter the “earliest effective filing
`
`date”) is April 29, 2002.
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`Ober was filed on February 29, 2000 and issued on December 16, 2003, and is
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`prior art under pre-AIA 35 U.S.C. § 102(e). Dai was filed on November 26, 2001 and
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`issued on September 14, 2004, and is prior art under pre-AIA 35 U.S.C. §§ 102(e).
`
`V. Reasons for the Relief Requested Under 37 C.F.R. §§ 42.22(a)(2) and
`42.104(b)(4)
` Overview of the ’940 Patent and its Technology
`The ʼ940 Patent relates to a method and architecture for reducing power
`
`consumption in an instruction-processing system. Ex. 1001 at Title. The specification
`
`for the ’940 Patent acknowledges that “reducing the frequency of (or halting) a system
`
`clock signal can reduce the dynamic power consumption of a processor,” and was
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`commonly used as a means of power conservation before the earliest effective filing
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`date. Ex. 1001 at 1:43-45. However, according to the ’940 Patent, methods and
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`architectures for “reduc[ing] static power consumption for a processor in a battery
`
`operated computing device” were not well understood. Id. at 1:59-61. Therefore, the
`
`’940 Patent purports to describe an invention directed to “a system that facilitates
`
`reducing static power consumption of a processor.” Ex. 1001 at 1:65-67. However,
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`as explained below, the Challenged Claims are directed only to halting the claimed
`
`processor and thus reducing dynamic power consumption, as was already known in
`
`the art.
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`To achieve power savings, the ʼ940 Patent describes a processor divided into
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`two “power areas”: a “core power area 126” and a “non-core power area 124.” Ex.
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`1001 at Fig. 1. The “core power area 126 includes the instruction-processing portion
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`of the processor” and the “non-core power area comprises the remaining portion of
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`[the] processor.” Id. at 3:5-6. Figure 1A of the ’940 Patent depicts the embodiment
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`recited in the Challenged Claims:
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`According to the specification, reducing (or halting) the clock to the core power
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`area is a well-known means of reducing dynamic power consumption. Id. at 1:43-45.
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`Static power consumption, on the other hand, is reduced by lowering the voltage to a
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`portion of the instruction-processing system. Ex. 1002
`
`
`The Prosecution History of the ’940 Patent
`The ’940 Patent was filed on March 28, 2012 as a continuation of the ’324
`
`Patent. Independent claim 9 of the original application recited a “core power area”
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`coupled to a “non-core power area,” with the components of each “power area” as
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`shown in Figure 1A of the specification.2 Original claim 9 recited no limitations
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`relating to “halting” a portion of the processor. Ex. 1005 at 46. However, original
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`claim 11 recited “predetermined operating modes, [in which] the non-core power area
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`is configured to be operable while instruction processing is halted in the core power
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`area.” Ex. 1005 at 46.
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`On August 6, 2012, the Examiner issued a Non-Final Rejection, asserting that
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`the claims were unpatentable as obvious over U.S. Patent No. 7,539,878 to Vaglica
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`(“Vaglica”). The Examiner found, with respect to original independent claim 1, that
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`Vaglica disclosed a “core power area” and a “non-core power area” with the claimed
`
`elements, other than “a non-core power area comprising a real-time clock and a core
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`2 This is also the same configuration recited in the Challenged Claims.
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`power area comprising an L2 cache; one or more L1 caches; cache tags; and snoop
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`circuitry.” Ex. 1005 at 105-06, 109. Additionally, the Examiner stated that Vaglica
`
`teaches register files in a “core power area,” rather than in a “non-core power area.”
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`Ex. 1005 at 106, 109. Although original independent claim 9 differed from original
`
`independent claim 1, the Examiner stated that claim 9 was obvious for the reasons
`
`stated with respect to claim 1.3 Ex. 1005 at 109. Moreover, with respect to original
`
`independent claim 9, the Examiner noted that:
`
`Vaglica further teaches selectively removing power to elements of the
`CPU that are not critical for coming out of powerdown. Therefore, one
`of ordinary skill in the art could easily modify Vaglica’s system by
`removing power to different elements that were decided not critical for
`coming out of powerdown. This would result in VD1 and VD2 being
`provided to different elements depending on what is determined as
`critical. Consequently, one of ordinary skill in the art would be able to
`include the various elements in claim 9 in the claimed power areas.
`
`Ex. 1005 at 109 (citation omitted) (emphasis in original).
`
`On October 18, 2012, the Applicant responded to the Non-final Rejection. The
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`Applicant’s response did not include any claim amendments. The Applicant instead
`
`
`3 Original claim 1 recited that the core power area includes an L2 cache, cache
`tags, and snoop circuitry. In original claim 9 (and in the Challenged Claims), the
`L2 cache, cache tags, and snoop circuitry are recited as being part of the non-core
`power area.
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`argued that “Vaglica does not describe or suggest ‘a processor, comprising a core
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`power area … comprising … one or more register files’ such as independent claims
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`1 and 9.” Ex. 1005 at 130 (emphasis in original). The Applicant instead argued that
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`Vaglica disclosed register files in the non-core power area. Ex. 1005 at 130-32.
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`Additionally, the Applicant argued:
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`As far as Applicant is aware, there are no references that describe the
`particular arrangement of elements in the independent claims (and
`hence, the particular arrangement of elements is first described in the
`instant application). Applicant avers, therefore, that Examiner has
`erred in arguing that the arrangement of elements is common
`knowledge because the facts asserted to be well-known, or to be
`common knowledge in the art, are not “capable of such instant and
`unquestionable demonstration as to defy dispute.”
`
`Ex. 1005 at 132.
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`The Examiner and the Applicant participated in an Examiner-initiated
`
`interview on December 22, 2012. Ex. 1005 at 138-42. According to the summary of
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`that interview, the Examiner proposed amending the independent claims to “further
`
`define the function of each ‘area.’” The Examiner and Applicant agreed that the
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`application would be in condition for allowance if the following limitation was added
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`to independent claims 1 and 9: “wherein, in predetermined operating modes, the non-
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`core power area is configured to be operable while the core power area is halted.”
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`Ex. 1005 at 142.
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`On December 31, 2012, the Examiner issued a Notice of Allowance for claims
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`including the preceding limitation in independent claims 1 and 9 via an Examiner’s
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`Amendment. Ex. 1005 at 143-46.
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`Neither of the references relied upon in this petition was discussed during
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`prosecution of the ʼ940 Patent. However, Dai was discussed in the predecessor
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`application for U.S. Patent No. 7,383,453 (“’453 Patent). Specifically, the Examiner
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`rejected claims in the ʼ453 Patent as unpatentable in view of Dai. In order to overcome
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`the rejection, the Applicant noted that Dai does not disclose an embodiment in which
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`a processor is capable of entering multiple power-saving modes. Ex. 1010 at 164-65.
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`Notably, however, the claims of the ʼ940 Patent do not recite multiple power-saving
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`modes. Instead, independent claim 9 of the ʼ940 Patent recites only a single power-
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`saving mode. Ex. 1001 at cl. 9. Thus, the grounds on which the Applicant overcame
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`Dai during prosecution of the ʼ453 Patent do not apply to the claims of the ʼ940 Patent.
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`
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`37 C.F.R. § 42.104(b)(3): Claim Construction
`1.
`A Person of Ordinary Skill in the Art
`Petitioners maintain that a person of ordinary skill in the art (“POSITA”) as of
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`April 29, 2002 would have had a bachelor’s degree in electrical engineering or
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`computer science and would have had at least a few years of experience in, or
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`knowledge of, processor design. Additional education could substitute for less work
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`experience. Alternatively, substantial work experience could substitute for some of
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`the educational background. Ex. 1002 ¶¶ 56-59.
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`2.
`Construction of Claim Terms
`In this IPR, the claims of the ’940 Patent “shall be given the broadest
`
`reasonable construction in light of the [’940 Patent’s] specification.” 37 C.F.R.
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`§ 42.100(b). Because a district court applies a different standard, however, the claim
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`constructions presented in this petition do not necessarily reflect the constructions
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`that Petitioners believe should be adopted by a district court.
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`In the ’1375 Case, the District Court adopted certain of Apple’s claim
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`construction positions. Ex. 1006 at 9-11. Petitioners have submitted the District
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`Court’s claim construction decision for the Board’s consideration. Power
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`Integrations, Inc. v. Lee, 797 F.3d 1318, 1326-27 (Fed. Cir. 2015) (“The fact that the
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`Board is not generally bound by a previous judicial interpretation of a disputed claim
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`term does not mean, however, that it has no obligation to acknowledge that
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`interpretation or to assess whether it is consistent with the broadest reasonable
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`construction of the term.”). Although Petitioners reserve the right to appeal or
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`otherwise challenge the District Court’s claim construction order, Petitioners request
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`that the Board in this IPR construe any claim terms at least as broad as the District
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`Court. See, e.g., Cisco Systems, Inc. v. Crossroads Systems, Inc., IPR2014-01463,
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`Final Written Decision, Paper 49 at 11-12 (PTAB, Mar. 16, 2016) (“Petitioners argue
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`that the ‘control access’ limitations ‘should be at least as broad as the District Court’s
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`construction… We agree with Petitioners.”).
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`3.
`“Power area”
`In the ʼ1375 Case, the District Court determined that the term “power area”
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`should be given its plain and ordinary meaning. Ex. 1006 at 7. For purposes of this
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`inter partes review, Petitioners maintain that the Board should construe this term
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`according to its plain and ordinary meaning as the District Court did. Id.
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` Detailed Overview of the Prior Art
`1. Ober
`Ober is titled “Power Management and Control for a Microcontroller.” Ex.
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`1007 at Title. Ober discloses a “power management architecture [which] includes a
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`power management state machine for controlling the power mode of the central
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`processing unit (CPU) and each of the subsystems within the microcontroller.” Id. at
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`2:55-59. Although Ober repeatedly refers to a “microcontroller,” the specification
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`makes clear that “the term ‘microcontroller’ is deemed interchangeable with any
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`System-on-Chip (SoC).” Id. at 4:13-15. The specification for Ober describes the
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`benefits of the invention as including “increased battery life for portable
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`microcontrolled devices” (Id. at 4:38-43), much like the specification of the ʼ940
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`Patent (Ex. 1001 at 1:59-61).
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`As reproduced below, the microcontroller described in Ober includes a CPU
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`core (shaded green) coupled via a system bus to various components in the non-core
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`power area (shaded red):
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`
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`Ex. 1007 at Fig. 1 (annotated).
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`The area includes an interrupt control unit and a power manager, among other
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`subsystems. Id. at 5:50-57; Fig. 1; see generally Ex. 1002 ¶¶ 64-73. Many of these
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`components are shown in Figure 1 above.
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`Ober’s design allows for configurable power modes which enable “the ability
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`of the system to maintain its state without data loss during battery discharge
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`conditions.” Ex. 1007 at 5:6-10; see Table 8. Among other things, Ober discloses
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`(i) a normal operation mode (“RUN” mode, highlighted in purple box) in which all
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`units are powered and all clocks are operating, and (ii) a first power-saving mode
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`(“IDLE” mode, highlighted in yellow box) in which the clock to the CPU is turned
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`off without any change in voltage to the CPU. Id. at Table 8. The Table below
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`describes these power-saving modes:
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`Id. at Table 8.
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`2.
`Dai
`Dai is titled “Method and Apparatus for Enabling a Self-Suspend Mode for a
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`Processor.” Ex. 1003 at Title. Much like the ʼ940 Patent, Dai is directed to, among
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`other things, addressing problems of “reduc[ed] battery life in mobile systems” (Ex.
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`1003 at 1:30) including through reductions in “leakage current” (Id. at 1:50-54).
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`Dai describes a processor with “two or more voltage supply input ports to
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`receive two or more voltages from one or more voltage regulators.” Ex. 1003 at 3:3-
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`5; see generally Ex. 1002 ¶¶ 74-80. One of the voltage supplies (V(ssm)) is provided
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`to “L2 cache 255, snoop controller (SC) 258,” and other components of the “non-core
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`power area” (shaded in red below). Ex. 1003 at 3:6-7. The other voltage supply
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`(V(core)) is provided to “L1 cache 260, core 265,” and other components of the “core
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`power area” (shaded in green below). Ex. 1003 at 3:8-10. Moreover, Dai provides
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`that the core may include a “pipeline,” including “execution units and registers for
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`executing instructions.” Ex. 1003 at 3:10-11. Many of these components are
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`represented in Dai’s Figure 2, which is reproduced below.
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`Dai discloses various modes which may be entered in order to save power by
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`turning off the clock to the core and/or reducing either V(core) or V(ssm). See
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`generally Ex. 1003 at 4:55-6:12.
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`37 C.F.R. § 42.104(b)(4): How the Construed Claims are
`Unpatentable
`An explanation of how claims 9-11 and 15 are unpatentable, including
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`identification of how each claim feature is found in the prior art, is set forth below in
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`Section VI.
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`37 C.F.R. § 42.104(b)(5): Supporting Evidence
`An Appendix of Exhibits supporting this Petition is attached. Included as
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`Exhibit 1002 is a Declaration of Richard Belgard under 37 C.F.R. § 1.68. In addition,
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`the relevance of the evidence to the Challenged Claims, including an identification of
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`the specific portions of the evidence supporting the challenge, is included in Section
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`VI.
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`VI. There Is a Reasonable Likelihood That Claims 9-11 and 15 of the ’940
`Patent Are Unpatentable
`Pursuant to Rule 42.104(b)(4)-(5), the following analysis and evidence
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`demonstrates where each element of the Challenged Claims is found in the prior art
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`for each of the grounds listed above.
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` Ground 1: Claims 9-11 and 15 are Obvious over Ober in view of
`Dai
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`Reasons to Combine Ober and Dai
`A person of ordinary skill in the art in April 2002 would have found it obvious
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`to combine the system of Ober with the caches, cache tags, snoop circuitry and other
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`components of Dai. Ex. 1002 ¶¶ 83-88. Such a combination involves nothing more
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`than the addition of known elements (cache, cache tags, snoop circuitry) in a manner
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`that will yield predictable results and known benefits. KSR Int'l Co. v. Teleflex Inc.,
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`550 U.S. 398, 417 (2007) (“[I]f a technique has been used to improve one device, and
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`a person of ordinary skill in the art would recognize that it would improve similar
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`devices in the same way, using the technique is obvious unless its actual application
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`is beyond his or her skill.”). First, a person of ordinary skill would have known to
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`draw on teachings from both references because both are directed to solving the same
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`problem. Specifically, the introductory sections of both patents refer to a need for
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`reducing power consumption in battery-powered portable computer devices.
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`Compare Ex. 1007 at 1:22–28, 2:10–20 with Ex. 1003 at 1:28–32. Thus, both
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`references are directed to solving a similar problem in a similar field of art. A person
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`of ordinary skill in the art would have recognized these similarities and the potential
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`for combination. Ex. 1002 ¶ 84, 87.
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`Second, the combination of the invention of Ober with the invention of Dai is
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`straightforward and would have yielded predictable results. Ober teaches that the
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`architecture is “modular” and may be implemented in a System on Chip with different
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`numbers of subsystems. Ex. 1007 at 3:45–51; Ex. 1002 ¶¶ 85-86. Similarly, Dai
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`discloses that the components contained within the claimed processor may be
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`alternatively included in various power domains for different configurations—or
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`optionally excluded from the processor—and are not limited to the partitioning
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`disclosed in any single embodiment. Ex. 1003 at 2:63–4:39. Moreover, even prior to
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`combination, the architectures disclosed by Ober and Dai are similar. Ober teaches a
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`“CPU core 22 . . . coupled to a system bus” which connects the CPU core to, among
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`other things, a power management system. Ex. 1007 at 5:31–53. Likewise, Dai
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`describes a processor (including a CPU core) that is coupled (via a bus and hub 110)
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`to hub 125, which includes Power Manager 127. Ex. 1003 at Fig. 1. Combining the
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`cache, cache tags, snoop circuitry and other components of Dai with the system of
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`Ober would therefore have involved no more than ordinary skill, and the person of
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`ordinary skill could expect the combination to yield the expected results and benefits.
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`Ex. 1002 ¶¶ 85-86.
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`Furthermore, a person of ordinary skill in the art would have been motivated to
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`combine the teachings of Dai with Ober in order to improve the operation and
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`efficiency of Ober. Ex. 1002 ¶ 88. As explained in the accompanying declaration of
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`Richard Belgard, inclusion of cache memory, cache tags, snoop circuitry, and related
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`components leads to increased processor efficiency and improvements in processor
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`performance. Ex. 1002 ¶¶ 36-49. Specifically, adding a n L2 cache (and cache tags
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`and snoop circuitry) to the “non-core power area” of Ober allows the processing
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`system to more rapidly retrieve and process instructions without needing to access
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`deeper levels of memory. Id. The same rationale supports addition of an L1 cache in
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`the “core power area.” A person of ordinary skill in the art as of April 2002 would
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`have been well aware of these benefits. Id. ¶ 49.
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`1.
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`Independent Claim 9
`(a) Preamble – “A processor, comprising:”
`Both Ober and Dai disclose the Preamble of Claim 9. Ober teaches a “modular
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`power management architecture for a microcontroller or System on Chip (SoC) which
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`can be utilized for microcontrollers or SoC's with different numbers of Subsystems
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`and which allows an operating System or application program to independently
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`control the Subsystems within the microcontroller to optimize power management of
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`the Subsystems.” Ex. 1007 at 3:45-51. Figure 1 of Ober (below) shows that the
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`architecture described by Ober includes a Core 22, which “may be any of a variety of
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`CPU [central processing unit] cores.” Id. at 5:29; Ex. 1002 ¶ 89; see id. Section XII.C.
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`Ex. 1007 Fig. 1.
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`(b) First Element, Part 1 – “a non-core power area,
`comprising:”
`Ober teaches a system on a chip that may be divided into the claimed “core
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`power area” and “non-core power area.” See, e.g., Ex. 1007 at Table 8. As described
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`in more detail below, the “CPU core 22” described by Ober may serve as the “core
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`power area” in claim 9 of the ʼ940 Patent. Ex. 1007 at 5:31-36; Fig. 1.
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`The components of Ober’s system on a chip that are external to CPU core 22
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`may serve as the “non-core power area.” Ex. 1002 ¶ 90; see id. Section XII.C.
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`Specifically, Ober states that the “CPU core is coupled to a system bus, for example,
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`a multiplexed address/data FPI bus 24.” Ex. 1007 at 5:31-36. The FPI bus couples
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`the CPU core 22 to other components on Ober’s system on a chip, including, a real-
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`time clock (RTC), clock distribution circuitry, and interrupt controller, among others.
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`Ex. 1007 at Figs. 1-2; 5:31-57. As described in more detail below, each of these
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`components is part of the “non-core power area.” The components of the “non-core
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`power area” are shaded in red below on Ober’s Figure 1:
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`Ex. 1007 Fig. 1 (annotated).
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`Additionally, Ober teaches that the CPU core power 22 may be controlled
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`independently of the power to the components in the non-core power area. Table 8 of
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`Ober describes various p