(12) United States Patent
`Lint et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7.426,648 B2
`Sep. 16, 2008
`
`USOO7426648B2
`
`2004/0107273 A1* 6/2004 Biran et al. ................. 709,223
`(54) GLOBAL AND PSEUDO POWER STATE
`OTHER PUBLICATIONS
`MANAGEMENT FOR MULTIPLE
`U.S. Appl. No. 09/551462, filed Apr. 18, 2000, “Wireless Video
`PROCESSINGELEMENTS
`Distribution.”
`U R RR 21,228, s A. t 03, “A Ms. d, system,
`(75) Inventors: Bernard J. Lint, Mountain View, CA
`al pparatus Ior improving Multi-Uore Processor Performance.
`U.S. Appl. No. 10/741,641, filed Dec. 19, 2003, “Methods and Appa
`(US); Todd A. Dutton, Southborough,
`MA (US); Kushagra Vaid, San Jose, CA ratus to Manage System Power and Performance.”
`(US)
`U.S. Appl. No. 10/750,256, filed Dec. 29, 2003, “Methods and Appa
`ratus to Selectively Power Functional Units.”
`(73) Assignee: Intel Corporation, Santa Clara, CA
`U.S. Appl. No. 10/811,864, filed Mar. 30, 2004, “Device, System and
`(US)
`Method for Reduced Power Consumption.”
`U.S. Appl. No. 10/850,775, filed May 21, 2004, “P-State Feedback to
`Operating System with Hardware Coordination.”
`U.S. Appl. No. 10/859,656, filed Jun. 2, 2004, “Packet Exchange for
`s
`Controlling System Power Modes.
`U.S. Appl. No. 10/859,892, filed Jun. 2, 2004, “Hardware Coordina
`tion of Power Management Activities.”
`U.S. Appl. No. 10/880,976, filed Jun. 29, 2004, “Power Management
`Apparatus, Systems, and Methods.”
`U.S. Appl. No. 10/884.359, filed Jul. 2, 2004, "An Apparatus and
`Method for Heterogeneous Chip Multiprocessors via Resource Allo
`cation and Restriction.”
`* cited by examiner
`Primary Examiner Thomas Lee
`Assistant Examiner Jaweed A Abbaszadeh
`(74) Attorney, Agent, or Firm—David P. McAbee
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 334 days.
`
`(21) Appl. No.: 10/956,203
`
`(22) Filed:
`
`Sep. 30, 2004
`
`(65)
`
`Prior Publication Data
`US 2006/0069936A1
`Mar. 30, 2006
`
`(51) Int. Cl.
`(2006.01)
`G06F I/26
`(2006.01)
`G06F I/32
`(52) U.S. Cl. ....................... 713/320, 713/300; 712/228;
`709/223
`(58) Field of Classification Search ................. 713/300,
`713/320, 712/228; 709/223
`See application file for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`2002/0007463 A1* 1/2002 Fung .......................... T13,320
`2003/0093.655 A1
`5/2003 Gosior et al. ............... T12/228
`
`ABSTRACT
`(57)
`A method and apparatus for global and local power manage
`ment is herein described. Hardware within monitor/receives
`power management requests for any number of processing
`elements and adjusts global performance resources to change
`the global power state of all the processing elements or
`adjusts a local performance resource for a processing element
`to operate that processing element at a pseudo power state
`within the global power state.
`
`25 Claims, 6 Drawing Sheets
`
`Receiving a first power
`management request for a first
`logical processor
`705
`
`Receiving a second power
`management request for a
`second logical processor
`710
`
`
`
`Adjusting at least one
`performance resource based on
`the first and second power
`management request
`
`715
`
`Qualcomm, Ex. 1005, Page 1
`
`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 1 of 6
`
`US 7426,648 B2
`
`First logical
`processor 110
`
`
`
`Second logical
`processor 115
`
`Architecture State
`Registers
`120
`
`Architecture State
`Registers
`125
`
`Execution UnitS
`
`135
`
`
`
`Instruction Re-Order 140
`
`Fetch! Decode
`Execution Resources
`
`145
`
`FIG. 1
`
`Qualcomm, Ex. 1005, Page 2
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`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 2 of 6
`
`US 7426,648 B2
`
`First logical
`processor 210
`
`Second logical
`processor 215
`
`Architecture State
`Registers
`220
`
`Architecture State
`Registers
`225
`
`
`
`Execution
`Units
`
`Instruction
`;
`Re-order
`4O. :
`
`:
`:
`
`Execution
`Units
`
`instruction
`Re-Order
`
`Fetch/Decode
`Fetch/Decode
`:
`245 :
`260
`Execution Resources
`
`FIG. 2
`
`Qualcomm, Ex. 1005, Page 3
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`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 3 of 6
`
`US 7426,648 B2
`
`First logical
`processor 310
`
`Second logical
`processor 315
`
`POWer Module
`
`FIG. 3
`
`
`
`Redister 415
`
`Software 410
`
`Register 420
`
`Hardware 405
`
`Register 425
`
`POWer Module 320
`
`FIG. 4
`
`Qualcomm, Ex. 1005, Page 4
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`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 4 of 6
`
`US 7426,648 B2
`
`Pseudo PO (1) 540
`
`Pseudo PO (2) 545
`
`Pseudo PO(n) 550
`
`Pseudo P1 (1) 560
`
`
`
`Pseudo P2(n) 575
`GE)
`
`
`
`Core Performance 505
`
`FIG. 5
`
`Core
`POWer
`510
`
`
`
`Qualcomm, Ex. 1005, Page 5
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`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 5 of 6
`
`US 7426,648 B2
`
`First logical
`processor 610
`
`Second logical
`processor 615
`
`- a
`
`- - - - - - - - - - - - - - -
`
`- - - - - - - - - - - - - - - - -
`
`- - - - - - - - - - - - - - - s - as as a s - - - - - - - - - - - - -
`
`
`
`
`
`
`
`POWer Module
`
`Controller hub 630
`
`
`
`
`
`Storage
`Medium
`650
`
`
`
`FIG. 6
`
`Qualcomm, Ex. 1005, Page 6
`
`

`

`U.S. Patent
`
`Sep. 16, 2008
`
`Sheet 6 of 6
`
`US 7.426,648 B2
`
`
`
`Receiving a first power
`management request for a first
`logical processor
`05
`
`Receiving a second power
`management request for a
`Second logical processor
`
`Adjusting at least One
`performance resource based on
`the first and second power
`management request
`
`FIG. 7
`
`Qualcomm, Ex. 1005, Page 7
`
`

`

`US 7,426,648 B2
`
`1.
`GLOBAL AND PSEUDO POWER STATE
`MANAGEMENT FOR MULTIPLE
`PROCESSINGELEMENTS
`
`FIELD
`
`This invention relates to the field of computer systems and,
`in particular, to power management for multiple processing
`elements.
`
`BACKGROUND
`
`10
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`15
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`25
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`30
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`35
`
`Typically, power management for a single processor on a
`single die has constituted changing global power States by
`altering global performance resources Supplied to the single
`die, such as Voltage and frequency. Therefore, when a pro
`cessor is performing in a max performance/power state, the
`max Voltage and frequency is Supplied to the processor. To
`change the power state of the processor the frequency, Volt
`age, or both are changed to effectuate the power state change.
`Other methods of power management have included reducing
`power to functional units of a microprocessor depending on
`whether the functional unit will be speculatively used to
`execute instructions in a cache, Such as in co-pending appli
`cation 750,256.
`However, advances in semi-conductor processing and
`logic design have permitted an increase in the amount of logic
`that may be present on integrated circuit devices. As a result,
`microprocessor configurations have evolved from a basic
`single processor on a single die to include multiple processor
`cores or multiple processor threads on a single die.
`Typically, multiple threads share common data caches,
`instruction caches, execution units, branch predictors, control
`logic, bus interfaces, and other processor resources, while
`maintaining a unique architecture state for each processor.
`One example of multi-threading technology is Hyper
`Threading Technology (HT) from Intel(R) Corporation of
`Santa Clara, Calif., that enables execution of threads in par
`allel using a signal physical processor. HT is achieved by
`having multiple architectural States that share one set of
`40
`caches, execution units, branch predictors, control logic, and
`buses.
`In addition, multi-core technology tends to include mul
`tiple core processors on a single die. Each core may have its
`own caches, execution units, branch predictors, control logic,
`45
`and architecture states. Yet, each core may also share some of
`those processing resources, as well as other resources, such as
`a bus interface. Multi-threads and multi-cores tend to overlap
`in that any configuration of multiple processors on a single die
`may share some resources, while having their own separate
`processing resources.
`In fact, it is common for an operating system to logically
`view a multi-core single die processor and a multi-threaded
`single die processor exactly the same: as multiple processors.
`Therefore, a single die processor with either multiple cores or
`multiple threads are typically referred to as a physical pro
`cessor having multiple “logical processors, wherein each
`logical processor may be a thread or a core. Moreover, the
`operating system may issue an independent power manage
`ment request for any single logical processor on the physical
`processor, since the operating system may not differentiate
`between physical and logical processors.
`Therefore, with the advent of logical processors the coarse
`grained control of global resource power management may
`affect both power consumption and processor performance.
`As a simple example, if a physical processor has two logical
`processors running at a max performance power state and the
`
`50
`
`55
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`60
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`65
`
`2
`operating system requests one of the two logical processors to
`enter a lower performance power state, then with the current
`global power management controls, there may be only two
`options. First, either the Voltage or frequency may be reduced.
`However, since global performance resources. Such as Volt
`age and frequency, are Supplied to the whole physical proces
`sor, both logical processors would be affected by the reduc
`tion instead of just the single logical processor. Second, the
`request for one of the processors to enter into a lower perfor
`mance power state may be ignored. Yet, this would result in
`both logical processors operating at max performance, which
`may waste power. Furthermore, hardware speculation of
`future units to be utilized to reduce power to functional units,
`as mentioned above, may not allow the operating system to
`modify performance of individual logical processors.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by way of example and
`not intended to be limited by the figures of the accompanying
`drawings.
`FIG. 1 illustrates an embodiment of a multi-threaded pro
`CSSO.
`FIG. 2 illustrates an embodiment of a multi-core processor.
`FIG. 3 illustrates an embodiment of a physical processor
`with two logical processors and associated firmware.
`FIG. 4 illustrates an embodiment of the firmware shown in
`FIG. 3.
`FIG. 5 illustrates an embodiment of global and pseudo
`power States on a core performance V. core power graph.
`FIG. 6 illustrates an embodiment of a system with a physi
`cal processor having two logical processors and firmware, a
`controller hub, a memory, and a storage medium.
`FIG. 7 illustrates a flow diagram of a method for receiving
`a first and a second power management request and adjusting
`at least one performance resource.
`
`DETAILED DESCRIPTION
`
`In the following description, numerous specific details are
`set forth Such as examples of specific numbers of physical and
`logical processors, specific processing resources shared or
`separated in a physical processor, and specific power states in
`order to provide a thorough understanding of the present
`invention. It will be apparent, however, to one skilled in the art
`that these specific details need not be employed to practice the
`present invention. In other instances, well known components
`or methods, Such as specific hardware and Software imple
`mentation have not been described in detail in order to avoid
`unnecessarily obscuring the present invention.
`The method and apparatus described herein are for effi
`ciently managing both global and local performance
`resources for physical and logical processors. It is readily
`apparent to one skilled in the art, that the method and appa
`ratus disclosed for adjusting performance resources may be
`implemented in any level computer system (personal digital
`assistants, mobile platforms, desktop platforms, and server
`platforms), as well as any number of processors. For example,
`a multiprocessor system with four or more physical proces
`sors may use the method and apparatus herein described to
`manage the global performance resources for each of the four
`physical processors and to manage the local performance
`resources for any logical processor present on the four physi
`cal processors. Additionally, a multiple server system may
`utilized the method herein described for adjusting local per
`formance resources that affect an individual server in the
`
`Qualcomm, Ex. 1005, Page 8
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`US 7,426,648 B2
`
`10
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`15
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`25
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`30
`
`3
`multiple server system and for adjusting global performances
`that affect all of the servers in the system.
`FIG. 1 illustrates an embodiment of a physical processor
`105 having two logical processors: first logical processor 110
`and second logical processor 115. Physical processor 105
`may be any combination of transistors, circuits, and logic for
`processing data and/or instructions. Processor 105 may
`include execution resources 130, caches 150, and bus inter
`face 155. Processor 105 may also include any combination of
`the following, which are not specifically depicted: a data path,
`and instruction path, a memory management unit, branch
`predictors, control logic, interrupt controllers, advanced pro
`grammable interrupt controllers (APICs), or any other cir
`cuits to process data.
`Execution resources 130 may include execution units 135,
`instruction re-order logic 140, fetch and decode logic 145,
`and any other circuits to operate on data or execute instruc
`tions. Execution units 135 may include any number of arith
`metic logic units (ALUs), floating-point units (FPUs), regis
`ter files, operand registers, or other execution logic.
`Execution units 135 may also be configurable to operate on
`multiple data operands in serial or parallel. Furthermore,
`execution units 135 may be able to execute a single instruc
`tion or multiple instructions on single or multiple data oper
`ands in serial or parallel. Instruction re-order logic 140 may
`include any logic, registers, or circuits to receive and/or re
`order instructions to be executed by execution units 135.
`Fetch/decode logic 145 may include circuits to fetch and
`decode elements, such as instructions and data operands for
`execution by execution units 135. Fetch/decode logic 145
`may be able to fetch and decode instructions, of fixed or
`variable length, and/or x86 instructions.
`Caches 150 may include low level data and instruction
`caches, secondary or higher level data or instruction caches,
`as well as other temporary storage for a microprocessor. Bus
`35
`interface 155, and 285 in FIG. 2, may include any number of
`controllers or control logic for interfacing with a front-side
`bus, a back-side bus, a direct memory access bus, or any other
`external interconnect
`As depicted in FIG. 1, architecture state registers 120 and
`125, which are associated with first logical processor 110 and
`second logical processor 115 respectively, share access to
`execution units 135, instruction re-order logic 140, fetch/
`decode logic 145. In another embodiment architecture state
`registers 120 and 125 share access to execution units 135 and
`fetch/decode logic 145; however, instruction re-order logic
`140 is partitioned among first logical processor 110 and sec
`ond logical processor 115. Architecture state registers 120
`and 125 may maintain a complete set of the architecture state
`for first logical processor 110 and second logical processor
`115, respectively. The architecture state may consist of gen
`eral-purpose registers, control registers, APIC registers,
`machine state registers (MSRs), the state of the instruction
`pointer, and any other registers, logic, or circuits to maintain
`the architecture State of a processor or to resume execution of
`an interrupted thread.
`Turning to FIG. 2, another embodiment of a physical pro
`cessor with two logical processors is shown. Physical proces
`Sor 205 comprises two logical processors: first logical pro
`cessor 210 and second logical processor 215. Architecture
`state registers 220 are associated with first logical processor
`210, while architecture state registers 225 are associated with
`second logical processor 215.
`In contrast to FIG. 1, first and second logical processors
`210 and 215 do not share access to execution resources 230
`and caches 270. Execution resources 230 depict execution
`units 235, instruction re-order logic 240, and fetch/decode
`
`55
`
`4
`logic 245 associated with first logical processor 210, while
`execution units 250, instruction re-order logic 255, and fetch
`decode logic 260 are depicted as associated with second
`logical processor 215. Execution units 235 and 250, instruc
`tion re-order logic 240 and 255, and fetch/decode logic 245
`and 260 may include any number of transistors, circuits,
`logic, or registers described above in reference to FIG. 1.
`These blocks may be physically separate in processor 205,
`physically contiguous and associated with first and second
`logical processors 210 and 215, or a single functional block,
`as shown in FIG. 1, with a portion dedicated to first logical
`processor 210 and a portion dedicated to second logical pro
`cessor 215.
`Both FIGS. 1 and 2 depict at least a first set of architecture
`state registers associated with a first logical processor and a
`second set of architecture state registers associated with a
`second logical processor. The ability for each logical proces
`Sor to maintain a separate architecture state potentially allows
`an operating system to view one physical processor as a
`plurality of processors. As a consequence, an operating sys
`tem may not differentiate between a thread and a core.
`Therefore, a logical processor, as used herein, includes any
`logic located on an integrated circuit capable to store an
`architecture State. As an example, a single physical micropro
`cessor may have one set of architecture state registers capable
`of storing an architecture state. Consequently, the single
`physical microprocessor may be referred to as having one
`logical processor. A thread, as used herein, refers to any logic
`capable to store an architecture state that shares access to at
`least one execution unit and one cache. A core refers to any
`logic capable to store an architectures state that has at least a
`portion of the execution resources dedicated to the core. It is
`readily apparent from FIGS. 1 and 2 that any number of
`separate architecture state registers and, therefore, logical
`processors may be present on a physical processor. Further
`more, there may any number of physical processors, as well
`as any number of processing elements. A processing element
`may be a logical processor, a physical processor, a single
`computing system, a server, a network of computers, or any
`level element for operating on data.
`Referring to FIG. 3, a physical processor 305 is shown
`having first logical processor 310, second logical processor
`315, and power module 320. Any number of logical proces
`sors may be present on physical processor 305; however, as to
`not obscure the invention only a single physical processor
`having two logical processors is illustrated in FIG. 3. Power
`Module 320, which may be only hardware as well as hard
`ware associated with Software, is depicted as associated with
`physical processor 305, first logical processor 310, and sec
`ond logical processor 315. Power Module 320 may be inte
`grated in physical processor 305, present on physical proces
`sor 305, or separate from physical processor 305. Power
`Module 320 will be discussed in more detail in reference to
`FIG. 4.
`Since an operating system may view each logical proces
`Sor, Such as logical processors 310 and 315, as separate pro
`cessors, the operating system may send individual power
`management requests (also know as commands) for each
`logical processor to change power states or performance lev
`els. A power management request/command may request any
`level of processing element, a single physical processor, mul
`tiple physical processors, multiple logical processors, or a
`single logical processor to operate at a certain power or per
`formance state. However, current methods of adjusting global
`resources based on an individual power management request/
`command may result in wasted power consumption or limit
`ing performance. Therefore, power module 320 may be oper
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`Qualcomm, Ex. 1005, Page 9
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`US 7,426,648 B2
`
`5
`able to receive the independent power management requests
`and based on those power management requests, the current
`power state of each processing element, or the combination of
`the power management requests and the current power state,
`power module 320 may also be operable to adjust perfor
`mance resources. In one embodiment, performance resources
`include global resources, which are resources that affect a
`plurality of processing elements, such of all logical processor
`located on a single physical processor, and/or local resources,
`which are resources that affect the performance/power of a
`single processing element. Such as a single logical processor.
`More detail of the adjustment of global and local performance
`resources will be discussed in reference to FIG. 5.
`Power module 320 may be any hardware, any software
`associated with the hardware, any microcode, or firmware for
`receiving power management requests and adjusting perfor
`mance resources based on those power management requests.
`Power module 320 may also receive power management
`requests an elect not to adjust performance resources either in
`contrast or conformance with the power management request.
`For example, if the power management request requests a
`logical processor to operate in its current power state, there
`would be no need for a change. As another example, power
`module 320 may be designed to violate the performance
`power management requests and not alter performance
`resources based on predetermined rules and dependencies.
`An embodiment of power module 320 is depicted in FIG. 4.
`In one embodiment, power module 320 comprises hardware
`405 with software 410 and registers 415,420, and 425. Hard
`ware 405 may be any hardware device to store and/or execute
`Software routines, such as a read access memory (RAM), a
`read only memory (ROM), a programmable read only
`memory (PROM), an erasable programmable read only
`memory (EPROM), an electrically erasable programmable
`read only memory (EEPROM), as programmable logic array
`(PLA), logic present in microprocessor 305, or any other
`circuit/memory for storing software 410. Hardware 405 may
`be inaccessible to users (locked), may be modifiable by spe
`cial privilege users, or may be fully modifiable by any user.
`Software 410 may be embedded software inhardware 405.
`Software 410 may also be microcode programmed in hard
`ware 405. Software 410 may include routines or microin
`structions to receive power management requests, to store the
`power management requests or values based on the power
`management requests in registers 415, 420, and 425, and/or to
`adjust global and/or local performance resources. Software
`410 may adjust global and/or local performance resources by
`issuing a request for the adjustment, by actually adjusting the
`performance resources itself, or by communicating with a
`device to adjust the performance resource. Software 410 may
`ascertain what global or pseudo power state logical processor
`310 and logical processor 315 is in by the latest request stored
`in registers 415-425 or by directly communicating with first
`and second logical processors 310 and 315.
`Registers 415, 420, and 425 may store the power manage
`ment requests, any value based on the power management
`requests, any representation of the power management
`requests, or the current power state of logical processors 310
`and 315. There may be any number of registers 415,420, and
`425. As a very basic example, there may be one register for
`every logical processor to store the current power State, the
`latest power management request, or a value based on the
`latest power management request, which may represent the
`current power state.
`As another simple example, if first logical processor 310
`and second logical processor 315 are in a max performance
`power state, which will be referred to as P0 for this example,
`
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`and first logical processor 310 receives an individual power
`management request to change to a lower performance power
`state, which for this example will be referred to as P1, then
`Power Module 320 may check any one, any combination, or
`all of registers 415-425 and discover that the last power man
`agement request for both logical processors 310 and 315 was
`for power state P0. Power Module 320 may then adjust local
`performance resources of first logical processor 310 to oper
`ate first logical processor 310 in a pseudo power state within
`global power state P0. Therefore, first logical processor 310
`may step down in power consumption; however, second logi
`cal processor 315 has the global performance resources avail
`able to operate in the max performance power state P0. In
`contrast, if Power Module 320 were not present or not uti
`lized, global performance resources, such as Voltage or fre
`quency, may have been adjusted forcing both first and second
`logical processors to operate at power state P1. As a conse
`quence, second logical processor 315, which was not
`requested to operate in a lower power state, may be forced to
`operate in that lower power state P1, limiting performance.
`Turning to FIG. 5, an embodiment of global and pseudo
`power states on a core performance V. core power graph is
`shown. Once again, the two logical processors from FIG. 3
`will be used to describe the graph in FIG. 5. However, any
`number of logical processors may be actually present on any
`number of physical processors. FIG. 5 illustrates four global
`power states: global power state 515 (P0), global power state
`520 (P1), global power state 525 (P2), and global power state
`530 (P3). Although, there are only four global power state
`illustrate in FIG. 5, there may be any number of global power
`states. Global power states 515-530 may be any level of
`power on core power axis 510 and any level of performance
`on core performance axis 505. A change between global
`power States may include adjusting global performance
`resources, such as Voltage Supplied to physical processor 305.
`frequency that physical processor 305 operates at, a combi
`nation of Voltage and frequency, or any global resource that
`would affect the performance of all logical processors located
`on one physical processor. As an example, in global power
`state 515 an operating voltage may be 1.4V and a core fre
`quency may be 3.4 GHz, which may be multiplied from an
`externally supplied lower frequency. To operate both logical
`processors at global power state 520, the operating Voltage
`may be adjusted to 1.3V and the supplied frequency may be
`adjusted so that the multiplied core frequency is 2.4 GHz.
`Within global power state 515 there are n pseudo power
`states shown including pseudo power State 540, pseudopower
`state 545, and pseudo power state 550. Within global power
`state 520 there are n pseudo power states shown including
`pseudo power state 560 and pseudo power state 565. Within
`global power state 525 there are n pseudo power states shown.
`Global power state 530 may also have n pseudo power states,
`which are not depicted in FIG. 5.
`A pseudo power State may be a power state within a global
`power state, in which the global performances resources of
`the global power state are available to a single processing
`element, such as a logical processor; however, the single
`processing element is consuming less power operating in the
`pseudo power state than if it were operating in the global
`power state. To operate a logical processor in a pseudo power
`state any number of local performance resources may be
`adjusted.
`For example for a logical processor, the width of instruc
`tions fetched and decoded, the number of instructions per
`cycle fetched and decoded, the number of data operands
`operated on, the width of the data operands operated on, the
`duty cycle, the size of the renaming pool, or any other per
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`Qualcomm, Ex. 1005, Page 10
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`US 7,426,648 B2
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`formance resource that may affect only a single logical pro
`cessor on a physical processor may be adjusted. Additionally,
`if voltage and frequency are independently Supplied to logical
`processors on a single physical processor, then Voltage and
`frequency may be local performance resources that may be
`adjusted. As an example for a plurality of servers as process
`ing elements, a local performance resource may be a resource
`that affects only one of the plurality of servers, such as the
`Voltage Supplied by a single power Supply to one of the
`plurality of servers.
`10
`Referring to FIG. 3-5 a few examples of how Power Mod
`ule 320 may monitor independent power management
`requests and adjust performance resources based on those
`independent power management requests will be discussed.
`As a first example, assume that based on a previous power
`management command, second logical processor 315 is oper
`ating at global power state 515. Power Module 320 may
`receive an independent power management command for first
`logical processor 310 to operate at global power state 520.
`Power Module 320 may check a previous power management
`command in a register, such as registers 415-425, to ascertain
`the current operating power state of second logical processor
`315. Power Module 320 may also directly communicate with
`second logical processor 315 to ascertain its current power
`State.
`25
`Since the previous power management command
`requested second logical processor 315 to operate in global
`power state 515, which is a higher performance power state
`than global power state 520, at least one local performance
`resource of first logical processor 310 may be changed to
`operate first logical processor at pseudo power state 540.
`Consequently, second logical processor 315 may still be oper
`ating at global power state 515, while first logical processor
`310 may be operating at pseudo power state 540. Any one or
`plurality of local performance resources may be changed,
`wherein a local performance resource affects the power con
`sumption of a single logical processor. Power Module 320
`may either randomly select or intelligently select a perfor
`mance resource to change. An intelligent selection of a per
`formance resource, may include selecting a performance
`resource that optimally obtains the desired power or perfor
`mance level and minimizes the effects on the un-requested
`changes in power of performance.
`It may be advantageous to design the pseudo power states,
`Such as pseudo power State 540 to decrease power consump
`tion and change performance to the same performance level
`of the requested power state. As shown in FIG. 5, all the
`pseudo power states within the global power states are at the
`same performance on the core performance axis 505 as the
`next lower performance power state. This may allow a logical
`processor to perform at the next lower performance global
`power State, while the global performance resources are still
`at the higher performance power State. Pseudo power state,
`Such as pseudo power state 540, may be designed so that a
`change in any single or multiple local performance resources
`55
`may be necessary to operate at that pseudo power state. How
`ever, pseudo power states are not so limited. As stated above
`a power management request may request a change in per
`formance level or power state; therefore, pseudo power states,
`Such as pseudo power state 540 may be designed to operate at
`any performance level on performance axis 505.
`Continuing the example from above, Power Module 320
`may then receive a power management command requesting
`first logical processor to operate at global power state 525.
`Power Module 320 may then check and determine that second
`logical processor 315 is still operating at global power state
`515. Since second logical processor 315 is still operating at a
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`higher performance power state, Power Module 320 may
`change or request a change to at least one local performance
`resource of first logical processor 310 to operate at second
`pseudo power state 545 within global power state 515. After
`the change, first logical processor 310 may be operating in
`second pseudo power state 545 and second logical processor
`315 may still be operating in global power state 515. There
`may be any number of pseudo power states within each global
`power state. Additionally, FIG. 5 illustrates second pseudo
`power state 545 at the same