UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`QUALCOMM INC. AND QUALCOMM TECHNOLOGIES, INC.,
`Petitioners
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`v.
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`APPLE INC.,
`Patent Owner
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`Case No. IPR2019-00322
`Patent No. 8,443,216
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`PATENT OWNER’S PRELIMINARY RESPONSE
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`TABLE OF CONTENTS
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`I.
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`INTRODUCTION ........................................................................................... 1
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`II.
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`OVERVIEW OF THE ’216 PATENT ............................................................ 2
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`III. OVERVIEW OF THE PRIOR ART ............................................................... 5
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`A. Mandelblat ............................................................................................. 5
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`B.
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`C.
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`Kurts ...................................................................................................... 9
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`Kang .................................................................................................... 13
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`IV. GROUND 1 IS DEFICIENT BECAUSE THE PETITION FAILS TO
`SHOW THAT MANDELBLAT DISCLOSES A POWER MANAGEMENT
`UNIT THAT ASSOCIATES A PERFORMANCE STATE OF A FIRST
`PERFORMANCE DOMAIN WITH A PERFORMANCE STATE OF A
`SECOND PERFORMANCE DOMAIN ....................................................... 15
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`A.
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`B.
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`The Petition’s Analysis Begins With Copied-And-Pasted Discussion
`Of A Different Limitation From A Different Petition ........................ 17
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`The Petition’s Focus On Common Control Of The Performance
`Domains Is Insufficient ....................................................................... 20
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`C. Mandelblat Does Not Associate The Performance States Of First And
`Second Performance Domains In The Power Management Unit As
`Claimed In The ’216 Patent ................................................................ 24
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`V. GROUND 2 IS DEFICIENT (OBVIOUSNESS BASED ON
`MANDELBLAT AND KURTS) .................................................................. 27
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`A.
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`B.
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`The Petition’s Inconsistent Mappings And Shifting Theories Fail To
`Demonstrate A Prima Facie Case Of Obviousness ............................ 27
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`The Petition Fails To Show That Any Of Its Four Contradictory
`Obviousness Theories Teach All Required Limitations Of The
`Challenged Claims .............................................................................. 38
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`1.
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`Petitioner’s First Theory Is Deficient (Mandelblat As Modified
`By Kurts) ................................................................................... 39
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`i
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`2.
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`3.
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`4.
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`Petitioner’s Second Theory Is Deficient (Mandelblat Alone) .. 39
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`Petitioner’s Third Theory Is Deficient (Kurts As Modified By
`Mandelblat (Without Dynamic Memory)) ................................ 40
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`Petitioner’s Fourth Theory Is Deficient (Kurts As Modified By
`Mandelblat (With Dynamic Memory)) ..................................... 44
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`VI. GROUND 3 IS DEFICIENT (OBVIOUSNESS BASED ON KURTS AND
`KANG)........................................................................................................... 51
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`A.
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`B.
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`The Petition Fails To Show That The Kurts-Kang Combination
`Would Provide A Power Management Unit Configured To Transition
`A Second Performance Domain To A First Performance State
`Responsive To A First Performance Domain Including A Processor
`Transitioning To A Second Performance State ................................... 51
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`The Petition Fails To Show That The Kurts-Kang Combination
`Would Provide A Power Management Unit That Associates A
`Performance State Of A First Performance Domain With A
`Performance State Of A Second Performance Domain ...................... 57
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`VII. CONCLUSION .............................................................................................. 60
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`ii
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`LIST OF EXHIBITS
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`Apple-2001
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`[RESERVED]
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`Apple-2002
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`Petition (IPR2019-00321)
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`iii
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`I.
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`INTRODUCTION
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`The Board should deny institution because (1) Ground 1 fails to show that
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`Mandelblat discloses an association of performance states between first and second
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`performance domains in a power management unit as recited in claims 1 and 8; (2)
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`Ground 2 presents inconsistent mappings and contradictory obviousness theories
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`that mask substantive deficiencies in the Mandelblat-Kurts combination; (3) the
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`petition fails to show in Ground 2 that Mandelblat and Kurts teach the requisite
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`transition in performance states of a second performance domain as recited in the
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`claims; (4) the petition fails to show in Ground 3 that Kurts and Kang teach the
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`requisite transition in performance states of a second performance domain; and (5)
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`the petition fails to show in Ground 3 that Kurts and Kang teach an association of
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`performance states between first and second performance domains in a power
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`management unit. Thus, each ground presented in the petition suffers fatal
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`deficiencies.
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`These multiple procedural and substantive deficiencies prove that Petitioner
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`has not demonstrated a reasonable likelihood of prevailing with respect to its
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`challenges against at least one claim of the ’216 patent. Institution should be
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`denied.
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`1
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`II. OVERVIEW OF THE ’216 PATENT
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`The ’216 patent describes “a power management unit (PMU) [that]
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`automatically transition[s] (in hardware) the performance states of one or more
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`performance domains in a system.” Qualcomm-1001, Abstract. For example, as
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`shown in Figure 1 (a highlighted version of which is reproduced below), an
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`integrated circuit 10 having a collection of components—such as processors, an
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`audio unit, a graphics unit, a memory controller, and network and peripheral
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`interfaces—are grouped into a set of performance domains 14A-14F (highlighted
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`in green).
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`Qualcomm-1001, FIG. 1 (annotated).
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`2
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`The ’216 patent explains that “[a] performance domain may be one or more
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`components that may be controlled … as a unit for performance configuration
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`purposes.” Id., 4:19-21. Each of the performance domains 14A-14F is capable of
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`assuming different performance states, where each performance state comprises a
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`different combination of performance characteristics such as a particular supply
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`voltage and a particular clock frequency for components within the domain. Id.,
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`4:36-67.
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`A power management unit (PMU) 28 (highlighted in purple above) on the
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`integrated circuit 10 is configured to “control transitions between performance
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`states for the various performance domains 14A-14F. Id., 4:1-3. For example, the
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`PMU 28 may detect when a processor in one performance domain is waking from
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`a sleep state, and in response may transition one or more other performance
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`domains that are linked to the first processor or performance domain to
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`corresponding performance states that can adequately support the activity of the
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`processor in its wake state. Id., 8:55-60 (“[O]ne or more performance domains
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`may be more closely linked with a particular processor in multiprocessor
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`configurations. In such cases, the closely linked performance domains may
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`transition to different performance states in response to the corresponding
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`processor entering the sleep state[] …”), 4:1-11. By way of example, the
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`following figure illustrates one scenario of the PMU 28 waking performance
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`3
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`domains in response to a processor transitioning from a sleep state to a wakeup
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`state:
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`Qualcomm-1001, FIG. 1 (annotated and repeated).
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`As shown in the above sequence, various performance domains under the
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`control of power management unit 28 are initially (at time t0) in a wake state
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`(green) corresponding to a wake state of processor 16B (green). At time t1, the
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`processor 16B enters a sleep state (red). The power management unit 28 detects
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`when the processor 16B has entered the sleep state, and in response, it transitions a
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`subset of the performance domains 14C-14D that are “closely linked” or associated
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`with the processor 16B to corresponding sleep states (red). Thus, the system may
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`conserve power by establishing sleep states for performance domains whose
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`activities are not required to support a processor when the processor is asleep and
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`not actively executing instructions. See, e.g., id., 4:1-19, 5:49-63, 8:18-36, 8:55-
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`65.
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`4
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`III. OVERVIEW OF THE PRIOR ART
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`A. Mandelblat
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`Mandelblat (Qualcomm-1003) describes techniques for dynamic memory
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`size adjustment to conserve power at times when the full range of the memory is
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`not needed. Qualcomm-1003, Abstract, [0004]-[0005], [0017]. Mandelblat
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`identified a design trend at the time of its filing toward the inclusion of
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`increasingly larger cache memories associated with microprocessors, but explained
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`that the larger cache sizes also led to increased power consumption. Id., [0005]
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`(“[T]he leakage power that is dissipated by the memory is quite significant relative
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`to the total power of the central processing unit (CPU).”). Moreover, “[t]he
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`amount of memory that may actually be required by a computer system and/or
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`associated software often varies with respect to time” and, in many cases, “only a
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`small portion of the memory may be needed at any given time.” Id., [0017].
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`To mitigate the problem of leakage power consumed by unused memory,
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`Mandelblat proposed to dynamically adjust the size of memories (e.g., cache) used
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`by a processor according to the system’s actual memory requirements in real time.
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`Id., [0017]. For example, Figure 1 depicts one embodiment of a dynamically
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`sizeable memory:
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`5
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Id., FIG. 1.
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`The memory shown in Figure 1 is comprised of several portions (referred to
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`as “ways” 102a-n), and each portion of the memory couples to a “sleep device”
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`104. Id., [0018]. The sleep devices 104a-n operate as switches that selectively
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`enable or disable each portion of memory by either coupling or removing a
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`corresponding portion of the memory from a power source. Id., [0018]; generally
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`[0018]-[0029], FIGS. 1-8. By selectively disabling portions of the memory, the
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`sleep devices 104a-n block current from flowing through the disabled portions
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`thereby reducing leakage power consumption. Id.
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`Mandelblat further describes power management logic for controlling
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`dynamic memory size of cache memory associated with a processor. For example,
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`6
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Figure 9 depicts one or more processors 901 having power management logic
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`(PML) 906 (including memory PML 907), a pair of logical cores 902 and 904, and
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`dynamically sizable memory 905 (e.g., L2 cache memory):
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`Id., FIG. 9; see also [0031]-[0038].
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`In the embodiment depicted in Figure 9, PML 906 controls the power states
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`of cores 902 and 904, each of which is independently configurable. For instance,
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`each core can be placed in a wakeup state (C0) that consumes more power, or in
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`one of several sleep states (C1, C2, C3, or C4) that consume various lesser degrees
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`7
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`of power. Id., [0037]. The only C-state that Mandelblat identifies for cores 902
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`and 904 in the active or wakeup state is “C0.”
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`Similarly, memory PML 907 controls dynamic size adjustments of memory
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`905. Id., [0037]-[0039]; generally id., [0037]-[0046], [0052], FIG. 12. In an
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`embodiment, memory PML 907 implements a finite state machine as depicted in
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`Figure 12 (reproduced below). To effect memory size transitions, memory PML
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`907 provides control signals to microcode 926, which in turn controls sleep devices
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`that shrink or contract the size of memory 905, e.g., by enabling or disabling one or
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`more portions (“ways”) of the memory 905. Id.
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`8
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Id., FIG. 12; see also [0036].
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`As explained in further detail below (Section IV.C), Mandelblat does not
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`associate C-states of a particular processor core with a specific size of memory
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`905. Instead, Mandelblat’s power management logic is configured to monitor
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`system activity and, based on certain variables representative of different aspects
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`of the system’s activity, to generate control signals that cause microcode 926 to
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`enable or disable one or more portions of the memory 905. See id., [0039]
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`(“Transitions between these [memory size] states may be managed according to
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`certain variables …”), [0052] (“Expanding the memory 905 may be based on one
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`or more indicators that an activity factor has increased.”); generally id., [0039]-
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`[0046].
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`B. Kurts
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`Kurts (Qualcomm-1004) describes techniques for establishing power
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`management states in a processor of a computing system. Qualcomm-1004,
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`Abstract, 1:15-33, 2:39-3:15, FIGS. 1, 3. For example, with reference to Figure 3,
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`Kurts describes a system 200 that operates to transition a processor 205 between an
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`active state C0, an auto-halt state C1, a stop-clock state C2, a deep sleep state C3,
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`and a deeper sleep state C4. Id. The petition characterizes the C0 state as a
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`“wake” state and the C1-C4 states as “sleep” states. Pet., 49; see also Qualcomm-
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`1005 (Kurts), 4:48-5:26 (Kurts describing C0 as a “normal operational state” and
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`Proceeding No. IPR2019-00322
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`C1-C4 as “power management states.”). Each C-state defines a respective set of
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`power management settings for the processor 205, including a supply voltage for
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`processor 205 in the C-state and a clock frequency for the processor 205. Id., 3:34-
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`62.
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`When the operating system or other software determines that the processor
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`205 should be placed in a different C-state, the I/O control hub 225 and its power
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`management state control logic 242 assert control signals (e.g., STPCLK#,
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`10
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`CPUSLP#, DPSLP#, DPRSTP#) for receipt by the processor 205 that specify the
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`target C-state for the processor 205. Id., 4:4:48-63. Power management logic 234
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`in processor 205 then acts to implement the C-state specified by the control
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`signals, including accessing values stored in VID table 277 that define
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`voltage/frequency settings for the C-state and communicating those settings to
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`clock generator 211 and voltage regulator 212. Id., 4:3-63. Figure 1 is a state
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`diagram illustrating possible C-state transitions for the processor 205:
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`11
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Qualcomm-1004 (Kurts), FIG. 1; see also id., 5:43-7:20 (describing various C-
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`state transitions as represented in Figure 1).
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`Kurts describes that the processor may include “one or more processing
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`cores and at least one execution unit 210 to process instructions.” Id., 3:34-38.
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`Further, within certain C-states, “portions of the processor 205 circuitry may be
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`powered down and local clocks may be gated.” Id., 5:5:57-59, 6:3-5. Implicit in
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`this disclosure is that some portions of the processor 205 may not be powered
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`down within a given C-state.
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`Although different power management settings may be applied to portions
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`of the processor 205 to establish a given C-state, Kurts is concerned with
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`establishing C-states for the processor 205 (as a whole), rather than establishing C-
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`states for individual portions (e.g., cores) of the processor 205. See id., 5:43-46
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`(describing C-states for the processor 205 as a whole: “FIG. 1 is a state diagram
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`illustrating the transitions between various C-states in which the processor 205…
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`may operate”), 6:9-10 (“processor 205 may transition into the C3 state 307”),
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`6:58-59 (“processor 205 may be capable of entering the C4 state”) (emphasis
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`added).
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`Moreover, in each of the reduced power states (e.g., sleep states C1-C4), the
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`processor 205 remains connected to power and is supplied with a reduced voltage
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`signal from voltage regulator 212. Id., 7:47-54 (“[F]or the Deeper Sleep or C4
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`12
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`state, there may be a C4 voltage and a corresponding C4 VID.”), 6:40-44 (“voltage
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`associated with the C4 state”), 1:29-33 (“C4 is defined as the Deeper Sleep state in
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`which all processor clocks are stopped and the processor voltage is reduced to a
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`lower data retention point.”).
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`C. Kang
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`Kang (Qualcomm-1006) describes techniques for conserving power in a
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`wireless communication terminal. Qualcomm-1006, Abstract, 1:65-2:34. Kang
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`explains that wireless terminals “in a cellular communication system [are] only
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`sporadically active and remain[] in an ‘idle’ mode for significant periods of time
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`when no call is in progress.” Id., 1:16-19. “To ensure that the terminal can still
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`receive messages sent to it by the system, the terminal periodically monitors a
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`paging channel …” Id., 1:19-20. The paging channel is divided into time slots so
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`that the terminal need only listen for paging signals during its assigned time slot.
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`Id., 2:5-38. To conserve power, the terminal enters a “sleep” state during the
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`intervening periods between its assigned time slots, and then “wakes” from the
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`sleep state just before its assigned time slot to listen for a paging signal. Id., 8:26-
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`46, FIG. 4.
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`Kang’s wireless terminal includes a “[m]odem processor 120 [having]
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`various processing units that support monitoring and/or communication with one
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`or more systems.” Id., 3:38-40. Additionally, the modem processor 120 is
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`13
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`“portioned into multiple power domains,” where “[e]ach power domain includes
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`processing units that are coupled to a power supply via a power connection.” Id.,
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`4:37-39.
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`
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`Qualcomm-1006 (Kang), FIG. 2A (annotated).
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`To conserve power when the wireless terminal goes to sleep, a power control
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`unit 140 on the modem processor 120 powers down each of the collapsible power
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`domains 210b-e of the processor 120. Id., 4:42-49, 5:22-23; generally 6:9-7:28,
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`8:26-47, FIG. 4. When a power domain 210b-e is powered down, Kang’s device
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`removes power from the domain, e.g., by toggling a headswitch that disconnects
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`the power domain from a power supply bus 214. Id., 5:42-6:8, FIG. 3. Kang’s
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`14
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`approach thus stands in contrast to Kurts’s power management C-states, which
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`only reduced the voltage applied to a processor in a sleep state, rather than cutting
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`power to independently configurable power domains. Supra, Section III.B.
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`IV. GROUND 1 IS DEFICIENT BECAUSE THE PETITION FAILS TO
`SHOW THAT MANDELBLAT DISCLOSES A POWER
`MANAGEMENT UNIT THAT ASSOCIATES A PERFORMANCE
`STATE OF A FIRST PERFORMANCE DOMAIN WITH A
`PERFORMANCE STATE OF A SECOND PERFORMANCE
`DOMAIN
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`The first ground of the petition is deficient because it has not shown that
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`Mandelblat discloses a power management unit in which a first performance state
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`of a second performance domain is associated with a second performance state of a
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`first performance domain.1 This feature is common to both of the independent
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`claims of the ’216 patent that the petition alleges to be unpatentable:
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`1 By addressing certain arguments in this preliminary response, Apple does not
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`concede that other arguments and positions advanced by Petitioner are correct.
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`Moreover, by referring to Petitioner’s language and characterizations in this
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`preliminary response without specifically challenging them at this time, Apple
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`does not indicate agreement with Petitioner. For example, Apple does not concede
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`that the prior art references asserted in the petition teach a “power management
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`unit” within the context of the ’216 patent, that the references necessarily teach a
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`plurality of performance domains, that the mapped power management units are
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`15
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Claim 1: “a power management unit configured to
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`establish a performance state in each of the plurality of
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`performance domains, and wherein
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`the power
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`management unit is configured to transition a second
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`performance domain of the plurality of performance
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`domains to a first performance state programmed into the
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`power management unit responsive
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`to
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`the
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`first
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`performance
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`domain
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`including
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`the
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`processor
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`transitioning to a second performance state, wherein the
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`first performance state is associated with the second
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`performance state in the power management unit.”
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`Claim 8: “transitioning a second performance
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`domain of the plurality of performance domains to a first
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`performance state programmed into a power management
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`unit of the SOC, wherein the transitioning is responsive to
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`the first performance domain including the processor
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`transitioning to a second performance state, wherein the
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`first performance state is associated with the second
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`performance state in the power management unit.”
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`configured to establish selected performance states or to transition performance
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`states, or that a single performance characteristic is sufficient to define a
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`performance state within the context of the ’216 patent.
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`Qualcomm-1001 (’216 Patent), 13:1-11 (claim 1), 13:48-55 (claim 8) (emphasis
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`added).
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`A. The Petition’s Analysis Begins With Copied-And-Pasted
`Discussion Of A Different Limitation From A Different Petition
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`As an initial matter, and to avoid confusion that could stem from the
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`petition’s discussion of the performance state association feature in Ground 1, the
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`Board should recognize that the overwhelming majority of the petition’s analysis
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`does not actually pertain to this feature from the ’216 patent, but is instead copied-
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`and-pasted from a concurrently filed petition (IPR2019-00321) challenging a
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`different feature recited in claim 8 of related U.S. Patent 8,271,812. Compare Pet.,
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`33-37 (petition’s analysis of the third element (part 3) of claim 1 of the ’216
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`patent) with Apple-2002 (IPR2019-00321 Petition) 38-42 (other petition’s analysis
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`of the second element (part 3) of claim 8 of the ’812 patent); see also id.,
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`Qualcomm-1018 (’812 Patent), claim 8. Although the present petition purports to
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`analyze the feature related to the power management unit’s association of
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`performance states under the caption for the third element (part 3) of claim 1 of the
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`’216 patent, in fact the first several pages of the petition’s analysis is directed to
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`the ’812 feature of a processor waking up in a different performance state from
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`which it operated prior to entering a sleep state. See Apple-1003 (’812 patent),
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`14:18-21 (claim 8 reciting “wherein the processor is transitioning from a sleep
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`17
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`state, and wherein the wakeup state is different from a prior performance state at
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`which the processor was operating prior to entering the sleep state”).
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`18
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`19
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Pet., 33-36 (annotations added); see also id.; Apple-1002 (IPR2019-00321
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`Petition) 38-42 (substantially identical analysis of the second element (part 3) of
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`claim 8 of the ’812 patent).
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`The petition fails to explain what, if any, relevance the mapping of
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`Mandelblat’s disclosure to the processor wakeup feature from claim 8 of the ’812
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`patent has on the performance state association feature required by claims 1 and 8
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`of the ’216 patent. Indeed, none of the text from page 33 of the petition through
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`the first two paragraphs of page 36 even once mentions the power management
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`unit in which the performance states are required to be associated in the ’216
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`patent. See Pet., 33-36.
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`B.
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`The Petition’s Focus On Common Control Of The Performance
`Domains Is Insufficient
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`What remains of the petition’s analysis after discounting the discussion of
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`the different feature from the ’812 patent is a bare, conclusory assertion that
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`Mandelblat anticipates the ’216 performance state association feature by virtue of a
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`power management unit (e.g., Mandelblat’s power management logic (PML) 906
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`and memory PML 907) that manages performance states of both processor core 1
`
`(902) (i.e., a component that the petition maps to a processor in a “first
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`performance domain”) and dynamically sizeable memory 905 (i.e., a component
`
`that the petition maps to a “second performance domain”):
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`Pet., 36 (highlighting added); see also id., 27-29 (petitioner’s mapping of core 1
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`(902) in a first performance domain and memory 905 in a second performance
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`
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`domain).
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`However, the petition’s focus on common control of the performance states
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`in a pair of performance domains is misplaced and insufficient to demonstrate that
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`a first performance state of a second performance domain is actually associated
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`with a second performance state of a first performance domain in the power
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`management unit as recited in claims 1 and 8 of the ’216 patent. There is no
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`dispute that Mandelblat’s PML 906 (including memory PML 907) is configured to
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`effect transitions of processor cores (e.g., core 1 (902)) between various power
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`states including active state C0 and reduced power (e.g., sleep) states C1, C2, C3,
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`and C4. See, e.g., Qualcomm-1003 (Mandelblat), [0037] (“The power
`
`management module … may control power management of the processor(s) and/or
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`Proceeding No. IPR2019-00322
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`of the individual core(s) 902 and 904, including transitions between various power
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`states. Where the operating system 924 supports ACPI, for example, the power
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`management module 907 may control and track the c-states of the various core(s)
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`and/or the p-states.”). Similarly, it is not disputed that Mandelblat’s PML 906
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`(including memory PML 907) is also configured to effect changes to the size of
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`dynamically sizeable memory 905. See, e.g., id., [0038] (“[T]he memory power
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`management module transitions between three high-level states (intermediate
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`states may be included for various embodiments): Full Cache size 1205, Minimum
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`Cache Size 1210, and Stop Shrink 1215.”). But the mere fact that PML 906 and
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`memory PML 907 provide centralized control to manage states of both core 1
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`(902) and memory 905 does not in itself demonstrate any association in the power
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`management unit between a first performance state of memory 905 and a second
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`performance state of core 1 (902).
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`The petition’s failure to provide any additional explanation or evidence
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`directed to this limitation beyond the common control theory is in itself a critical
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`flaw that warrants dismissal of Ground 1. See 37 C.F.R. §42.104(b) (evidence
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`must be presented in the petition); In re: Magnum Oil Tools Int’l, Ltd., Case No.
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`2015-1300, Slip Op. at p. 26 (Fed. Cir. July 25, 2016) (“[W]e find no support for
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`the PTO’s position that the Board is free to adopt arguments on behalf of
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`petitioners that could have been, but were not, raised by the petitioner during an
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`IPR.”).
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`To the extent Petitioner would argue that any of the petition’s discussion
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`under the third element (part 3) of claim 1 that precedes the explanation of the
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`common control theory—i.e., the copied-and-pasted portion analyzing the
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`processor wakeup state feature from the ’812 petition (IPR2019-00321)—
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`materially supplements Petitioner’s analysis to show how Mandelblat somehow
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`discloses the claimed association of performance states, Apple respectfully
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`disagrees. As mentioned above, the copied-and-pasted discussion never even
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`mentions Mandelblat’s PML 906 or memory PML 907 (the alleged “power
`
`management unit”), and thus on its face does not address how performance states
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`of core 1 (902) and memory 905 would be associated with each other in the power
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`management unit, as required by claims 1 and 8. At most, the copied-and-pasted
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`portion of the petition describes a causal relationship between C-state transitions of
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`core 1 (902) and size transitions of memory 905. See, e.g., Pet., 35 (“Table 1
`
`identif[ies] that Core 1 entered the C4 sleep state, and that Dynamically Sizeable
`
`Memory 905 may have further shrunk to an intermediate or minimum size.”); id.
`
`36 (“Table 1, in the column labeled Wakeup Performance State 2, reflects core 1
`
`awakening from the sleep state to the C0 state, and Dynamically Sizeable Memory
`
`905 transitioning to the full size.”). But here again, the petition is deficient
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`because claims 1 and 8 clearly require more than just a causal relationship in which
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`the transition of a first performance domain including the processor (e.g., core 1
`
`(902)) to a second performance state (e.g., a particular C-state) prompts the power
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`management unit to transition a second performance domain (e.g., memory 905) to
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`a first performance state. This causal relationship is already recited in the third
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`element (part 2) of claim 1 and the first portion of the second element of claim 8,
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`and thus any reading of the claims that requires no more than cause and effect in
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`the state transitions of the first and second performance domains would effectively
`
`render the additional limitations about the association of performance states in the
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`power management unit superfluous. See Wasica Finance GMBH v. Continental
`
`Automotive Systems, Inc., Case No. 2015-2078, p. 28, FN 10 (Fed. Cir. 2017) (“It
`
`is highly disfavored to construe terms in a way that renders them void,
`
`meaningless, or superfluous.”) (citing Bicon, Inc. v. Straumann Co., 441 f.3d 945,
`
`950-51 (Fed. Cir. 2006)).
`
`C. Mandelblat Does Not Associate The Performance States Of First
`And Second Performance Domains In The Power Management
`Unit As Claimed In The ’216 Patent
`
`Moreover, apart from the deficiencies in Petitioner’s own analysis of this
`
`limitation, Mandelblat also fails in substance to disclose the requisite association of
`
`performance states between the first and second performance domains. The
`
`petition alleges that “the expansion of the Dynamically Sizeable Memory 905 to
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`24
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`Proceeding No. IPR2019-00322
`Attorney Docket No: 39521-0069IP1
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`the full cache size, the first performance state, is associated with the transition of
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`Core 1 (902) to the C0 state, the second performance state in PML 906 and
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`Memory PML 907, the power management unit.” Pet., 36. But this is not an
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`accurate description of how Mandelblat’s system operates. Mandelblat instead
`
`explains that transitions between memory sizes are “managed according to certain
`
`variables which may be stored, for example, in a register or other data store,” and
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`those variables include “1) all but one core in low power state, 2) ratio<=shrink
`
`threshold, 3) a c-state timer output, 4) at least one core in low power state, 5)
`
`ratio>shrink threshold, 6) expand and/or 7) shrink.” Qualcomm-1003
`
`(Mandelblat), [0039]. Memory PML 907 monitors the states of these variables and
`
`determines whether to shrink or expand memory 905 from its current size based on
`
`the states of such variables. See id., [0045] (“The ‘expand’ variable may be set or
`
`dynamic memory expansion may be otherwise enabled … if the ratio>shrink
`
`threshold, at least one core in low power state and/or the C0 time>threshold.”),
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`[0046] (“The ‘shrink’ variable may be set or dynamic memory size reduction may
`
`be otherwise enabled … if the ratio<=shrink threshold is set and all but 1 core in
`
`low power state is set.”), FIG. 12. Noticeab