(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2007/0043965 A1
`Mandelblat et al.
`(43) Pub. Date:
`Feb. 22, 2007
`
`US 2007.0043965A1
`
`(54) DYNAMIC MEMORY SZING FOR POWER
`REDUCTION
`
`(75) Inventors: Julius Mandelblat, Haifa (IL); Moty
`Mehalel, Haifa (IL); Avi Mendelson,
`Haifa (IL); Alon Naveh, Ramet
`Hasharon (IL)
`Correspondence Address:
`INTEL CORPORATION
`C/O INTELLEVATE, LLC
`P.O. BOX S2OSO
`MINNEAPOLIS, MN 55402 (US)
`(73) Assignee: INTEL CORPORATION
`(21) Appl. No.:
`11/208,935
`
`(22) Filed:
`
`Aug. 22, 2005
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`G06F L/26
`(52) U.S. Cl. .............................................................. 713/324
`
`(57)
`
`ABSTRACT
`
`Systems and methods of dynamic memory for power reduc
`tion are described with respect to a memory with a coupled
`sleep device. In one embodiment, the operating require
`ments can reflect amount of memory required to perform
`commensurate operations. Memory power management
`logic is used to coordinate memory requirements with
`operating requirements. The sleep device is able to enable or
`disable the memory based on the requirements to reduce
`power consumption.
`
`
`
`
`
`
`
`
`
`
`
`instantiate (1100)
`
`Monitor at least one core of one or more processors, and at
`least one memory with more than one way (1102)
`
`Determine a required number of ways (1104)
`
`While the required number is less than an enabled number
`of ways, disable one or more ways such that the enabled
`number is equivalent to the required number (1106)
`
`While the required number is more than the enabled
`number, enable one or more ways such that the enabled
`number is equivalent to the required number (1108)
`
`(Optional) Prior to the disabling, scan the one or more
`ways for data to be at least written to at least one of a RAM
`or a storage (1110)
`
`Complete (1112)
`
`Qualcomm, Exhibit 1003, Page 1
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 1 of 7
`
`US 2007/0043965 A1
`
`100
`
`102n
`
`102b
`
`102a
`
`Way-n
`
`Way-1
`
`Way-0
`
`En-n
`
`En-1 H
`
`En-O
`
`N7
`
`104n
`
`Q
`
`N
`
`104b.
`
`104a
`
`20
`
`
`
`204
`
`FG. 2
`
`Qualcomm, Exhibit 1003, Page 2
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 2 of 7
`
`US 2007/0043965 A1
`
`
`
`Qualcomm, Exhibit 1003, Page 3
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 3 of 7
`
`US 2007/0043965 A1
`
`600
`
`602
`
`606b
`
`606a
`
`
`
`En
`
`800
`
`802
`
`En L
`
`806b
`
`W
`
`806a
`
`W
`
`704
`
`804
`
`Qualcomm, Exhibit 1003, Page 4
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 4 of 7
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`US 2007/0043965 A1
`
`
`
`
`
`
`
`
`
`
`
`Memory 912
`
`Power Management Logic
`(PML) 906
`
`Memory PML 907
`
`
`
`
`
`One or More Processor(s) 901
`Micro-
`Dynamically
`code 926
`Sizable Memory
`905
`
`Core 1
`902
`
`COre 2
`904
`
`Graphical
`Interface
`920
`
`Chipset 916
`
`FIG. 9
`
`One or
`More Clock
`Sources
`908
`
`
`
`RAM 91.8a
`Storage 918b
`OS 924
`
`NetWork
`Interface
`922
`
`Qualcomm, Exhibit 1003, Page 5
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 5 of 7
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`US 2007/0043965 A1
`
`Instantiate (1000)
`
`
`
`Monitor a processor and a memory (1002)
`
`Determine the processor requirements and the memory
`requirements (1004)
`
`Determine a plurality of requirements from the processor
`requirements and the memory requirements (1006)
`
`Determine when one or more of the plurality of
`requirements are satisfied (1008)
`
`Adjust the memory based on at least one of the plurality of
`requirements being satisfied (1010)
`
`Complete (1012)
`
`F.G. 10
`
`Qualcomm, Exhibit 1003, Page 6
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 6 of 7
`
`US 2007/0043965 A1
`
`
`
`Instantiate (1100)
`
`
`
`Monitor at least one core of one or more processors, and at
`least one memory with more than one way (1102)
`
`Determine a required number of ways (1104)
`
`While the required number is less than an enabled number
`of ways, disable one or more ways such that the enabled
`number is equivalent to the required number (1106)
`
`While the required number is more than the enabled
`number, enable one or more ways such that the enabled
`number is equivalent to the required number (1108)
`
`(Optional) Prior to the disabling, scan the one or more
`ways for data to be at least written to at least one of a RAM
`or a storage (1110)
`
`Complete (1112)
`
`F.G. 11
`
`Qualcomm, Exhibit 1003, Page 7
`
`

`

`Patent Application Publication Feb. 22, 2007 Sheet 7 of 7
`
`US 2007/0043965 A1
`
`
`
`
`
`ALL BUT 1 CORE IN LOW
`POWER STATE & #EXPAND
`
`STOP
`SHRINK
`1215
`
`
`
`
`
`
`
`EXPAND
`
`SHRINK & EXPAND
`
`RESET
`
`SHRINK & EXPAND
`
`FIG. 12
`
`Qualcomm, Exhibit 1003, Page 8
`
`

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`US 2007/0043965 A1
`
`Feb. 22, 2007
`
`DYNAMIC MEMORY SZING FOR POWER
`REDUCTION
`
`BACKGROUND
`0001) 1. Technical Field
`0002 One or more embodiments of the present invention
`generally relate to integrated circuits and/or computing
`systems. In particular, certain embodiments relate to power
`management of memory circuits.
`0003 2. Discussion
`0004 As the trend toward advanced processors with
`more transistors and higher frequencies continues to grow,
`computer designers and manufacturers are often faced with
`corresponding increases in power consumption. Further
`more, manufacturing technologies that provide faster and
`Smaller components can at the same time result in increased
`leakage power. Particularly in mobile computing environ
`ments, these increases can lead to overheating, which may
`negatively affect performance, and can significantly reduce
`battery life.
`0005 With the focus on performance and small form
`factors, in a microprocessor, for example, cache memory
`sizes are increasing to achieve the best performance for a
`given silicon area. These recent trends toward even larger
`memory sizes have increased the portion of power consump
`tion associated with memories. As a result, the leakage
`power that is dissipated by the memory is quite significant
`relative to the total power of the central processing unit
`(CPU).
`BRIEF DESCRIPTION OF THE DRAWINGS
`0006 Various advantages of embodiments of the present
`invention will become apparent to one skilled in the art by
`reading the following specification and appended claims,
`and by referencing the following drawings, in which:
`0007 FIG. 1 is a block diagram of an example of a
`memory architecture to implement dynamic sizing accord
`ing to one embodiment of the invention;
`0008 FIG. 2 is a diagram of another example of a
`memory architecture to implement dynamic sizing accord
`ing to one embodiment of the invention;
`0009 FIG. 3 is a diagram of a cell-level example of a
`memory architecture to implement dynamic sizing accord
`ing to one embodiment of the invention;
`0010 FIG. 4 is a diagram of a cell-level example of a
`memory architecture to implement dynamic sizing accord
`ing to one embodiment of the invention;
`0011
`FIG. 5 is a diagram of another cell-level example of
`a memory architecture to implement dynamic sizing accord
`ing to one embodiment of the invention;
`0012 FIGS. 6-8 are diagrams of various examples of
`sleep devices according to embodiments of the invention;
`0013 FIG. 9 is a system-level block diagram of an
`example computer system according to embodiments of the
`invention;
`0014 FIG. 10 is a flowchart of an example of a method
`of managing dynamic memory sizing according to one
`embodiment of the invention;
`
`FIG. 11 is a flowchart of another example of a
`0.015
`method of managing dynamic memory sizing according to
`one embodiment of the invention; and
`0016 FIG. 12 is a state diagram of an example of a
`dynamic memory management machine according to one
`embodiment of the invention.
`
`DETAILED DESCRIPTION
`0017. The amount of memory that may actually be
`required by a computer system and/or associated Software
`often varies with respect to time. For typical applications,
`for example, only a small portion of the memory may be
`needed at any given time. According to one or more embodi
`ments, a memory, Such as the memory of FIG. 1, may be
`dynamically sized to reduce the power requirements of a
`memory circuit and the system in which it is used. Specifi
`cally, as is described herein, embodiments of the invention
`may provide a reduction in power consumption without
`Substantially affecting performance by disabling one or more
`Sub-sections of a memory when those sub-sections are not
`needed and/or are unselected.
`0018 FIG. 1 shows a representation of a dynamically
`sizable memory 100 according to one embodiment. The
`dynamically sizable memory of the example embodiment of
`FIG. 1 is an n-way associative cache memory that may be
`implemented, for example, using static random access
`memory (SRAM). The dynamically sizable memory 100
`includes a plurality of sub-sections 102a, 102b-102n (each
`of which are ways in this particular example), each sepa
`rately coupled to a plurality of sleep devices 104a, 104b
`104n, respectively, as shown, such that each of the sub
`sections or ways 102 may be selectively enabled/disabled.
`The sleep devices 104, according to one or more embodi
`ments of the invention, may include a sleep transistor that is
`used to selectively couple? decouple an associated Sub-sec
`tion of a memory to a power source.
`0019 FIG. 3 illustrates an example sub-section or way
`300 of such an implementation at the transistor level. The
`way 300 includes cells 302a, 302b-302m coupled to a sleep
`device 304. The power supply of the way 300 may be
`coupled to global power lines of the host integrated circuit
`through a serial transistor 304, which may be referred to
`herein as a sleep device or sleep transistor. FIG. 4 shows a
`single cell 402 that may correspond to one of the cells 302
`of FIG. 3. More specifically, as shown in FIGS. 3 and 4, the
`input port of the sleep devices 304 and 404 is coupled to the
`power Supply (VSS in this example) and the output port is
`coupled to the array supply, which may be referred to as the
`virtual power supply of the array or VVss.
`0020 While the example embodiments of FIGS. 3 and 4
`show a sleep device coupled between a sub-section of the
`memory and Vss, for alternative embodiments, the sleep
`device may be instead be coupled between the sub-section of
`the memory and Vcc as shown for the cell 502 in FIG. 5, or
`a sleep circuit may be coupled between each of Vcc and Vss
`and the associated Sub-section.
`0021. In accordance with one or more embodiments, the
`sleep device may be on as long as the associated way is
`active and may be turned off if it is determined that the
`associated way is to be deactivated. As a result of turning off
`a sleep device and disabling an associated Sub-section of
`
`Qualcomm, Exhibit 1003, Page 9
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`US 2007/0043965 A1
`
`Feb. 22, 2007
`
`memory, the rail-to-rail Voltage of the virtual power Supply
`is reduced. The leakage power of the associated memory
`array may therefore be reduced since the leakage is depen
`dent on the voltage (See Equation 1 below).
`(Eq. 1)
`Ilkg=k V"
`is Leakage current; V is Rail-to-rail
`0022) Where I
`Voltage; k may be a constant; and n may be, but is not
`required to be, greater than 3.
`0023 FIGS. 6-7 show alternative embodiments of the
`sleep device, according to embodiments of the invention.
`FIG. 6 shows a sleep device 604 with two sleep transistors,
`606a and 606b. The advantages of this configuration
`include, but are not limited to, cases where sleep transistor
`606a has a different resistance value than 606b. In embodi
`ments, by reducing the size of the sleep transistor 606a, the
`voltage at the gate of the sleep transistor 606a may be higher
`than GROUND and therefore doesn't require as much
`voltage to disable a way or cell 602.
`0024. Similarly, other advantages are provided by the
`sleep device 704 shown in FIG. 7, and sleep device 804
`shown in FIG. 8. The sleep device 704 may provide for a
`gradual reduction in the power provided to a way or cell 702.
`The sleep device 804 may provide for a limited reduction in
`power provided to a way or cell 802. The alternative sleep
`devices of FIGS. 6-8 provide alternative embodiments
`which are illustrative of the types of sleep devices which
`may be employed by one of ordinary skill in the art, based
`at least on the teachings provided herein, according to
`embodiments of the invention and are not intended to limit
`the scope of the invention. Moreover, as may be apparent to
`one of ordinary skill, these various embodiments of sleep
`devices may have applications which are more specialized
`than others and may be more advantageous, therefore, for
`certain dynamically sizable memory.
`0.025
`For other embodiments, various circuit and/or
`other techniques may be used to implement alternative sleep
`logic and/or to provide functionality similar to the sleep
`devices using a different approach. In one embodiment of
`the invention, for example, different sub-sections of a
`memory may be implemented on different power planes
`such that sub-sections of the memory may be enabled/
`disabled through power plane control. Other approaches are
`within the scope of various embodiments.
`0026. While a plurality of individual pairs of ways and
`associated sleep devices are shown here, embodiments of
`the invention may readily be implemented in various
`arrangements without departing from the spirit and scope of
`the embodiments of the invention. FIG. 2, for example,
`shows a dynamic memory 200 according to an alternative
`embodiment of the invention that includes a plurality of
`ways 202a, 202b-202n, where n may be a number greater
`than one, coupled to a single sleep device 204. The ways and
`sleep devices may be similar in function and design to those
`described in FIG. 1 except, in this embodiment, the sleep
`device 204 may be deactivated to disable all of the ways
`associated with it.
`0027) Further, while an n-way associative cache memory
`implemented on a microprocessor is described herein for
`purposes of illustration, it will be appreciated that embodi
`ments of the invention may be applied to other types of
`
`memory, including cache memories having a different archi
`tecture and/or memories implemented on another type of
`integrated circuit device.
`0028. For other embodiments, for example, other parti
`tions, Sub-sections or portions of memory, including cache
`memories of various levels, may be selectively enabled
`and/or disabled using one or more of the approaches
`described herein. The illustrated ways may therefore provide
`a convenient grouping of cells, such as an array, but use of
`the term “ways is not intended to limit the spirit or scope of
`the invention.
`0029 Referring back to FIG. 1, as described above, sleep
`device 104a may be deactivated to disable way 102a when
`way 102a is not needed, thus providing a leakage power
`savings or activated to enable way 102a. It is noted that the
`use of the term enable with respect to the memory refers to
`the powering, at any active level, of the memory; while the
`use of the term disable refers to the removal or blocking of
`power to the memory. From a logical standpoint, according
`to embodiments of the invention described herein, enabled
`memory may be accessed for READ/WRITE operations,
`while disabled memory may not.
`0030. According to one or more embodiments, to enable
`and/or disable associated Sub-sections of the dynamically
`sizable memory 100, the sleep devices 104a-104m may be
`controlled by memory power management logic or other
`logic (not shown), which may be implemented in a host
`integrated circuit, a computer system or in software. An
`example of Such an implementation is described below in
`reference to FIG. 9.
`0031 FIG.9 is a block diagram of a computer system 900
`having a dynamically sizable memory 905 according to an
`example embodiment of the invention. The computer system
`900 may be a personal computer system such as, for
`example, a laptop, notebook or desktop computer system.
`The computer system 900 may include one or more proces
`sors 901, which may include sub-blocks such as, but not
`limited to, one or more cores, illustrated by core 902 and
`core 904, the dynamically sizable cache memory 905, which
`may, for example, be an L2 cache memory, and power
`management logic 906, which may include memory power
`management logic 907. One or more of the processor(s) 901
`may be an Intel(R) Architecture microprocessor. For other
`embodiments, the processor(s) may be a different type of
`processor Such as, for example, a graphics processor, a
`digital signal processor, an embedded processor, etc. and/or
`may implement a different architecture.
`0032. The one or more processors 901 may be operated
`with one or more clock sources 908 and provided with
`power from one or more voltage sources 910. The one or
`more processors 901 may also communicate with other
`levels of memory, such as memory 912. Higher memory
`hierarchy levels such as system memory (RAM) 918a and
`storage 918b, Such as a mass storage device which may be
`included within the system or accessible by the system, may
`be accessed via host bus 914 and a chip set 916.
`0033. In addition, other functional units such as a graph
`ics interface 920 and a network interface 922, to name just
`a few, may communicate with the one or more processors
`901 via appropriate busses or ports. For example, the
`memory 912, the RAM 918a, and/or the storage 918b may
`
`Qualcomm, Exhibit 1003, Page 10
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`Feb. 22, 2007
`
`include Sub-sections that provide for dynamic sizing of the
`memory according to embodiments of the invention. Fur
`thermore, one of ordinary skill would recognize that some or
`all of the components shown may be implemented using a
`different partitioning and/or integration approach, in varia
`tion to what is shown in FIG. 9, without departing from the
`spirit or scope of the embodiment as described.
`0034) For one embodiment, the storage 918b may store
`Software such as, for example an operating system 924. For
`one embodiment, the operating system is a Windows.(R)
`operating system, available from Microsoft Corporation of
`Redmond, Washington, that includes features and function
`ality according to the Advanced Configuration and Power
`Interface (ACPI) Standard (for example, ACPI Specifica
`tion, Rev. 3.0, Sep. 2, 2004: Rev. 2.0c, Aug. 25, 2003: Rev.
`2.0, Jul. 27, 2000, etc.) and/or that provides for Operating
`System-directed Power Management (OSPM). For other
`embodiments, the operating system may be a different type
`of operating system such as, for example, a Linux operating
`system.
`0035) While the system 900 is a mobile personal com
`puting system, other types. of systems such as, for example,
`other types of computers (e.g., handhelds, servers, tablets,
`web appliances, routers, etc.), wireless communications
`devices (e.g., cellular phones, cordless phones, pagers, per
`Sonal digital assistants, etc.), computer-related peripherals
`(e.g., printers, Scanners, monitors, etc.), entertainment
`devices (e.g., televisions, radios, Stereos, tape and compact
`disc players, video cassette recorders, camcorders, digital
`cameras, MP3 (Motion Picture Experts Group, Audio Layer
`3) players, video games, watches, etc.), and the like are also
`within the scope of various embodiments. The memory
`circuits represented by the various foregoing figures may
`also be of any type and may be implemented in any of the
`above-described systems.
`0036) The memory power management module 907 of
`one embodiment may be implemented as a finite state
`machine (FSM). A state diagram corresponding to the opera
`tion of the memory power management module 907 of one
`example embodiment is shown in FIG. 12.
`0037. The memory power management module 907 may
`operate in cooperation with other features and functions of
`the processor(s) 901 Such as the power management module
`906. In particular, the power management module of one
`embodiment may control power management of the proces
`sor(s) 901 and/or of the individual core(s) 902 and 904,
`including transitions between various power states. Where
`the operating system 924 supports ACPI, for example, the
`power management module 907 may control and track the
`c-states of the various core(s) and/or the p-states. The power
`management module may also store or otherwise have
`access to other information to be used in managing the
`dynamic memory sizing approach of one or more embodi
`ments such as, for example, the operating Voltage/frequency
`of the processor and/or one or more cores, a minimum cache
`memory size, timer information, and/or other information
`stored in registers or other data stores.
`0038. With continuing reference to FIGS. 9 and 12, the
`memory power management module transitions between
`three high-level states (intermediate states may be included
`for various embodiments): Full Cache size 1205, Minimum
`Cache Size 1210, and Stop Shrink 1215. The transitions
`
`between these states may be managed in cooperation with a
`microcode (pcode) or other module 926 coupled to the
`memory 905. For the Full Cache Size state 1205, the
`microcode 926 is requested to return the cache back to its
`full size. This is the default (reset) state. For the Minimum
`Cache Size state 1210, the microcode 926 is requested to
`shrink the cache memory down to its minimum size. For
`Some embodiments, the minimum size is programmable
`(e.g. via microcode) and may be determined by various
`design considerations such as, but not limited to, typical
`Software profiles, acceptable delays in reducing cache size,
`a minimum size below which the memory is inoperable
`and/or other factors. It is noted that any minimum size for
`the memory may be dependent upon the state of the system,
`and therefore may not be constant over time, as one of
`ordinary skill in the art would appreciate. For the Stop
`Shrink state 1215, the microcode is requested to stop the
`cache shrink sequence. The ways or other Sub-sections that
`have been disabled or shut down remain disabled, but the
`effective cache size is not reduced any further.
`0039 Transitions between these states may be managed
`according to certain variables which may be stored, for
`example, in a register or other data store (not shown). For
`one embodiment, for example, these variables may include,
`but are not limited to 1) all but one core in low power state,
`2) ratio<=shrink threshold, 3) a c-state timer output, 4) at
`least one core in low power state, 5) ratio>shrink threshold,
`6) expand and/or 7) shrink.
`0040. For the processor 901 of FIG. 9 including 2 cores
`and operating according to the ACPI specification, the
`variable “all but one core in low power state' may be set for
`one embodiment in response to determining that one core is
`already in a C4 state while the other, which may continue to
`execute during the dynamic memory sizing operations, is
`still in an active state (CO). For one embodiment, this
`variable should not be set if any of the cores have a break
`event pending. If two (or more) cores are present on the
`processor 901, but one (or more) of the cores is disabled or
`removed, then that core may be disregarded during the
`decision-making process.
`0041) The “ratio<=shrink threshold” variable may be set
`in response to the processor 901 or one of its cores, for one
`embodiment, being programmed to operate at a lower/equal
`frequency than a predetermined frequency set as the shrink
`threshold. The shrink threshold may be programmed for
`Some embodiments and may be equal to Zero.
`0042. One or more timer outputs may also be considered
`in determining whether to transition between states. For one
`embodiment, for example, a timer, Such as an 8-bit down
`counter, for example, may be used to count the contiguous
`time that the processor (or a core) spends in the active or CO
`state and may indicate when that time exceeds a pre
`programmed threshold. For this example, a variable “CO
`timer over threshold’ may be used.
`0043. The variable “at least one core in a low power
`state.” for the example processor and system shown in FIG.
`9, may be set when one of the cores has entered a stable C1,
`C2 or C3 State and not the C4 or WFS State.
`0044) The “ratio>shrink threshold variable may be set
`when the processor or one of its cores is programmed to
`operate at a higher frequency than the shrink threshold. For
`
`Qualcomm, Exhibit 1003, Page 11
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`
`Feb. 22, 2007
`
`some embodiments, if the shrink threshold equals 0, this
`ratio need not be taken into account when determining
`whether to expand the memory.
`0045. The “expand variable may be set or dynamic
`memory expansion may be otherwise enabled for one
`embodiment if the ratio>shrink threshold, at least one core
`in low power state and/or the C0 timer-threshold. For other
`embodiments and/or implementations, the expand variable
`may be set under different conditions or in response to
`different inputs.
`0046) The “shrink” variable may be set or dynamic
`memory size reduction may be otherwise enabled for one
`embodiment if the ratio<=shrink threshold is set and all but
`1 core in low power state is set.
`0047. With continuing reference to FIGS. 9 and 12, a
`transition from the Full Cache Size state 1205 to the Mini
`mum Cache Size state 1210 may be undertaken for one
`embodiment for a multi-core processor in response to deter
`mining that one core is already in the C4 (or other low
`power) state, and when the processor 901 is operating below
`the shrink threshold p-state. It may be assumed then that the
`effective cache reduction will not substantially affect per
`formance and therefore can be initiated. Concurrently, it
`may be confirmed that an effective memory expansion is not
`needed, e.g. that the C0 timer has not timed out indicating
`a possible rise in the activity factor.
`0.048. Once microcode has entered the C4 flow on the
`core that is in the C4 state, the microcode may detect the
`request to reduce the effective size of the memory to the
`Minimum Cache Size and begin disabling ways or other
`sub-sections of the memory. For one embodiment, in the
`minimum cache size state 1210, ways or other sub-sections
`may be disabled one at a time. Other approaches may be
`used for other embodiments.
`0049. During the dynamic memory size reduction pro
`cess, microcode may stop the shrink process after program
`mable chunks or other intervals to determine whether the
`shrink variable is still asserted. If it is not, the shrink process
`will be frozen. Further, if a pending interrupt occurs, the
`shrink process will be interrupted.
`0050. Once the pre-defined number of ways or other
`Sub-sections has been shut down, the remaining core(s) may
`indicate a C4 state causing the entire processor 901 to enter
`into a C4 state. For some embodiments, this sequence may
`be repeated for every C4 entry of the last core until the cache
`memory has reached the pre-defined minimum size. From
`that point, a shrink request may be disregarded.
`0051) While in the Minimum Cache Size state 1210, if
`one core has exited the C4 state and the conditions for an
`expand operation (or setting of an expand variable) have not
`been met or a pending break request exists for any core, the
`shrink variable may be negated and shrink process may be
`halted (i.e., the Stop Shrink State 1215 may be entered). This
`may be leave the memory 905 in an intermediate effective
`size until either the conditions to continue the shrink occur
`or conditions for an expand operation occur. If the effective
`memory 905 size is below a given number of ways or other
`Sub-sections, such as a minimum number of ways below
`which the memory 905 will not operate properly and has
`either not reached “O'” or a minimum size has been pro
`grammed at a given level, e.g. “re-open to 2', the microcode
`
`may need to re-open the memory so that at least a given
`number of ways or other Sub-sections are operational.
`0.052 From either the Minimum Cache Size state 1210 or
`the Stop Shrink State 1215, an indication to effectively
`expand the memory 905 may occur. Expanding the memory
`905 may be based on one or more indicators that an activity
`factor has increased. For one embodiment, indicators may
`include a transition to a higher p-state than the shrink
`threshold, one of the core(s) transitioning to a different
`power state, e.g. C1/2/3 instead of aiming for C4 and/or the
`C0 timer exceeding its threshold. Such occurrences may
`indicate that a program is in one of its longer activity
`stretches. If any of the above occur, the expand variable may
`be asserted or effective expansion of the memory 905 may
`be otherwise initiated.
`0053 For one embodiment, effective memory expansion
`may occur Substantially instantaneously, i.e. not over mul
`tiple cycles apart from some delay to prevent current spikes.
`After expansion, the microcode will disregard an expand
`request. In addition to the above, upon every core C4 exit for
`Some embodiments, microcode may check the shrink vari
`able (or shrink control field), microcode may expand the
`memory back to a minimum number of ways before pro
`ceeding with a break to a higher power state.
`0054 For the shrink process, some additional consider
`ations may apply to one or more embodiments. For example,
`for Some embodiments, microcode may need to control the
`memory shrink segment entry with a semaphore so that only
`a single core may access the memory interface at one time.
`(It is assumed that the other core is in a core C4 state for the
`example embodiment described above, but this may not be
`guaranteed during an expand segment or process. In any
`case, event timing may cause a break before an atomic
`segment of the shrink flow is completed. The semaphore
`may ensure that the second core will not access the memory
`interface until the shrink/expand process is completed).
`0055) Further, to prevent memory 905 issues microcode
`may need to ensure that a second (or other) core is blocked
`into core C4 state when the shrink/reduction process occurs.
`For some embodiments, the may happen in hardware based
`on the same semaphore but microcode may need to account
`for the delay factor by rechecking the shrink indication
`before starting the actual atomic shrink flow.
`0056. Due to the potentially long shrink flow, microcode
`may need to periodically detect and ensure that there are no
`breaks pending and that a request to halt the shrink flow has
`not occurred. This may be done periodically after every
`"chunk” by testing if the shrink variable is still asserted. If
`microcode detects that the shrink conditions have ended, it
`should release the semaphore to ensure other core(s) can
`respond to break events and proceed with other flows. The
`shrink request/variable may be negated if any pending break
`events are detected and therefore, no interrupt window may
`need to be opened in the middle of the flow.
`0057 For some embodiments, as mentioned above, there
`may be a minimum effective size below which the memory
`905 may not operate. For example, if the minimum size for
`the memory 905 is 2 ways (i.e. it may not function properly
`with only 1 way enabled), the shrink process may proceed
`directly from 2 ways to 0 ways enabled even if it is
`programmed to shrink 1 way or other Sub-section at a time.
`
`Qualcomm, Exhibit 1003, Page 12
`
`

`

`US 2007/0043965 A1
`
`Feb. 22, 2007
`
`For a “normal expand flow for one embodiment,
`0.058
`microcode may try to capture the semaphore on every core
`C4 exit (unwind) regardless of whether an expand is
`required. Thus, the sleeping or low power core (for a
`multi-core processor) may not be able to begin execution
`during a shrink flow preventing possible contention with the
`shrink process. Memory expansion may be performed dur
`ing an interrupt microcode handling routine. For some
`embodiments, as mentioned above, where the memory is
`inoperable below a minimum operable size, it may be
`expanded directly to the minimum operable size under
`certain conditions. For example, in an embodiment of the
`invention, in the case where a processor may implement an
`MWAIT state, an auto-expansion may be implemented on
`every MWAIT exit and the memory may proceed directly to
`the minimum operable effective size.
`0059) Machine Check Architecture (MCA) exceptions
`may occur either on a core exiting the shrink flow (e.g. a
`parity error on the memory 905) or on the other core(s), if
`its clock(s) have restarted and/or it has initiated a core C4
`exit. In both cases, the memory 905 may have been reduced
`below the minimum operable size and may not have reached
`Zero effective size. Since this is not a legal operational size
`and since it may be assumed that C4 may not be entered
`again Soon, m