(12)
`
`United States Patent
`Kurts et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,363.523 B2
`Apr. 22, 2008
`
`USOO7363523B2
`
`(54) METHOD AND APPARATUS FOR
`CONTROLLING POWER MANAGEMENT
`STATE TRANSTIONS
`
`(75) Inventors: Tsvika Kurts, Haifa (IL); Alon Naveh,
`R t Hash
`(IL); Efraim Rot
`alatastroyiram Kotem,
`EMI, It is Eiger,
`111 Sporo,
`; Jorge P.
`Rodriguez, Portland, OR (US); Ernest
`Knoll, Haifa (IL); David I. Poisner,
`Folsom, CA (US)
`
`(73) Assignee: lots Corporation, Santa Clara, CA
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 327 days.
`
`(21) Appl. No.: 10/931,565
`(22) Filed:
`Aug. 31, 2004
`(65)
`Prior Publication Data
`US 2006/OO47986 A1
`Mar. 2, 2006
`ar. Z.
`
`(51) Int. Cl
`C
`ge. T
`(2OO 6. 3.
`GOIR 2/06
`.01)
`(
`(52) U.S. Cl. .........r r 713/320; 713/323; 702/60
`(58) Field of Classification Search ................ 713/320,
`713/323, 324; 702/60
`See application file for complete search history.
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`6/1996 Crump et al. ............... T13,323
`9, 1996 Dunstan et al. ............. 395/750
`2/2000 Wang et al. ................ T13,320
`
`5,530,879 A *
`5,560,022 A
`6,021,500 A
`
`
`
`9/2000 Orton et al. .................. 327/44
`6,118,306 A
`8/2001 Pole, II et al. .
`... 713,300
`6,272.642 B2
`12/2002 Ewertz .......................... T13/1
`6,499,102 B1
`2/2003 Stapleton et al. .....
`... 713,330
`6,523,128 B1
`3/2003 Bhatia et al. .....
`... 700,293
`6,535,798 B1
`5/2003 Forbes ................
`... T13,323
`6,571,341 B1
`6/2003 Wunderlich et al. ........ 713/322
`6,584,573 B1
`6,633,987 B2 10/2003 Jain et al. .............
`... 713,300
`6,691,234 B1
`2/2004 Huff ..............
`... 713,300
`6,691.238 B1
`2/2004 Forbes et al. ..
`... 713,323
`6,823,240 B2 11/2004 Cooper ....................... TOO,299
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`WO
`
`WO 98.44405
`
`10, 1998
`
`OTHER PUBLICATIONS
`PCT International Search Report and Written Opinion of the Inter
`national Search Authority, Application No.: PCT/US2005/026941
`mailed Jul. 29, 2005. pp. 11.
`(Continued)
`Primary Examiner Suresh K Suryawanshi
`(74) Attorney, Agent, or Firm—Derek J. Reynolds
`
`ABSTRACT
`(57)
`An integrated circuit device, such as a processor initiates a
`transition to a first power management state. The device then
`receives a request to exit the first power management state
`and, in response exits the first power management state at
`the highest of a reference operating Voltage. Such as a
`minimum operating Voltage, and a current voltage. For one
`aspect, an analog to digital converter may be used to
`determine the current voltage level. Further, for one aspect
`the first power management state may be a deeper sleep (C4)
`state, and the processor may quickly exit to a C2 state in
`response to a bus event Such as a bus Snoop.
`
`29 Claims, 8 Drawing Sheets
`
`BESIN
`
`INTATEPOWERMSTTRANSTCN
`408
`
`NTATEWOLAGE TRANSiTIONTO
`OWERMGMTSTATE WOTAG
`41
`V
`MONTORWOLTAGERING
`RANSION
`Ais
`
`NATETRANSiTION FROMPER
`MANAGEMENTSTATE TONEXT
`STATE
`420
`
`ETERMNECURRENTWOLTAG
`425
`
`SW3CR =TO
`REFicci
`430
`M
`
`Y
`
`TRANSiTIONTor.
`WCCTOEXT
`
`XITSUBSTANTIALLY ATCURRENT
`WOLFAE
`
`440
`
`Qualcomm, Ex. 1004, Page 1
`
`

`

`US 7,363.523 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`6.954,864 B2 10/2005 Schelling .................... T13/310
`6,988,214 B1* 1/2006 Verdun ....
`713,320
`7,010,438 B2 * 3/2006 Hancock et al.
`... 702/60
`7,103,786 B2 * 9/2006 Chen et al. .......
`... 713,320
`2002fOO2.6597 A1
`2/2002 Dai et al. ...
`... 713,322
`2003/OOO97O2 A1
`1/2003 Park ........................... T13,300
`
`
`
`2004, OO19815 A1
`
`1/2004 Vyssotski et al. ........... T13,322
`
`OTHER PUBLICATIONS
`PCT International Preliminary Report on Patentability, Application
`No.: PCT/US/2005/026941 mailed Mar. 8, 2007. pp. 7.
`
`* cited by examiner
`
`Qualcomm, Ex. 1004, Page 2
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 1 of 8
`
`US 7,363.523 B2
`
`
`
`STPCLK
`
`BREAKEVENT
`
`DPSLP#
`
`
`
`TIMEOUT
`
`DPRSTPh.
`
`BUS EVENT
`
`FIGURE 1
`
`Qualcomm, Ex. 1004, Page 3
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 2 of 8
`
`US 7,363.523 B2
`
`
`
`
`
`
`
`
`
`
`
`NITIATE TRANSTION TOA
`FIRST PWR MGMT STAT
`
`RECEIVE REQUEST TOEXIT
`FIRST PWR MGMT STATE
`110
`
`EXITATHIGHER OF REF.
`OPERATING VOLTAGE AND
`CURRENT VOLTAGE is
`
`
`
`
`
`FIGURE 2
`
`Qualcomm, Ex. 1004, Page 4
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 3 of 8
`
`US 7,363.523 B2
`
`200
`
`EXEC. UNIT 210
`PWRMGMT LOGIC234
`
`
`
`VID TABLE
`277
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`DEEPER SLEEP ENTRY)
`EXIT LOGIC 275 ADC
`
`VIDCOD
`
`s CPU CORE VCC
`
`
`
`STPCLKE
`CPUSLP
`DPSLP#
`DPRSTPh.
`
`CTRL
`LOGIC 242
`
`STPCPU
`STOP CPU
`
`I/O CONTROLHUB225
`232
`
`OPERATING SYSTEM 245
`
`ACPI 250
`
`MASS STORAGE 230
`
`FIGURE 3
`
`BIOS
`278
`FWH 279
`
`Qualcomm, Ex. 1004, Page 5
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 4 of 8
`
`US 7,363.523 B2
`
`BEGIN
`
`INITIATE POWERMGMT TRANSTION
`
`405
`
`INITIATE VOLTAGE TRANSiTION TO
`POWER MGMT STATE VOLTAGE
`
`MONITORVOLTAGE DURING
`TRANSiTION
`
`415
`
`INITIATETRANSITION FROM POWER
`MANAGEMENT STATE TONEXT
`STATE
`420
`
`DETERMINE CURRENT VOLTAGE
`425
`
`
`
`SVCC CORE TO
`REF Voc?
`430
`
`TRANSiTION TO REF.
`VCCTOEXIT
`
`435
`
`EXIT SUBSTANTIALLY AT CURRENT
`VOLTAGE
`
`
`
`440
`
`FIGURE 4
`
`
`
`
`
`
`
`
`
`
`
`
`
`Qualcomm, Ex. 1004, Page 6
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet S of 8
`
`US 7,363.523 B2
`
`ADC
`500
`
`
`
`
`
`VCOcore
`
`VIDEN:O
`
`AD LATCH
`REGISTER CONVERSION
`TABLE
`LOGIC 505
`CONVERT (LEVEL)
`
`
`
`FIGURE 5
`
`Qualcomm, Ex. 1004, Page 7
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 6 of 8
`
`US 7,363.523 B2
`
`VID (NO)
`
`X
`
`STPCLK —
`crustP -
`
`X
`
`XX
`
`—
`- -
`
`DPSLP
`
`DPRSTP
`
`CORE VC
`
`- TRANSiTION TONEXT FREQ)
`VID PAIR UPON EXIT TO CO
`
`EXIT C4
`
`N PROC, GC4
`Voltage Set Point
`
`EXIT TO REF. VIDIFREQ
`PAR
`
`FIGURE 6
`
`Qualcomm, Ex. 1004, Page 8
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 7 of 8
`
`US 7,363.523 B2
`
`VIDINO)
`
`X
`
`XXXX
`
`CPUSLP
`
`DPSLP — —
`
`DPRSTP
`
`CORE VC
`
`EXIT C4
`
`TRANSiTIONSTONEXT FREQ,
`u-VD PAIR UPON EXIT TO CO
`
`
`
`EXIT TO CURRENTVD
`
`TRANSiTION TO REF VOLT
`
`
`
`C4 VOLTAGE -----------------------------------
`
`FIGURE 7
`
`Qualcomm, Ex. 1004, Page 9
`
`

`

`U.S. Patent
`
`Apr. 22, 2008
`
`Sheet 8 of 8
`
`US 7,363.523 B2
`
`Cmd VID
`
`Target-VID-Mux
`
`LFM
`
`MinGVVD
`
`Core-VicCAD
`
`GE)
`
`Cmpr
`&
`Max
`
`HIFT
`LEFT2 ADC Offset
`
`?
`
`Target-VID
`
`Y
`
`ad
`C4E Exit VID-Ct
`
`Tardet-VID-MUX
`
`CMpr
`&
`C
`ntr
`
`Up/Dn Countet:
`C4WD V. Current-VID
`
`CAE VID-Ct
`
`VID-Out-Mux
`
`WD-Out
`
`FIGURE 8
`
`Qualcomm, Ex. 1004, Page 10
`
`

`

`1.
`METHOD AND APPARATUS FOR
`CONTROLLING POWER MANAGEMENT
`STATE TRANSTIONS
`
`BACKGROUND
`
`5
`
`US 7,363.523 B2
`
`2
`interrupts may be lost due to this latency, a processor may
`be prevented from entering the C4 state altogether. The
`result may be an increase in the processor average power
`dissipation and a reduction in battery life versus systems that
`are able to enter C4.
`
`An embodiment of the present invention relates to the
`field of electronic systems and, more particularly, to a
`method and apparatus for controlling power management
`state transitions, and, in particular, transitions into and out of 10
`a deeper sleep state, for example.
`Power consumption continues to be an important issue for
`many current computing system including personal comput
`ers, wireless handsets, personal digital assistants, etc.
`In today's mobile computing environment, for example, 15
`to address power dissipation concerns, certain components
`may be placed into lower power states based on reduced
`activity or demand. For one approach, an operating system
`may support a built-in power management Software inter
`face such as Advanced Configuration and Power Interface 20
`(ACPI). ACPI describes a power management policy includ
`ing various “C states' that may be supported by processors
`and/or chipsets. For this policy, C0 is defined as the Run
`Time state in which the processor operates at high Voltage
`and high frequency. C1 is defined as the Auto HALT state in 25
`which the core clock is stopped internally. C2 is defined as
`the Stop Clock state in which the core clock is stopped
`externally. C3 is defined as the Deep Sleep state in which all
`processor clocks are shut down, and C4 is defined as the
`Deeper Sleep state in which all processor clocks are stopped 30
`and the processor Voltage is reduced to a lower data retention
`point. Of the various C states, C4 or Deeper Sleep, is the
`lowest power state.
`In operation, to enter the Deeper Sleep state, ACPI may
`detect a time slot in which there are no new or pending 35
`interrupts to the mobile processor. The ACPI policy then
`uses input/output (I/O) controller or other chipset features to
`place the mobile processor into the Deeper Sleep state.
`Once the processor is placed into this C4 state, a break
`event or interrupt from the operating system or another 40
`source may be sent to the chipset, and the chipset will then
`allow the processor to exit the Deeper Sleep state. The
`ability to transition between various power management
`states, including the Deeper Sleep state, may enable power
`dissipation to be reduced and battery life to be increased. 45
`Currently, entry into Deeper Sleep is done by referencing
`an external Voltage reference in the processor Voltage regu
`lator circuit and regulating to this reference Voltage when
`ever a platform “Deeper Sleep' signal such as a DPRSLPVR
`signal or other similar signal is asserted by the I/O controller 50
`or other integrated circuit. The Voltage regulator then tran
`sitions from a first voltage to a second lower Voltage
`associated with the Deeper Sleep state. Upon exiting the
`Deeper Sleep state, a voltage transition in the other direction
`takes place with a similar specified time window. Using 55
`current approaches, Deeper Sleep entry and exit latency
`times may be relatively large and may lead to system
`performance degradation and/or reduce potential power sav
`ings.
`In some cases, the Deeper Sleep entry/exit latencies may 60
`further prevent some systems from ever entering the Deeper
`Sleep state. For example, systems that include an active
`Universal Serial Bus 1 (USB1) and/or AC97 (Audio
`Codec 97) device may have difficulty entering the C4 power
`state because the operating system may not tolerate the long 65
`latency associated with transitioning out of C4 and back to
`C0 to handle a USB1 interrupt. Where there is a concern that
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention is illustrated by way of example
`and not limitation in the figures of the accompanying
`drawings in which like references indicate similar elements,
`and in which:
`FIG. 1 is a state diagram showing power management
`state transitions associated with one embodiment.
`FIG. 2 is a high-level flow diagram of a power manage
`ment state transition approach of one embodiment.
`FIG. 3 is a block diagram of an exemplary computing
`system in which the power management state transition
`control approach of one embodiment may be advanta
`geously implemented.
`FIG. 4 is a flow diagram showing a power management
`state transition control approach of one embodiment.
`FIG. 5 is a diagram of an exemplary analog-to-digital
`converter that may be advantageously used in the computing
`system of FIG. 3.
`FIG. 6 is a timing diagram illustrating relative signal
`transitions associated with an aspect of the power manage
`ment state transition control approach of one embodiment.
`FIG. 7 is a timing diagram illustrating relative signal
`transitions associated with another aspect of the power
`management state transition control approach of one
`embodiment.
`FIG. 8 is a block diagram of exemplary Deeper Sleep
`entry/exit logic that may be advantageously used in the
`system of FIG. 3, for example.
`
`DETAILED DESCRIPTION
`
`A method and apparatus for controlling power manage
`ment state transitions is described. In the following descrip
`tion, particular components, circuits, state diagrams, soft
`ware modules, systems, timings, etc. are described for
`purposes of illustration. It will be appreciated, however, that
`other embodiments are applicable to other types of compo
`nents, circuits, state diagrams, Software modules, systems,
`and/or timings, for example.
`References to “one embodiment,” “an embodiment,”
`“example embodiment,” “various embodiments, etc., indi
`cate that the embodiment(s) of the invention so described
`may include a particular feature, structure, or characteristic,
`but not every embodiment necessarily includes the particular
`feature, structure, or characteristic. Further, repeated use of
`the phrase “in one embodiment” does not necessarily refer
`to the same embodiment, although it may.
`Referring to FIG. 2, for one embodiment, an integrated
`circuit device Such as a processor, for example, initiates a
`transition to a first power management state at block 105.
`The first power management state may be, for example, a
`Deeper Sleep state. Subsequently, in response to receiving a
`request to exit the first power management state at block
`110, the device exits the first power management state at the
`higher of a reference operating Voltage and a current Voltage
`at block 115. For some embodiments, the reference operat
`ing voltage may be a minimum active state operating
`Voltage, for example.
`Further details of this and other embodiments are pro
`vided in the description that follows.
`
`Qualcomm, Ex. 1004, Page 11
`
`

`

`US 7,363.523 B2
`
`10
`
`15
`
`25
`
`3
`Embodiments of the invention may be implemented in
`one or a combination of hardware, firmware, and software.
`Embodiments of the invention may also be implemented in
`whole or in part as instructions stored on a machine-readable
`medium, which may be read and executed by at least one
`5
`processor to perform the operations described herein. A
`machine-readable medium may include any mechanism for
`storing or transmitting information in a form readable by a
`machine (e.g., a computer). For example, a machine-read
`able medium may include read only memory (ROM); ran
`dom access memory (RAM); magnetic disk storage media;
`optical storage media; flash memory devices; electrical,
`optical, acoustical or other form of propagated signals (e.g.,
`carrier waves, infrared signals, digital signals, etc.), and
`others.
`FIG. 3 is a block diagram of an exemplary system 200 that
`may advantageously implement the power management
`state transition approach of one or more embodiments. The
`system 200 is a notebook or laptop computer system, but
`may be a different type of electronic system such as a
`personal digital assistant, wireless telephone/handset or a
`desktop or enterprise computing system, for example, for
`other embodiments. Other types of electronic systems are
`within the scope of various embodiments.
`The system 200 includes a processor 205, a platform-level
`clock generator 211, a Voltage regulator 212 coupled to the
`processor 205, a memory control hub 215 coupled to the
`processor 205 over a bus 217, a memory 220 which may
`comprise one or more of random access memory (RAM),
`flash memory and/or another type of memory, an input/
`output (I/O) control hub 225 coupled to the memory control
`hub 215 over a bus 227, and a mass storage device 230
`coupled to the I/O control hub 225 over a bus 232.
`For one embodiment, the processor 205 may be an Intel(R)
`architecture microprocessor Such as, for example, a follow
`on processor to the Intel Pentium(R) M processor including
`one or more processing cores and at least one execution unit
`210 to process instructions. For such embodiments, the
`processor 205 may include Intel SpeedStep(R) technology or
`another power management-related technology that pro
`vides for two or more Voltage/frequency operating points.
`An associated power management unit 234 may be included
`on the processor 205 to control transitions between two or
`more of the Voltage/frequency pairs.
`For other embodiments, the processor 205 may be a
`different type of processor Such as a digital signal processor,
`an embedded processor, or a microprocessor from a different
`SOUC.
`Where Intel SpeedStep(R) technology or another type of
`power management technology is included on the processor
`50
`205, the available voltage/frequency pairs associated with
`the technology include a minimum Voltage/frequency pair
`corresponding to a minimum active mode operating Voltage
`and a minimum operating frequency associated with the
`processor 205 for a fully functional operational mode. These
`may be referred to herein as the minimum operating Voltage
`and minimum operating frequency or minimum active mode
`operating Voltage and frequency, respectively. Similarly, a
`maximum operating Voltage and frequency may be defined.
`Other available voltage frequency pairs may be referred to
`as operating Voltage/frequency pairs or simply other Voltage?
`frequency or frequency/voltage pairs.
`Deeper Sleep entry/exit logic 275 may also be included on
`the processor, either within or outside of the power man
`agement unit 234, to control entry into and exit from the
`65
`Deeper Sleep state, also referred to herein as the C4 state.
`Portions of exemplary Deeper Sleep entry/exit logic that
`
`30
`
`4
`may be used to provide the Deeper Sleep entry/exit logic 275
`are described in more detail below in reference to FIG. 8.
`A voltage identification (VID) memory 277 that is acces
`sible by the Deeper Sleep entry/exit logic 275 may be
`included to store a Voltage identification code look-up table.
`The VID memory may be an on- or off-chip register or
`another type of memory, and the VID data may be loaded
`into the memory via Software, basic input/output system
`(BIOS) code 278 (which may be stored on a firmware hub
`279 or in another memory), an operating system, other
`firmware and/or may be hardcoded, for example. Alterna
`tively, a software look-up table including VID and related
`data may be otherwise accessible by the logic 275.
`An analog-to-digital converter (ADC) 280 may also be
`provided as part of the Deeper Sleep entry/exit logic 275 to
`monitor a Voltage Supply level and provide an associated
`digital output as described in more detail below. Exemplary
`ADC logic that may be used to provide the ADC 280 is
`discussed in more detail below in reference to FIG. 5.
`The Voltage regulator 212 provides a Supply Voltage to the
`processor 205 and may be in accordance with a version of
`the Intel Mobile Voltage Positioning (IMVP) specification
`such as the IMVP-6 specification, for example. For such
`embodiments, the Voltage regulator 212 is coupled to
`receive VID signals from the processor 205 over a bus 235
`and, responsive to the VID signals, provide an associated
`supply voltage to the processor 205 over a signal line 240.
`The voltage regulator 212 may include Deeper Sleep logic
`270 that is responsive to one or more signals to provide a
`Deeper Sleep voltage to the processor 205. For other
`embodiments, a different type of Voltage regulator may be
`used, including a voltage regulator in accordance with a
`different specification. Further, for some embodiments, the
`Voltage regulator may be integrated with another component
`of the system 200 including the processor 205.
`The memory control hub 215 may include both graphics
`and memory control capabilities and may alternatively be
`referred to herein as a graphics and memory control hub
`(G/MCH) or a North bridge. The graphics and memory
`control hub 215 and the I/O control hub 225 (which also may
`be referred to as a South bridge) may be collectively referred
`to as the chipset. For other embodiments, chipset features
`may be partitioned in a different manner and/or may be
`implemented using a different number of integrated circuit
`chips. For example, for some embodiments, graphics and
`memory control capabilities may be provided using separate
`integrated circuit devices.
`The I/O control hub 225 of one embodiment includes
`power management state control logic 242, alternatively
`referred to herein as C-state control logic. The power
`management state control logic 242 may control aspects of
`the transitions between some power management and/or
`normal operational states associated with the processor 205,
`either autonomously or in response to operating system or
`other software or hardware events. For example, for Intel(R)
`architecture processors for which at least active mode and
`power management states referred to as C0, C1, C2 and C4
`are Supported, the power management state control logic
`242 may at least partially control transitions between at least
`a Subset of these states using one or more of a stop clock
`(STPCLKii), processor sleep (CPUSLP#), deep sleep
`(DPSLPH), deeper stop (DPRSTPH), and/or stop processor
`(STPCPU#) signals as described in more detail below.
`For other types of architectures and/or for processors that
`Support different power management and/or normal opera
`tional states, the power management state control logic 242
`may control transitions between two or more different power
`
`35
`
`40
`
`45
`
`55
`
`60
`
`Qualcomm, Ex. 1004, Page 12
`
`

`

`US 7,363.523 B2
`
`5
`
`10
`
`30
`
`35
`
`40
`
`25
`
`5
`management and/or normal operational states using one or
`more signals that may be similar to or different from the
`signals shown in FIG. 3.
`The mass storage device 230 may include one or more
`compact disc read-only memory (CD-ROM) drive(s) and
`associated disc(s), one or more hard drive(s) and associated
`disk(s) and/or one or more mass storage devices accessible
`by the computing system 200 over a network. Other types of
`mass storage devices Such as, for example, optical drives
`and associated media, are within the Scope of various
`embodiments.
`For one embodiment, the mass storage device 230 stores
`an operating system 245 that includes code 250 to support a
`current and/or a follow-on version of the Advanced Con
`figuration and Power Interface (ACPI) specification (cur
`15
`rently rev 2.0c). ACPI may be used to control some aspects
`of power management as described in more detail below.
`The operating system 245 may be a WindowsTM or another
`type of operating system available from Microsoft Corpo
`ration of Redmond, Wash. Alternatively, a different type of
`operating system Such as, for example, a Linux operating
`system, and/or a different type of operating system-based
`power management may be used for other embodiments.
`Further, the power management functions and capabilities
`described herein as being associated with ACPI may be
`provided by different software or hardware.
`Where the system 200 is a mobile or portable system, a
`battery or battery connector 255 may be included to provide
`power to operate the system 200 either exclusively or in the
`absence of another type of power source. Additionally, for
`Some embodiments, an antenna 260 may be included and
`coupled to the system 200 via, for example, a wireless local
`area network (WLAN) device 261 to provide for wireless
`connectivity for the system 200.
`It will be appreciated that the system 200 and/or other
`systems of various embodiments may include other compo
`nents or elements not shown in FIG. 3 and/or not all of the
`elements shown in FIG.3 may be present in systems of all
`embodiments.
`The power management state transition approach of some
`embodiments is now described in reference to FIGS. 1 and
`3-8.
`First, FIG. 1 is a state diagram illustrating the transitions
`between various C-states in which the processor 205 of FIG.
`3 may operate for one embodiment. The normal operational
`state or active mode for the processor 205 is the C0 state 301
`in which the processor actively processes instructions. In the
`C0 state, the processor is in a high-frequency mode (HFM)
`in which the Voltage/frequency setting may be provided by
`the maximum Voltage/frequency pair.
`In order to conserve power and/or reduce thermal load, for
`example, the processor 205 may be transitioned to a lower
`power state whenever possible. For example, from the C0
`state, in response to firmware, such as microcode, or soft
`ware, Such as the operating system 245, executing a HALT
`55
`or MWAIT instruction (not shown), the processor 205 may
`transition to the C1 or Auto-HALT state 303. In the C1 state,
`portions of the processor 205 circuitry may be powered
`down and local clocks may be gated.
`The processor may transition into the C2 state 305, also
`referred to as the stop grant or SLEEP state, upon assertion
`of the STPCLK# or similar signal by the I/O controller 225,
`for example. The I/O controller 225 may assert the STP
`CLKH signal in response to the operating system 245
`determining that a lower power mode may be or should be
`entered and indicating this via ACPI software 250. In
`particular, one or more ACPI registers (not shown) may be
`
`45
`
`50
`
`60
`
`65
`
`6
`included in the I/O controller 225 and the ACPI Software 250
`may write to these registers to control at least Some transi
`tions between states. During operation in the C2 state,
`portions of the processor 205 circuitry may be powered
`down and internal and external core clocks may be gated.
`For Some embodiments, the processor may transition
`directly from the C0 state 301 into the C2 state 305 as
`shown.
`Similarly, the processor 205 may transition into the C3
`state 307, also referred to as the Deep Sleep state, in
`response to the I/O controller 225 or other chipset feature
`asserting a CPUSLPH signal and then a DPSLPH signal or
`other similar signals. In the Deep Sleep state, in addition to
`powering down internal processor circuitry, all phase-lock
`loops (PLLs) in the processor 205 may be disabled. Further,
`for some embodiments, a STOP CPU signal may be
`asserted by the input/output controller 225 and received by
`the clock generator 211 to cause the clock generator to halt
`the clock signal CLK to the CPU 205.
`In the system 200 of FIG. 3, a transition to the C4 or
`Deeper Sleep state 309 may be undertaken in response to
`ACPI software 250 detecting that there are no pending
`processor interrupts, for example. ACPI software may do
`this by causing the ICH 225 to assert one or more power
`management-related signals such as the exemplary Deeper
`Stop (DPRSTPH) signal. For some embodiments, a Deeper
`Sleep Voltage Regulator (DPRSLPVR) signal may be
`asserted concurrently to indicate to the Voltage regulator 212
`to enter a lower power state.
`The Deeper Stop (DPRSTP#) signal is provided directly
`from the chipset to the processor and causes central power
`management logic 234 on the processor to initiate a low
`frequency mode (LFM). For the low frequency mode, the
`processor may transition to the minimum or another low
`operating frequency, for example. Where the processor
`includes Intel(R) SpeedStep(R) or an analogous power man
`agement technology, the minimum operating frequency may
`be the lowest SpeedStep technology frequency (or corre
`sponding frequency for the analogous technology) as
`described above. Assertion of the DPRSTPH signal may
`further cause the internal VID target to be set to the
`minimum operating Voltage, or another operating Voltage
`associated with the C4 state and the LFM frequency as
`indicated in the VID table 277. The voltage transition upon
`entering the C4 state is described in more detail below.
`With continuing reference to FIG. 1, when the processor
`205 is in one of the power management states C1-C4, certain
`events may indicate a need to transition to a higher power
`state. In particular, when the processor 205 is in a C4 state
`309, if a bus event, such as a bus snoop is received, there
`may be a need to transition to a C2 state, for example.
`For one embodiment, the processor may effectively pop
`out of the C4 state 309 through a LFMC3 state 311 to a LFM
`C2 state 313 in a relatively short amount of time (e.g.
`approximately 35 us for one embodiment) to enable the
`Snoop to occur. By transitioning from C4 to C2 while
`remaining in LFM, it may be possible to respond to bus
`events more quickly. In this manner, the processor 205 may
`be capable of entering the C4 state between USB, AC97
`and/or other device memory access frames, for example.
`Where this capability is provided, the C4 state may alter
`nately be referred to as a C4E state.
`When the Snoop is finished, following a predetermined
`timeout period, the chipset may then cause the processor 205
`to transition back into the C4 state 309. For some embodi
`ments, while in the C2. LFM state 313, if a break event such
`as an interrupt is received prior to the timeout period, the
`
`Qualcomm, Ex. 1004, Page 13
`
`

`

`7
`processor may instead transition to the C0 state. The pro
`cessor may do so through an intermediate C0/C1 state 315
`in which the operating Voltage and frequency have not yet
`been restored to their previous values. Previous operating
`frequency/voltage settings may then be restored upon tran
`sitioning back to the C0 state 301 as shown. The transition
`to the C0 state 301 and back to a previous operating
`Voltage/frequency pair may occur under the control of power
`management logic 234 through intermediate Voltage/fre
`quency pairs. Where the processor 205 incorporates Speed
`Step technology, for example, the processor may undergo
`SpeedStep transitions to arrive at the previous operating
`Voltage/frequency pair.
`By providing an approach for quickly transitioning from
`the very low power C4 state to the C2 state according to
`Some embodiments, it may be possible for systems, such as
`the system 200 to enter the C4 state even with active USB,
`AC97 or other I/O devices that require low latencies.
`Further details of the low latency exit from the C4 state are
`now described in reference to FIGS. 4-8.
`FIG. 4 is a flow diagram showing the power management
`state transition control approach of one embodiment. While
`FIGS. 3, 5 and 8 are referred to in order to show specific
`exemplary hardware that may be used to practice the method
`of FIG. 4, it will be appreciated that the method of FIG. 4
`may be practiced using various other Software and/or hard
`ware modules.
`Referring to FIG. 4, for one embodiment, in response to
`detecting a predetermined event or condition, a power
`management state transition to the Deeper Sleep or C4 state,
`for example, may be initiated at block 405.
`At block 410, a voltage transition from a current voltage
`level to a lower voltage level associated with the C4 state is
`then initiated.
`For the system 200 of FIG. 2, for example, this transition
`may be initiated by Deeper Sleep Entry/Exit Logic 275
`responsive to the deeper stop (DPRSTP#) signal being
`asserted. The Deeper Sleep Entry/Exit logic 275 may
`include logic to determine the VID to be provided to the
`voltage regulator 212 over the bus 235 as described in more
`detail below in reference to FIG. 7. The VID may be a
`multi-bit value (e.g. 7 bits for one embodiment) that corre
`sponds to a particular voltage to be driven by the Voltage
`regulator 212.
`For one embodiment, a specific Voltage may be associated
`with the power management state to which the processor is
`transitioning. For example, for the Deeper Sleep or C4 state,
`there may be a C4 voltage and a corresponding C4 VID. The
`logic 275 causes the C4 VID to be driven onto the bus 235
`and, in response, the Voltage regulator 212 begins transi
`tioning from the current Supply Voltage provided to the
`processor over the signal line 240 to the lower C4 voltage.
`Processor leakage then causes the Voltage to transition down
`towards the C4 voltage setting.
`Referring back to FIG. 4, at block 415, for some embodi
`ments, the Voltage is monitored as it transitions from the
`previous Voltage setting to the target Voltage setting.
`For the system 200, the analog to digital converter (ADC)
`280 may be used to monitor the voltage transition either on
`the signal line 240 or at a point internal to the processor. The
`ADC 280 may be integrated on the processor 205 or may be
`provided as part of a separate integrated circuit. An exem
`plary ADC 500 that may be used to provide the ADC 280 of
`FIG. 3 is described in reference to FIG. 5, which shows a
`diagram of an ADC of one embodiment.
`For one embodiment, the ADC 500 includes a 4-bit
`Analog to Digital (A/D) core 501 and operates on a backup
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`US 7,363.523 B2
`
`5
`
`10
`
`15
`
`8
`ring oscillator of the host processor. The ADC 500 may be
`enabled once the bus clock is stopped (in response to the
`Deep Sleep signal), for example, to sample the Vcc level on
`an output signal line Such as the signal line 240, or at a point
`internal to the host chip.
`The A/D range (i.