Case 3:17-cv-01375-DMS-MDD Document 312 Filed 08/22/18 PageID.11073 Page 1 of 17
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`Juanita R. Brooks, SBN 75934, brooks@fr.com
`Seth M. Sproul, SBN 217711, sproul@fr.com
`Frank Albert, SBN 247741, albert@fr.com
`Joanna M. Fuller, SBN 266406, jfuller@fr.com
`Robert M. Yeh, SBN 286018, ryeh@fr.com
`Fish & Richardson P.C.
`12390 El Camino Real
`San Diego, CA 92130
`Phone: 858-678-5070 / Fax: 858-678-5099
`
`Ruffin B. Cordell, DC Bar No. 445801, pro hac vice, cordell@fr.com
`Lauren A. Degnan, DC Bar No. 452421, pro hac vice, degnan@fr.com
`Fish & Richardson P.C.
`1000 Maine Avenue, S.W. Suite 1000
`Washington, D.C. 20024
`Phone: 202-783-5070 / Fax: 202-783-2331
`
`Mark D. Selwyn, SBN 244180, mark.selwyn@wilmerhale.com
`Wilmer Cutler Pickering Hale and Dorr LLP
`950 Page Mill Road
`Palo Alto, CA 94304
`Phone: 650-858-6000 / Fax: 650-858-6100
`Attorneys for Defendant/Counterclaim-Plaintiff Apple Inc.
`
`[Additional counsel identified on signature page.]
`UNITED STATES DISTRICT COURT
`SOUTHERN DISTRICT OF CALIFORNIA
`Case No. 3:17-CV-1375-DMS-MDD
`QUALCOMM INCORPORATED,
`
`
`
`v.
`
`APPLE INC.,
`
`Plaintiff,
`
`Defendant.
`
`AND RELATED COUNTERCLAIMS.
`
`DEFENDANT AND
`COUNTERCLAIM- PLAINTIFF APPLE
`INC.’S RESPONSIVE CLAIM
`CONSTRUCTION BRIEF
`
`September 5, 2018
`Date:
`9:00 a.m.
`Time:
`Courtroom 13A
`Place:
`Judge: Hon. Dana M. Sabraw
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`Case No. 3:17-CV-1375-DMS-MDD
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`Qualcomm, Ex. 1009, Page 1
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`TABLE OF CONTENTS
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`B.
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`I.
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`II.
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`Page
`U.S. PATENT NOS. 7,355,905; 7,760,559; AND 8,098,534 ............................... 1
`A.
`“integrated circuit” (’905, cl. 1; ’559, cls. 1-3; ’534, cls. 1, 3,
`4) ......................................................................................................................... 1
`“received on a first / second input to the integrated
`circuit” (’905, cl. 1); “receiving power from at least one
`first / second input to the integrated circuit” (’559, cl. 1) ......................... 2
`“during use” (’905, cl. 1; ’559, cls. 1, 2; ’534, cl. 1) ...................................... 2
`C.
`U.S. PATENT NOS. 7,383,453 AND 8,433,940 (the “Youngs
`Patents”) ........................................................................................................................ 3
`A.
`“core” and “area” (’453, cls. 1, 2, 4) .............................................................. 3
`“sufficient to maintain the state information of the
`B.
`instruction-processing circuitry” (’453, cls. 1, 2, 4) ..................................... 4
`“power area” (’940, claims 9, 11) ................................................................... 4
`C.
`“real-time clock” (’940 patent, cls. 9, 11) ...................................................... 5
`D.
`III. U.S. PATENT NOS. 8,271,812; 8,443,216; AND 8,656,196 ............................... 6
`A.
`“performance domain” (’812, cl. 8; ’216, cl. 1; ’196, cls. 1-
`3) ......................................................................................................................... 6
`“power management unit” (’812, cl. 8; ’216, cls. 1-2; ’196,
`cl. 1) .................................................................................................................... 7
`“establish a . . . performance state” (’812, cl. 8; ’216, cl. 1;
`’196, cl. 1) ........................................................................................................... 9
`“a prior performance state at which the processor was
`operating prior to entering the sleep state” (’812, cl. 8) .......................... 10
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`B.
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`C.
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`D.
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`Case No. 3:17-CV-01375-DMS-MDD
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`Qualcomm, Ex. 1009, Page 2
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`TABLE OF AUTHORITIES
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` Page(s)
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`Cases
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`3M Innovative Props. Co. v. Tredegar Corp.,
`725 F.3d 1315 (Fed. Cir. 2013) ............................................................................................ 5
`
`AIA Eng’g Ltd. v. Magotteaux Int’l S/A,
`657 F.3d 1264 (Fed. Cir. 2011) ............................................................................................ 4
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`BASF Corp. v. Johnson Matthey Inc.,
`875 F.3d 1360 (Fed. Cir. 2017) ............................................................................................ 4
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`Biogen Idec, Inc. v. GlaxoSmithKline LLC,
`713 F.3d 1090 (Fed. Cir. 2013) ........................................................................................ 1, 2
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`Enfish, LLC v. Microsoft Corp.,
`822 F.3d 1327 (Fed. Cir. 2016) .......................................................................................... 10
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`Free Motion Fitness, Inc. v. Cybex Int’l, Inc.,
`423 F.3d 1343 (Fed. Cir. 2005) ............................................................................................ 8
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`K-2 Corp. v. Salomon S.A.,
`191 F.3d 1356 (Fed. Cir. 1999) ............................................................................................ 9
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`Medversant Techs., L.L.C. v. Morrisey Assocs., Inc.,
`No. CV 09-05031 MMM, 2011 WL 9527718 (C.D. Cal. Aug. 5, 2011) ........................ 5
`
`Oatey Co. v. IPS Corp.,
`514 F.3d 1271 (Fed. Cir. 2008) ........................................................................................ 4, 7
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`Pitney Bowes, Inc. v. Hewlett-Packard Co.,
`182 F.3d 1298 (Fed. Cir. 1999) ............................................................................................ 8
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`Proprietect L.P. v. Johnson Controls, Inc.,
`No. 12-12953, 2013 WL 6795238 (E.D. Mich. Dec. 23, 2013) ...................................... 8
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`Qualcomm, Ex. 1009, Page 3
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`U.S. PATENT NOS. 7,355,905; 7,760,559; AND 8,098,534
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`“integrated circuit” (’905, cl. 1; ’559, cls. 1-3; ’534, cls. 1, 3, 4)
`The claims, written description, and prosecution history all support a construction
`of “one or more circuit elements that are integrated onto a single semiconductor
`substrate.” (Ex. 4 ¶¶ 23–35.) The claim language requires that the integrated circuit
`contain a logic and memory circuit, and the written description uses the term similarly,
`adding the detail that the logic and memory circuits are “integrated onto a single
`semiconductor substrate (or chip).” (Ex. 1 at 2:61–63; see also Ex. 4 ¶ 29.)
`Qualcomm’s arguments based on the claims and written description fail to support
`its construction.1 In particular, the assertion that Apple’s construction does not give
`notice of the integrated circuit’s boundaries ignores the rest of the claims’ language.
`Other claim terms flesh out the details of what falls within the “integrated circuit,”
`requiring that the integrated circuit contain a coupled logic and memory circuit,
`consistent with Apple’s construction. Qualcomm also points to usage in the written
`description as somehow contradicting Apple’s construction. However, the passage
`Qualcomm cites is largely identical to Apple’s construction. The passage differs slightly
`in that it requires the presence of “the logic circuits 12 and the memory circuits,” but this
`is consistent with Apple’s “one or more circuit elements” construction. Qualcomm goes
`on to claim that the “integrated circuit” construction should contain the word
`“connected,” but Apple’s construction mirrors the language in the specification. Further,
`this argument ignores the full language of Apple’s construction, which requires that the
`circuit elements on the substrate be integrated.
`Next, Qualcomm misapplies the prosecution history.2 Qualcomm argues that a
`single sentence describing how the “integrated circuit has only one power supply input
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`1 Qualcomm’s construction is inconsistent with the plain and ordinary meaning. And
`Qualcomm unsurprisingly fails to point to any of its dictionary definitions for
`support because they define “integrated circuit” as Apple does: as circuit elements
`integrated onto a substrate. (Ex. 4 ¶ 33.)
`2 Qualcomm points to no deviation from the plain and ordinary meaning where Apple
`“unequivocally and unambiguously disavow[ed]” that meaning. Biogen Idec, Inc. v.
`GlaxoSmithKline LLC, 713 F.3d 1090, 1095 (Fed. Cir. 2013).
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`Qualcomm, Ex. 1009, Page 4
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`to the integrated circuit (ExtVDD, see Fig. 3)” requires that the integrated circuit must
`include the entire chip. In so doing, Qualcomm ignores multiple paragraphs immediately
`preceding this sentence that place it into context. The preceding three paragraphs discuss
`in detail how the cited reference teaches a type of memory that does not receive a supply
`voltage at all. (Ex. 4 ¶ 32.) The Response then cites this lack of a supply voltage to show
`that the prior art reference does not contain two claim elements: (1) memory that is
`“continuously supplied by the second supply voltage” and (2) “a first supply voltage
`received on a first input to the integrated circuit; and ... a second supply voltage received
`on a second input to the integrated circuit.” (Id.; see also id. at Ex. I.) Accordingly,
`Qualcomm’s cited passage relates to the lack of a “supply voltage,” and does not limit
`the boundary of an integrated circuit itself. This is far from the “unequivocally and
`unambiguously” disavowing standard. Biogen Idec, Inc., 713 F.3d at 1095.
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`“received on a first / second input to the integrated circuit” (’905, cl.
`1); “receiving power from at least one first / second input to the
`integrated circuit” (’559, cl. 1)
`Apple’s construction is consistent with the claim language and comes directly from
`the written description. Qualcomm’s added term “generated external to” does not.
`Moreover, Qualcomm gives no explanation as to why its construction replaces the word
`“power” with “voltage”—terms that describe two distinct aspects of electricity.
`Instead of referring to the claims or written description, Qualcomm relies on the
`same sentence in the prosecution history discussed above, which describes how the prior
`art’s “integrated circuit has only one power supply input to the integrated circuit.” This
`argument is both insufficient and incorrect. As discussed above, in context, this
`discussion is demonstrating how the prior art has an integrated circuit with only one
`power input, because its memory receives no power at all. This statement does not
`disavow claim scope and does not require that the power be “generated external to the
`integrated circuit.” (Ex. 4 ¶¶ 41-43.)
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`“during use” (’905, cl. 1; ’559, cls. 1, 2; ’534, cl. 1)
`“During use” is a common term that the claims and written description use in its
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`Qualcomm, Ex. 1009, Page 5
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`plain and ordinary meaning. Based on this usage, a skilled artisan would consistently
`apply the term “during use” to indicate that the logic circuit and the memory circuit are
`operating. Apple advocates this plain and ordinary meaning, or the related meaning
`“while operating.” (Ex. 4 ¶¶ 45-48.)
`Qualcomm argues that the term “during use” is indefinite because it refers to
`“use” of different claim elements, such as logic circuit and the memory circuit, in the
`different places where it appears. But that argument erroneously interprets the phrase
`“during use” as if it were “during [its] use.” The actual claim language “during use” is
`used consistently throughout the claims as explained above. Moreover, Qualcomm’s
`strained effort to apply “during use” selectively to one or the other of logic or memory
`circuit is inconsistent with the claimed invention. Indeed, Qualcomm’s expert confirmed
`in his deposition that the memory circuit is not in use when the logic circuit is asleep or
`when the memory circuits are not in states capable of being read and written. (Ex. 18 at
`217:7-23.) Qualcomm also argues at length that the prosecution history does not define
`the term “during use.” This is irrelevant, since the meaning is clear from the usage in the
`claims and written description.
`(cid:44)(cid:44)(cid:17)(cid:3) U.S. PATENT NOS. 7,383,453 AND 8,433,940 (the “Youngs Patents”)
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`“core” and “area” (’453, cls. 1, 2, 4)
`Qualcomm tries to manufacture indefiniteness where none exists. Qualcomm
`ignores that the ’453 provides objective boundaries for these terms: a core is directly
`involved in instruction processing and an area is not. (Ex. 6 at cl. 1, 3:7–17, 3:34–36,
`4:13–15.) Thus, in any specific implementation, components directly related to
`instruction processing are located in the core(s), while components not directly related
`to instruction processing are in the area(s). (Id. at 3:7–17; Ex. 19 at 83:15–86:13, 94:22–
`95:5.) A skilled artisan understands with reasonable certainty whether a component is
`directly related to instruction processing or not. (Ex. 19 at 56:5–8, 74:20–75:16.)
`Depending on design choices, cache can be in the core or area. (Id. at 85:6–9.) A claim
`is not indefinite merely because the specification provides alternative designs. See, e.g.,
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`BASF Corp. v. Johnson Matthey Inc., 875 F.3d 1360, 1367 (Fed. Cir. 2017) (reversing district
`court’s indefiniteness ruling because “the claims and specification let the public know
`that any known SCR and AMOx catalysts can be used as long as they play their claimed
`role in the claimed architecture”). Because the “core” / “area” concept is clear to a
`skilled artisan, the Court should reject Qualcomm’s indefiniteness argument.
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`“sufficient to maintain the state information of the instruction-
`processing circuitry” (’453, cls. 1, 2, 4)
`The parties agree that this term should be construed consistently across the claims
`– across its use in both normal operation and low power modes. Qualcomm, however,
`ignores the normal operation mode. All the intrinsic evidence highlighted by Qualcomm
`relates to low power mode embodiments. (See Ex. 6 at 4:18–21 (“In one embodiment
`of the present invention, the voltage in core power 134 is reduced to the minimum value
`that will maintain state information within core power area 126.”).) Apple agrees that in
`certain embodiments of low power modes, the voltage is reduced such that instruction
`processing is stopped. In at least claim 1’s normal operation mode, however, the ’453
`is clear that instruction processing occurs. (Id. at cl. 1 (“core is active”), 4:13–15 (“The
`voltage applied to core power 134 remains sufficiently high during instruction processing
`so that core power area 126 remains fully active”).) And, in some low power modes, the
`processor is stopped by halting the clock “without reducing any voltages” from
`normal operation mode. (Id. at 4:61–64.) Because Qualcomm’s construction directly
`contradicts claim 1’s normal operation mode and excludes some embodiments of low
`power mode, the Court should reject it. See, e.g., AIA Eng’g Ltd. v. Magotteaux Int’l S/A,
`657 F.3d 1264, 1278 (Fed. Cir. 2011) (“[A] construction that renders the claimed
`invention inoperable should be viewed with extreme skepticism.”); Oatey Co. v. IPS Corp.,
`514 F.3d 1271, 1276 (Fed. Cir. 2008) (reversing construction excluding embodiment).
`(cid:38)(cid:17)(cid:3)
`“power area” (’940, claims 9, 11)
`Apple’s construction embraces the
`language of the specification while
`Qualcomm’s ignores it. Apple’s construction and the ’940 make clear, “[n]on-core power
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`Qualcomm, Ex. 1009, Page 7
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`area 124 receives non-core power 136 and core power area 126 receives core power
`134.” (Ex. 7 at 3:59–60.) In contrast, Qualcomm injects a new concept – “power supply”
`– appropriated from an unrelated patent. (Dkt. No. 295 at 15:13–16.) Rather than clarify
`the meaning of “power area,” Qualcomm’s “same power supply” requirement creates
`confusion because it is unclear to a skilled artisan whether “same power supply” refers
`to the ultimate power source or some portion of a power distribution system. (See Ex. 8
`¶ 51; Ex. 19 at 135:13–24, 215:16–216:2; Ex. 20 at 80:4-10, 82:15-22); see also Medversant
`Techs., L.L.C. v. Morrisey Assocs., Inc., No. CV 09-05031 MMM FFMX, 2011 WL 9527718,
`at *35 (C.D. Cal. Aug. 5, 2011) (rejecting proposed construction that “would inject
`ambiguity into the term”). Moreover, neither the term, nor the concept of “power
`supply” appears in the ’940. Qualcomm offers no cogent legal basis for importing into
`the construction of “power area” the “power supply” claim limitation of a different
`patent. The Court should therefore reject Qualcomm’s proposal.
`(cid:39)(cid:17)(cid:3)
`“real-time clock” (’940 patent, cls. 9, 11)
`The parties agree that a real-time clock provides time-of-day services. (Ex. 7 at
`3:36–37; Dkt. No. 295 at 15:19–23.) The parties also agree that a “real-time clock” may
`include firmware and software. (Dkt. No. 295 at 15:24-25; Ex. 20 at 55:10–12.)
`Nonetheless Qualcomm seeks to limit “real-time clock” to just a circuit. (Dkt. No. 295
`at 15:24–25.) Nowhere in the ’940 is a “real-time clock” so limited. Restricting “real-
`time clock” to one implementation narrows this term from its plain meaning. (Ex. 19 at
`220:25–221:1 (“[B]y saying it is a circuit, we kind of narrow down the potential realization
`of [real-time clock].”).) Qualcomm’s proposal must therefore be rejected. See 3M
`Innovative Props. Co. v. Tredegar Corp., 725 F.3d 1315, 1333 (Fed. Cir. 2013) (“[Courts] will
`not narrow a claim term beyond its plain and ordinary meaning unless there is support
`for the limitation in the words of the claim, the specification, or the prosecution
`history.”).
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`Qualcomm, Ex. 1009, Page 8
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`Case 3:17-cv-01375-DMS-MDD Document 312 Filed 08/22/18 PageID.11081 Page 9 of 17
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`(cid:44)(cid:44)(cid:44)(cid:17)(cid:3) U.S. PATENT NOS. 8,271,812; 8,443,216; AND 8,656,1963
`(cid:36)(cid:17)(cid:3)
`“performance domain” (’812, cl. 8; ’216, cl. 1; ’196, cls. 1-3)
`
`Qualcomm’s argument on this term is flawed in at least two ways. First,
`Qualcomm completely ignores the de Cesare Patents’ disclosures of independently
`controlled performance domain components. Second, Qualcomm misconstrues the
`plain language of the claims to support its incorrect conclusion restricting control of a
`performance domain to the PMU.
`Neither party disputes that components within a performance domain may be
`controlled as a unit. However, Qualcomm ignores that the de Cesare Patents
`unequivocally describe
`independent control of components within the same
`performance domain. (See, e.g., Ex. 12 at 5:25–28 (“[A]ny other performance
`characteristics that apply to more than one component in a performance domain and
`that may be independent[ly] controlled for such components may be represented by
`multiple instances in the performance state.”).) Further disclosed is that a processor may
`enter sleep state while other components in the same performance domain, such as
`an L2 cache, remain active. (Id. at 5:29–36.) A skilled artisan understood that
`independent control of components in a performance domain allows the L2 cache to
`“remain active to maintain cache coherence” during processor sleep. (See id. 5:36–43;
`Ex. 21 at 72:10–15 (“[T]hose independent components . . . have say a different clock
`frequency or different voltage.”).) In sum, unitary and independent control are not
`mutually exclusive according to the intrinsic and extrinsic evidence, (Ex. 21 at 74:22–
`75:5), thus the Court should reject Qualcomm’s attempt to exclude these embodiments.
`Second, Qualcomm injects a “controlled by the PMU” limitation that is otherwise
`absent from the claims. Claim 8 of the ’812 recites that “the power management unit is
`configured to transition at least a first performance domain of the plurality of
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`3 Qualcomm argues that claim 8 of the ’812 is “representative” of the de Cesare Patents
`“[f]or claim construction.” (Dkt. No. 295 at 18:6.) As each claim is unique, Apple
`disagrees that any claim is representative of any other claim.
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`Qualcomm, Ex. 1009, Page 9
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`Case 3:17-cv-01375-DMS-MDD Document 312 Filed 08/22/18 PageID.11082 Page 10 of 17
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`performance domains.” (Ex. 12 at cl. 8.) Qualcomm’s proposed construction seeks to
`rewrite the claims by embedding the PMU-control concept into the performance domain
`construction. Further, there is no requirement in the claims that the PMU control every
`transition, as discussed below with regard to the PMU. Qualcomm rewrites the claim to
`ascribe responsibilities of control to the PMU through the term “performance domain.”
`In so doing, Qualcomm contradicts the specification’s teaching that “performance
`domain[] transition may be hardware controlled by the PMU 28, or may be software
`controlled using the valid indications in the performance configuration registers.” (Id.
`at 8:57–60.) Qualcomm’s construction is thus improper for failing to include all disclosed
`embodiments that fairly fall within the scope of the claim. See Oatey Co., 514 F.3d at 1276
`(reversing construction that excludes embodiment).
`The Court should therefore adopt Apple’s proposed construction which captures
`the plain language of the de Cesare Patents and embraces the intrinsic record.
`(cid:37)(cid:17)(cid:3)
`“power management unit” (’812, cl. 8; ’216, cls. 1-2; ’196, cl. 1)
`The de Cesare Patents do not require Qualcomm’s “hardware-only”
`implementation of power management unit that precludes any use of software.4 First,
`Qualcomm ignores the specification’s express disclosures of software-managed state
`transitions. (See, e.g., Ex. 12 at Abstract, 8:38–39 (“[S]oftware may use processor
`instruction execution mechanisms to cause the processor to enter the sleep state.”).)
`That is, software that runs on the PMU itself causes the transition. Second, Qualcomm
`misunderstands the exchange between the examiner and the applicant. In response to
`the examiner’s non-final rejection on § 101 grounds of certain claims as implemented in
`software only, the applicant clarified that certain claim limitations recite hardware, but
`never limited a power management unit to a hardware-only implementation. (Ex. 22 at
`864 (rejecting “claims 17-20 as being non-statutory for being implemented only in
`software . . . Such an interpretation ignores the express recitation of hardware [including]
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`4 Qualcomm has the Ventana holding, and its applicability here, backwards; Qualcomm
`is improperly limiting the claims, not Apple. (See Dkt. No. 295 at 22:14–16.)
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`Qualcomm, Ex. 1009, Page 10
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`Case 3:17-cv-01375-DMS-MDD Document 312 Filed 08/22/18 PageID.11083 Page 11 of 17
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`‘a processor . . . [and] ‘a power management unit.’”).) And, because a processor
`indisputably includes hardware, the claims would have overcome the examiner’s rejection
`on that basis alone. Therefore, Apple never expressly disclaimed a PMU that is either
`partially or completely software-implemented PMU. Free Motion Fitness, Inc. v. Cybex Int’l,
`Inc., 423 F.3d 1343, 1353 (Fed. Cir. 2005) (absent “a clear and unmistakable disclaimer,”
`a patent may cover a feature “even when the undesirability of that feature formed the
`basis of an . . . argument overcoming rejection during prosecution”). Third, whether a
`hardware PMU implementation is faster than a software PMU implementation is
`immaterial when the claims do not require a particular configuration. See id.; Pitney Bowes,
`Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1309–11 (Fed. Cir. 1999) (cautioning against
`importing limitations into the claims that are not found in the claims themselves).
`Fourth, Qualcomm improperly mischaracterizes Dr. Mooney’s testimony regarding
`software implementations of the power management unit. (Dkt. No. 295 at 21:25–22:2.)
`Dr. Mooney explained that defining a software-only PMU to include hardware is
`“splitting hairs” because at some level software must run on hardware. (Ex. 21 at 62:7–
`19.) Further, a skilled artisan would not consider a software-implemented PMU to
`include hardware. (Id. at 61:13–20, 184:24–185:2 (“You could implement a power
`management unit in software. That would have to interface to the hardware through
`interface logic in order to affect the transitions being requested.”).) Finally, Qualcomm
`cites no support for its assertion that the PMU does not include the PMU driver—in
`fact, a skilled artisan would understand the PMU to include the driver. (See Ex. 15 ¶ 33.)
`Next, the PMU need not transition every performance domain to achieve a state
`transition. Qualcomm mistakenly equates “each” with “every.” See Proprietect L.P. v.
`Johnson Controls, Inc., No. 12-12953, 2013 WL 6795238, at *10 (E.D. Mich. Dec. 23, 2013)
`(rejecting construction of “each groove” as “every individual groove” where “‘each
`groove’ only refers to ‘each’ of the previously recited ‘plurality of grooves’”). That the
`PMU is capable of establishing a performance state in each of a plurality of performance
`domains does not require it to do so in every performance domain. In fact, claim 8
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`Qualcomm, Ex. 1009, Page 11
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`Case 3:17-cv-01375-DMS-MDD Document 312 Filed 08/22/18 PageID.11084 Page 12 of 17
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`merely requires that “the power management unit is configured to transition at least a
`first performance domain of the plurality of performance domains.” (Ex. 12 at cl. 8.)
`Requiring the PMU to transition any more than one performance domain would
`therefore be inconsistent with the claim language.
`Finally, “automatic transition” is yet another limitation contrived by Qualcomm
`without support. (See Dkt. No. 295 23:1–6.) The claims simply do not require automatic
`transitions, and the specification describes non-automatic transitions. (Ex. 12 at 10:63–
`11:3, 8:52–55.) See K-2 Corp. v. Salomon S.A., 191 F.3d 1356, 1364 (Fed. Cir. 1999)
`(“Courts do not rewrite claims; instead, we give effect to the terms chosen by the
`patentee.”) The Court should reject Qualcomm’s overly narrow proposal.
`(cid:38)(cid:17)(cid:3)
`“establish a . . . performance state” (’812, cl. 8; ’216, cl. 1; ’196, cl. 1)
`Qualcomm’s brief
`injects confusion
`into an otherwise simple concept:
`performance characteristics (e.g., voltage and/or clock frequency) must be set