(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2005/0064829 A1
`Kang et al.
`(43) Pub. Date:
`Mar. 24, 2005
`
`US 2005OO64829A1
`
`(54)
`
`(76)
`
`POWER COLLAPSE FOR AWIRELESS
`TERMINAL
`
`Inventors: Inyup Kang, San Diego, CA (US);
`Karthikeyan Ethirajan, San Diego,
`CA (US)
`
`Correspondence Address:
`Qualcomm Incorporated
`Patents Department
`5775 Morehouse Drive
`San Diego, CA 92.121-1714 (US)
`
`Appl. No.:
`
`10/786,585
`
`Filed:
`
`Feb. 24, 2004
`Related U.S. Application Data
`Provisional application No. 60/504,507, filed on Sep.
`19, 2003.
`
`(21)
`(22)
`
`(60)
`
`Publication Classification
`
`(51) Int. Cl." ....................................................... H04Q 7/20
`(52) U.S. Cl. .......................................................... 455/127.1
`(57)
`ABSTRACT
`An integrated circuit for a modem processor includes pro
`cessing units that are partitioned into “always-on' and
`“collapsible' power domains. An always-on power domain
`is powered on at all times. A collapsible power domain can
`be powered off if the processing units in the power domain
`are not needed. A power control unit within an always-on
`power domain powers down the collapsible power domains
`after going into sleep and powers up these domains after
`waking up from Sleep. Tasks for powering down the col
`lapsible power domains may include (1) Saving pertinent
`hardware registers for these power domains, (2) freezing
`output pins of the IC to minimally disturb external units, (3)
`clamping input pins of the collapsed power domains, (4)
`powering down a main oscillator and disabling the oscillator
`clock, and So on. Complementary tasks are performed for
`powering up the collapsed power domains.
`
`100
`-1
`
`s a r a was a swar as a war wives or or use
`
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`
`Modem Processor
`
`
`
`Controller
`
`Internal
`Memo
`ry
`
`
`
`
`
`
`
`
`
`
`
`
`
`Main
`Oscillator
`
`
`
`Sleep
`OScillator
`
`Non-Volatile
`Memory
`(e.g., Flash)
`
`Volatile
`Memory
`(e.g., SDRAM)
`
`Qualcomm, Ex. 1015, Page 1
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 1 of 6
`
`US 2005/0064829 A1
`
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`Qualcomm, Ex. 1015, Page 2
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 2 of 6
`
`US 2005/0064829 A1
`
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`Qualcomm, Ex. 1015, Page 3
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 3 of 6
`
`US 2005/0064829 A1
`
`20
`
`Collapsible
`Power Domains
`
`FIG. 2B
`
`
`
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`
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`POWer
`Connection
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`
`Always-On
`Power Domain
`
`Collapsible
`Power Domain
`
`Collapsible
`POWer Domain
`
`210e
`
`Qualcomm, Ex. 1015, Page 4
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 4 of 6
`
`US 2005/0064829 A1
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`Qualcomm, Ex. 1015, Page 5
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 5 of 6
`
`US 2005/0064829 A1
`
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`Qualcomm, Ex. 1015, Page 6
`
`

`

`Patent Application Publication Mar. 24, 2005 Sheet 6 of 6
`
`US 2005/0064829 A1
`
`SDRAM
`Program
`
`
`
`
`
`
`
`
`
`5
`
`Flash
`Program
`
`Boot Code
`
`
`
`BOOt
`SRAM
`
`134
`
`Modem Processor
`
`FIG. 7
`
`is
`is
`freeze io
`
`810
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`814
`
`VDD a
`
`Shifter
`
`Always-on
`POWer
`Domain
`
`V
`
`Collapsible
`POWer
`Domain
`
`-----------------------------------
`
`FIG, 8A
`
`VDD x
`
`820
`
`VDD a
`
`
`
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`Collapsible
`POWer
`DOmain
`
`FIG. 8B
`
`Qualcomm, Ex. 1015, Page 7
`
`

`

`US 2005/OO64829 A1
`
`Mar. 24, 2005
`
`POWER COLLAPSE FOR AWIRELESS
`TERMINAL
`
`RELATED APPLICATIONS
`0001. This application claims priority to U.S. Provisional
`Patent Application No. 60/504,507 filed Sep. 19, 2003.
`
`BACKGROUND
`
`0002 I. Field
`0003. The present invention relates generally to circuits,
`and more specifically to techniques for conserving power for
`a wireless terminal.
`II. Background
`0004)
`0005) A wireless terminal (e.g., a cellular phone) in a
`cellular communication System is only sporadically active
`and remains in an "idle' mode for Significant periods of time
`when no call is in progreSS. To ensure that the terminal can
`Still receive messages Sent to it by the System, the terminal
`periodically monitors a paging channel even while it is in the
`idle mode. These messages may alert the terminal to the
`presence of an incoming call, carry updated System param
`eters for the terminal, and So on.
`0006 The wireless terminal is typically portable and
`powered by an internal battery. To conserve power and
`extend Standby time between battery recharges, the System
`typically sends messages on the paging channel to the
`terminal at designated times. The paging channel may be
`divided into "slots', and the terminal may be assigned to
`Specific slots by the System. Thereafter, the terminal enters
`an “active' State prior to its assigned slot, monitors the
`paging channel for messages, and transitions to an “inac
`tive' State if additional communication is not required. In the
`time period between Successive active States, the terminal is
`asleep in the inactive State and deactivates as much circuitry
`as possible to conserve power. “Sleep” refers to the time
`during which the terminal is in the inactive State.
`0007 Conventionally, the terminal powers down analog
`circuit blocks (e.g., power amplifiers, oscillators, and So on)
`and disables clocks to digital circuit blocks while in the
`inactive State. A digital circuit that is fabricated in comple
`mentary metal oxide semiconductor (CMOS) consumes
`power via two mechanisms: (1) by dissipating dynamic
`current when the circuit is active and Switching and (2) by
`drawing leakage current when the circuit is inactive and not
`Switching. In contemporary CMOS fabrication technology,
`the dynamic current is many times greater than the leakage
`current. In this case, Significant power Saving may be
`achieved for CMOS digital circuits by simply disabling the
`clocks to these circuits to shut off the dynamic current.
`0008 However, leakage current is not negligible and will
`become a significant portion of the total power consumption
`as CMOS technology scales to smaller geometry. This is
`because leakage current increases at a very high rate with
`respect to the decrease in transistor size. The higher leakage
`current, coupled with long periods of inactivity, consumes
`power and reduces Standby time for portable devices that use
`battery power, which is highly undesirable.
`0009. There is therefore a need in the art for techniques
`to conserve power for a wireless terminal.
`
`SUMMARY
`0010 Techniques for performing “power collapse” for a
`wireless terminal are provided herein. Power collapse refers
`to the powering down of circuit blockS/processing units
`when not needed to reduce leakage current and conserve
`power. To implement power collapse, the circuit blockS/
`processing units within an integrated circuit (IC) used for the
`wireleSS terminal are partitioned into multiple power
`domains. Each power domain couples to a power Supply via
`a power connection. Each power domain is designated as
`either “always-on' or “collapsible”. An always-on power
`domain is powered on at all times (i.e., while the wireless
`terminal is powered on). A collapsible power domain can be
`powered off if the processing units in the power domain are
`not needed.
`0011 Power collapse is typically performed in conjunc
`tion with a sleep timeline that indicates when the wireleSS
`terminal can go to Sleep. The Sleep timeline may be different
`for different wireleSS communication Systems. A power
`control unit within the always-on power domain powers
`down the collapsible power domains after going into Sleep
`and powers up these domains just before waking up from
`Sleep. The collapsed power domains may also be powered
`up based on an external interrupt event.
`0012. A set of tasks is typically performed for powering
`down the collapsible power domains. For example, the
`powering down tasks may include Saving pertinent hardware
`registers of the collapsible power domains, freezing output
`pins of the IC to minimally disturb external units coupled to
`the IC, clamping input pins of the collapsed power domains,
`powering down a main oscillator and disabling a main clock
`from the oscillator, and So on. A complementary Set of tasks
`is typically performed for powering up the collapsed power
`domains. For example, the powering up tasks may include
`powering up the main oscillator and enabling the main
`clock, restoring Software, firmware, and hardware States,
`releasing input and output pins, and So on. These various
`tasks are described in further detail below.
`0013 Various aspects, embodiments, and features of the
`invention are described in further detail below.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0014. The features and nature of the present invention
`will become more apparent from the detailed description Set
`forth below when taken in conjunction with the drawings in
`which like reference characters identify correspondingly
`throughout and wherein:
`0.015 FIG. 1 shows a block diagram of the wireless
`terminal;
`0016 FIG. 2A shows the partitioning of the modem
`processor into multiple power domains,
`0017 FIG. 2B shows a layout of an integrated circuit for
`the modem processor,
`0018 FIG. 3 shows a configuration for connecting the
`power domains to power Supply bus(es);
`0019 FIG. 4 shows a timeline for processing a paging
`channel for a wireleSS communication System;
`0020 FIGS. 5A and 5B show a powering down
`Sequence and a powering up Sequence, respectively, for the
`collapsible power domains,
`
`Qualcomm, Ex. 1015, Page 8
`
`

`

`US 2005/OO64829 A1
`
`Mar. 24, 2005
`
`FIG. 6 shows timelines for three different systems;
`0021)
`0022 FIG. 7 illustrates a software boot process for the
`modem processor, and
`0023 FIGS. 8A and 8B show interface and output cir
`cuits between the power domains and/or modem processor
`pads.
`
`DETAILED DESCRIPTION
`0024. The word “exemplary” is used herein to mean
`“Serving as an example, instance, or illustration.” Any
`embodiment or design described herein as “exemplary' is
`not necessarily to be construed as preferred or advantageous
`over other embodiments or designs.
`0.025
`FIG. 1 shows a block diagram of a wireless ter
`minal 100, which may be a cellular phone, a handset, a
`wireleSS communication device, a personal digital assistant
`(PDA), and so on. Terminal 100 may monitor and/or com
`municate with one or more wireleSS communication Systems
`such as a Code Division Multiple Access (CDMA) system,
`a Global System for Mobile Communications (GSM) sys
`tem, a Bluetooth System, a multiple-input multiple-output
`(MIMO) system, an orthogonal frequency division multiple
`access (OFDMA) system, and so on. A CDMA system may
`implement one or more CDMA standards such as IS-2000
`and IS-95 (which are also known as “1x-EV DV”), IS-856
`(which is also known as “1x-EV DO”), Wideband-CDMA
`(W-CDMA), and so on. A CDMA system that implements
`W-CDMA is also known as a Universal Mobile Telecom
`munications System (UMTS) system. Terminal 100 is
`capable of providing bidirectional communication via a
`receive path and a transmit path.
`0026. For the receive path, signals transmitted by base
`Stations in one or more Systems are received by an antenna
`112, routed through a duplexer (D) 114, and provided to a
`receiver unit (RCVR) 116. Receiver unit 116 conditions
`(e.g., filters, amplifies, and frequency downconverts) the
`received Signal, digitizes the conditioned signal, and pro
`vides data samples to a modem processor 120 for further
`processing. For the transmit path, modem processor 120
`processes data to be transmitted by terminal 100 and pro
`vides “data chips” to a transmitter unit (TMTR) 118. Each
`data chip is a value to be transmitted in one chip period,
`which is 1/(1.2288x10) for some CDMA systems. Trans
`mitter unit 118 conditions (e.g., converts to analog, filters,
`amplifies, and frequency upconverts) the data chips and
`generates a modulated Signal, which is routed through
`duplexer 114 and transmitted from antenna 112.
`0.027 Modem processor 120 includes various processing
`units that Support monitoring and/or communication with
`one or more systems. Modem processor 120 further inter
`faces with other units within terminal 100. For the embodi
`ment shown in FIG. 1, modem processor 120 includes a
`modem core 130, a controller 132, an internal memory 134,
`phase locked loops (PLLs) 136, and a power control unit
`140, all of which couple to a bus 128. Modem core 130
`performs demodulation and decoding for the receive path
`and encoding and modulation for the transmit path. Con
`troller 132 controls the operation of various processing units
`within modem processor 120. Internal memory 134 stores
`data and program code used by the processing units within
`modem processor 120 and may include a cache, random
`
`access memories (RAMs), read only memories (ROMs), and
`So on. PLLS 136 control various oscillators within terminal
`100 such that these oscillators operate at the proper frequen
`cies. Power control unit 140 controls power to various
`processing units within modem processor 120, as described
`below.
`0028. For the embodiment shown in FIG. 1, modem
`processor 120 further couples to a main oscillator 152, a
`sleep oscillator 154, a volatile memory 156, and a non
`volatile memory 158, all of which support modem processor
`120. Main oscillator 152 provides a high-frequency main/
`system clock used by modem processor 120 for normal
`operation and may be implemented, for example, with a
`temperature-compensated crystal oscillator (TCXO). Sleep
`oscillator 154 provides a low-frequency sleep clock used by
`an always-on power domain within modem processor 120.
`Volatile memory 156 provides bulk storage for data and code
`used by modem processor 120 and may be implemented
`with, for example, a synchronous dynamic RAM (SDRAM)
`or some other type of memory. Non-volatile memory 158
`provides bulk non-volatile Storage and may be implemented
`with, for example, a NAND Flash, a NOR Flash, or some
`other type of non-volatile memory.
`0029. In general, modem processor 120 may include
`fewer, more and/or different processing units than those
`shown in FIG. 1. The specific processing units included in
`modem processor 120 are typically dependent on the design
`of modem processor 120 and the communication System(s)
`being Supported. Modem processor 120 may also couple to
`fewer, more and/or different external units than those shown
`in FIG. 1.
`0030 Modem processor 120 may be implemented in a
`single CMOS integrated circuit for various benefits such as
`Smaller size, lower cost, less power consumption, and So on.
`AS IC fabrication technology continually improves and
`migrates to Smaller geometry, the size of transistors contin
`ues to Shrink. A lower power Supply may be used for a
`Smaller geometry IC to reduce power consumption. The
`threshold voltage (which is the Voltage at which a transistor
`turns on) for Smaller-size transistors is often reduced (i.e.,
`lowered) to improve operating speed. However, the lower
`threshold Voltage and Smaller transistor geometry result in
`higher leakage current, which is the current passing through
`a transistor when it is not Switching. Leakage current is more
`problematic as CMOS technology scales down to 90 nm
`(nanometer) and Smaller.
`0031 Power consumption due to leakage current can be
`reduced by powering down as much digital circuitry as
`possible when not needed. Terminal 100 may only be active
`for a small portion of the time while it is idle. In this case,
`the power to many of the processing units can be powered
`down (i.e., “collapsed”) for a large portion of the time to
`reduce power consumption and extend Standby time.
`0032 Modem processor 120 is partitioned into multiple
`power domains. Each power domain includes processing
`units that are coupled to a power Supply via a power
`connection. Each power domain is designated as either
`always-on or collapsible. An always-on power domain is
`powered on at all times while terminal 100 is powered on.
`A collapsible power domain may be powered down if the
`processing units in the power domain are not needed. Each
`collapsible power domain may be powered on or off inde
`
`Qualcomm, Ex. 1015, Page 9
`
`

`

`US 2005/OO64829 A1
`
`Mar. 24, 2005
`
`pendently of the other collapsible power domains. AS used
`herein, "power up' and “power on' are Synonymous terms
`that are used interchangeably, and “power down' and
`"power off are also synonymous terms.
`0.033
`FIG. 2A shows the partitioning of the processing
`units within modem processor 120 into multiple power
`domains 210. In this example, the five processing units 130
`through 140 in modem processor 120 are placed in five
`different power domains 210a through 210e. In general,
`each power domain can include any number of processing
`units, and each processing unit can include any number of
`circuit blocks. Each power domain 210 couples to a power
`Supply buS 214 via a power connection 212. For the example
`shown in FIG. 2A, power domain 210a for power control
`unit 140 is the only always-on power domain, and all other
`power domains 210b through 210e are collapsible.
`0034). Each of processing units 130 through 140 within
`modem processor 120 may include various circuit blockS.
`For example, modem core 130 includes CDMA processing
`blockS 222, a clock generator 224, a modem digital Signal
`processor (DSP) 226, a modem processor 228, a sub-system
`processor 230, RAMs 232, and ROMs 234. Clock generator
`224 generates various clocks used by the processing units
`within modem processor 120. CDMA processing blocks 222
`perform (1) encoding, interleaving, and modulation for the
`transmit path and (2) demodulation, deinterleaving, and
`decoding for the receive path. For example, CDMA pro
`cessing blockS 222 may implement a rake receiver with
`multiple Searchers and finger processors for the receive path,
`as is known in the art. CDMA processing blockS 222 also
`perform other ancillary functions Such as maintaining a real
`time counter (RTC), which provides system time, for each
`system being monitored by terminal 100. Modem DSP 226
`performs modem (modulation/demodulation) functions that
`are not time critical Such as pilot channel processing, traffic
`channel processing (e.g., processing on Soft decisions) and
`so on. Modem processor 228 controls the operation of
`various circuit blocks within modem core 130. Sub-system
`processor 230 controls input/output (I/O) buses and periph
`erals. Processors 228 and 230 may be implemented with
`reduced instructing set computing (RISC) processors.
`RAMs 232 and ROMs 234 store data and code used by
`modem core 130.
`0035). Power control unit 140 controls the power for each
`of the collapsible power domains and is described in further
`detail below.
`0036 FIG. 2B shows an exemplary layout of a CMOS
`integrated circuit for modem processor 120. FIG. 2A shows
`the processing units for modem processor 120 but does not
`indicate the size of each unit. FIG. 2B shows the size of
`always-on power domain 210a versus the size of collapsible
`power domains 210b through 210e. In a typical implemen
`tation, the always-on power domain occupies only a Small
`portion (e.g., two to three percent) of the total die area of the
`integrated circuit, and the collapsible power domains occupy
`most of the die area. Thus, leakage current for the integrated
`circuit may be significantly reduced by powering down the
`collapsible power domains when not needed.
`0037 Power connection 212 for each collapsible power
`domain 210 includes appropriate hardware to Supply power
`to and remove power from the processing blocks within the
`power domain. Each collapsible power domain 210 can be
`powered down if none of the processing units in the domain
`is needed.
`0038 FIG. 3 shows a configuration 300 for connecting
`power domains 210 to power supply buses. Power connec
`
`tion 212a couples always-on power domain 210a directly to
`a power Supply buS 214a, which is denoted as Vs. Power
`connections 212b through 212e are for collapsible power
`domains 210b through 210e, respectively. For the embodi
`ment shown in FIG. 3, each of power connections 212b
`through 212e includes a headswitch that can be either
`enabled to power up the domain or disabled to power down
`the domain. The headswitch for each collapsible power
`domain X (where X=b, c, d, or e) may be implemented with
`a P-channel FET312 having a source that couples to a power
`Supply bus 214b (which is denoted as Vs), a drain that
`couples to an internal power bus for the power domain
`(which is denoted as VDD x), and a gate that receives a
`pwr ctrl X control signal for the power domain. The pWr c
`trl X signal is logic low to power up power domain X and
`logic high to power down power domain X. Power Supply
`buses 214a and 214b may have the same or different
`Voltages.
`0039 Power for the collapsible power domains may be
`controlled in other manners, and this is within the Scope of
`the invention. For example, a footSwitch between the power
`domain and circuit ground may be used to control power to
`the power domain. AS another example, both headswitch and
`footSwitch may be used for a given collapsible power
`domain. In general, an integrated circuit may include any
`number of power Supply buses. One power Supply bus may
`be used for input/output (I/O) pads for the integrated circuit
`and this power Supply buS may be powered on at all times
`while terminal 100 is powered on. Always-on power domain
`210a may then be coupled to this power supply bus for the
`I/O pads. Multiple power supply buses may be used to
`provide different Supply Voltages or for different power
`regimes.
`0040 Power control unit 140 includes various circuit
`blocks that Support powering on and off the collapsible
`power domains. For the embodiment shown in FIG. 2A,
`power control unit 140 includes State registers 242, a sleep
`controller 246, a clock controller 248, an interrupt controller
`250, and a power controller 252. State registers 242 store (1)
`powered down Status of the collapsed power domains and
`(2) pertinent hardware States (e.g., finite State machine
`(FSM) states) that cannot be restored by software upon
`power up.
`0041 Sleep controller 246 monitors activity and keeps
`track of Sleep timeline for each System being monitored.
`Terminal 100 may monitor one or multiple systems such as,
`for example, 1x-EV DV, 1x-EV DO, and GSM systems,
`which are described below and shown in FIG. 6. In an
`embodiment, Sleep controller 246 includes one sleep core
`for each System. Each Sleep core includes a Sleep counter
`and a sleep finite state machine (FSM). The sleep counter
`maintains System time continuity during Sleep. When the
`Sleep counter expires at the start of warm-up time (see FIG.
`4), sleep controller 246 interrupts power controller 252 to
`wake-up. The Sleep counter continues to count the duration
`of the warm-up time. When the sleep counter expires at the
`Start of on-line time, Sleep controller 246 interrupts modem
`processor 120 to indicate the Start of on-line processing.
`During the active state, a real time counter (RTC) within
`modem core 130 maintains system time for each system
`being monitored.
`0042 Clock controller 248 disables main clock 152 prior
`to powering down and enables main clock 152 after pow
`ering up. Interrupt controller 250 monitors input signals
`from other units external to modem processor 120. These
`
`Qualcomm, Ex. 1015, Page 10
`
`

`

`US 2005/OO64829 A1
`
`Mar. 24, 2005
`
`input Signals are received via the pads of modem processor
`120. Interrupt controller 250 detects for interrupts from these
`external units and alerts power controller 252 when it
`receives an external interrupt requiring modem processor
`120 to wake up.
`0.043 Power controller 252 generates various control
`Signals used to Support powering down and up the collaps
`ible power domains. Power controller 252 receives signals
`from Sleep controller 246 indicating the Start and end of a
`Sleep period and external interrupts from interrupt controller
`250. Power controller 252 may maintain a finite state
`machine (FSM) for each block to be controlled (e.g., main
`oscillator) and a FSM for each power domain to be sepa
`rately powered on and off. Based on these various inputs and
`the FSMs, power controller 252 generates the control signals
`to power down and up the collapsible power domains at the
`appropriate time. For example, power controller 252 can
`generate the pWr ctrl Signals for the Switches in power
`connections 212, as shown in FIG. 3. Power controller 252
`can also generate a signal for an external power management
`unit, which can then power up or down the power Supply
`bus(es) for the collapsible power domains.
`0044 Power control unit 140 stores information for the
`timeline for each System being monitored and determines
`the time periods in which the collapsible power domains
`may be powered down. Power control unit 140 may power
`down the collapsible power domains if the duration of Sleep
`is Sufficiently long (e.g., exceeds a predetermined time
`period). Power control unit 140 may forego powering down
`if the Sleep period is too short and powering down would not
`be justified by the Overhead associated with powering down
`and up. If the collapsible power domains are not powered
`down because the Sleep period is too short, then the main
`clock may still be disabled to cut off dynamic current and
`reduce power consumption.
`0.045 Power control unit 140 performs a number of tasks
`to properly power down and power up the collapsible power
`domains within modem processor 120. Table 1 lists some of
`the tasks that may be performed for powering down and up
`the collapsible power domains. Fewer, additional and/or
`different tasks may also be performed, depending on the
`design of modem processor 120.
`
`TABLE 1.
`
`down So that external units coupled to modem processor 120
`are minimally affected by the modem processor being pow
`ered down. Memory 156 stores code and data used by
`various processing units within modem processor 120 and is
`placed in a low power mode when the modem processor is
`powered down. The main clock is disabled, and main
`oscillator 152 is also powered off during sleep. Power is
`removed from each collapsible power domain by controlling
`the Switch in the power connection for that power domain.
`In general, complementary tasks are performed to power
`down and power up. Each of the tasks in Table 1 is described
`in further detail below.
`0047 Modem processor 120 includes various processing
`units that may be grouped into three different categories
`general-purpose processors, Specialized processors, and
`hardware blocks. The general-purpose processors (e.g., con
`troller 132, modem processor 228, and Sub-System processor
`230) operate based on software code and may be configured
`to perform various functions. Specialized processors (e.g.,
`modem DSP 226) operate based on firmware and are
`designed to perform specific functions (e.g., arithmetic func
`tions, powering down/up tasks, and So on). The hardware
`blocks (e.g., CDMA processing blockS 222) perform specific
`processing and may utilize registers to maintain State infor
`mation. The processing units within modem processor 120
`may be interdependent on one another. For example, the
`hardware blockS may be controlled by the Specialized pro
`ceSSors, which may in turned be controlled by the general
`purpose processors. In this case, the temporal order in which
`the processing units are restored after powering up is impor
`tant.
`0048. During sleep, other analog and digital circuit
`blocks within terminal 100 may also be powered down. For
`example, the radio frequency (RF) front end, power ampli
`fiers, oscillators, and So on for the transmit and receive paths
`are often powered down during sleep. Moreover, the cir
`cuitry for the transmit path does not need to be powered up
`to receive messages. For simplicity, only tasks and events
`related to powering down and up modem processor 120 are
`described below.
`0049 Many cellular systems use a paging channel to
`transmit messages to idle terminals. In a 1xEV DV System,
`the paging channel (PCH) is divided into (80 mSec) paging
`channel Slots. A terminal operating in a Slotted mode is
`assigned Specific slots on the paging channel. A slot cycle
`index (SCI) determines how often the terminal's assigned
`Slots appear on the paging channel. An SCI of one indicates
`that the assigned slots appear every 2.56 Seconds. Paging
`messages (if any) are sent to the terminal in its assigned
`Slots.
`0050 Different cellular systems may use different struc
`tures and formats for the paging channel. However, the same
`general concept is typically used for all paging channel
`implementations. A terminal is assigned to only a Small
`portion of the paging channel timeline and only needs to be
`active for a Small portion of the time to process the paging
`channel. To conserve power, the terminal can Sleep and most
`of the analog and digital circuits can be powered down.
`0051
`FIG. 4 shows a timeline for processing the paging
`channel in the 1xEV DV system. In FIG. 4, a new paging
`slot cycle for terminal 100 starts at time To. Terminal 100
`sleeps from time To until its next assigned slot. Terminal 100
`
`Powering Down Tasks
`Save pertinent hardware state 1
`registers from collapsible
`2
`power domains
`Put external memory 156 in
`low 2 power mode
`Freeze IC output pins
`3
`4 Disable main clock to
`5
`collapsible power domains
`6
`Power off collapsible power
`7
`domains
`Power off main oscillator 152 8
`
`1
`
`2
`
`5
`
`6
`
`3
`
`4
`
`Powering Up Tasks
`
`Power on main oscillator 152
`Power on collapsed power
`domains
`Enable main clock to collapsed
`power domains
`Take external memory 156 out
`of low power mode
`Reboot software
`Re-download firmware image
`Restore hardware registers
`Release IC output pins
`
`0046) Some hardware states may need to be saved before
`powering down So that modem processor 120 can properly
`resume operation upon being powered on. The output pins
`for modem processor 120 are maintained at the “latest” logic
`State, which is the logic State right before powering down,
`during the entire time that modem processor 120 is powered
`
`Qualcomm, Ex. 1015, Page 11
`
`

`

`US 2005/OO64829 A1
`
`Mar. 24, 2005
`
`wakes up at time T, prior to its next assigned slot, and
`powers on and warms up the necessary circuitry. Terminal
`100 receives and processes the paging channel Starting at
`time T. Terminal 100 finishes processing the paging chan
`nel at time Ts and thereafter goes back to Sleep if additional
`communication is not needed. The terminal may sleep for a
`Significant portion of the time. As an example, for the 1xEV
`system with SCI=1, the sleep time from To to T. may be
`2503 msec, the warm-up time from T to T. may be 17msec,
`and the active (i.e., on-line) time from T to Ts may be 40
`msec. In this case, terminal 100 can sleep for over 97 percent
`of the time.
`0.052
`FIG. 4 also shows an overlay of power collapse
`over the Sleep timeline. After completion of the on-line
`processing at time To, terminal 100 performs powering
`down tasks during the power-down period from time To to
`time T. Prior to the warm-up time, terminal 100 performs
`powering up tasks during the power-up period from time T.
`to time T.
`0053 FIG. 5A shows a timeline for a powering down
`sequence 510 to turn off power to the collapsible power
`domains within modem processor 120. Power control unit
`140 performs the tasks listed in Table 1 during the power
`down period after it has been determined that the terminal
`can go to Sleep because no additional communication is
`required. At time T, the pertinent hardware registers are
`Saved. At time T, memory 156 is placed in the low power
`mode during sleep. At time T, the State of the output pins
`for modem processor 120 is frozen. At time T, the main
`clock is disabled. At time Ts, power is removed from the
`collapsible power domains. At time T, main oscillator 152
`is powered down. The tasks for powering down may be
`performed in other chronological orders than that shown in
`FIG. 5A. These tasks can typically be performed within a
`Short period of time (e.g., one mSec).
`0054 FIG. 5B shows a timeline for a powering up
`sequence 520 to turn on power to the collapsible power
`domains within modem processor 120. Power control unit
`140 performs the tasks listed in Table 1 during the power-up
`period prior to the warm-up time for the assigned