P C C A R D S TA N D A R D
`
`Volume 2
`Electrical Specification
`
`Kingston Exhibit 1012 - 1
`
`

`

`PCMCIA
`JEIDA
`
`'1999, PCMCIA/JEIDA
`All rights reserved.
`
`No part of this publication may be
`reproduced, stored in a retrieval
`system, or transmitted, in any form or
`by any means, mechanical,
`electronic, photocopying, recording
`or otherwise, without prior written
`permission of PCMCIA and JEIDA.
`Printed in the United States of
`America.
`
`PCMCIA (Personal Computer
`Memory Card International
`Association)
`2635 North First Street, Suite 209
`San Jose, CA 95134 USA
`+1-408-433-2273
`+1-408-433-9558 (Fax)
`
`JEIDA (Japan Electronic Industry
`Development Association)
`Kikai Shinko Kaikan, 3-5-8, Shibakoen
`Minato-ku, Tokyo 105, JAPAN
`+81-3-3433-1923
`+81-3-3433-6350 (Fax)
`
`The PC Card logo and PC Card are
`trademarks of PCMCIA, registered in
`the United States. The PC Card logo
`and PC Card are trademarks of
`JEIDA, registered in Japan.
`
`PCMCIA HAS BEEN NOTIFIED BY
`CERTAIN THIRD PARTIES THAT
`THE IMPLEMENTATION OF THE
`STANDARD WILL REQUIRE A
`LICENSE FROM THOSE THIRD
`PARTIES TO AVOID
`INFRINGEMENT OF THEIR
`RIGHTS. PCMCIA HAS OBTAINED
`FROM SOME, BUT NOT ALL , OF
`THOSE PARTIES A GRANT OF
`IMMUNITY THAT PCMCIA WILL
`EXTEND TO YOU, CONTINGENT
`UPON YOUR ENTERING INTO
`AND DELIVERING TO PCMCIA
`THE RECIPROCAL GRANT OF
`IMMUNITY AGREEMENT
`CONTAINED ELSEWHERE IN
`THIS STANDARD.
`
`IMPORTANT:
`In order to receive the Grant of
`Immunity, the owner of this
`Standard must sign and return the
`enclosed Registration Card to:
`PCMCIA
`2635 North First Street, Suite 209
`San Jose, CA 95134 USA
`
`NEITHER PCMCIA NOR JEIDA
`MAKES ANY WARRANTY,
`EXPRESS OR IMPLIED, WITH
`RESPECT TO THE STANDARD,
`INCLUDING AS TO NON-
`INFRINGEMENT,
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`FOR A PARTICULAR PURPOSE.
`THIS STANDARD IS PROVIDED TO
`YOU (cid:210)AS IS.(cid:211)
`
`Document No. 0299-02-2000
`
`First Printing, February 1999
`
`Kingston Exhibit 1012 - 2
`
`

`

`ELECTRICAL SPECIFICATION
`
`CONTENTS
`1. Overview ______________________________________________1
`1.1 Summary of Electrical Specification Changes....................................................................2
`1.1.1 PCMCIA 2.0/JEIDA 4.1 (September 1991).......................................................................................................................2
`1.1.2 PCMCIA 2.1/JEIDA 4.2 (July 1993)....................................................................................................................................2
`1.1.3 PC Card Standard February 1995 Release (Release 5.0) ............................................................................................2
`1.1.4 PC Card Standard March 1995 Update (Release 5.01)...............................................................................................3
`1.1.5 PC Card Standard May 1995 Update (Release 5.02)...................................................................................................3
`1.1.6 PC Card Standard November 1995 Update (Release 5.1)..........................................................................................3
`1.1.7 PC Card Standard May 1996 Update (Release 5.2).....................................................................................................3
`1.1.8 PC Card Standard 6.0 Release (March 1997).................................................................................................................3
`1.1.9 PC Card Standard 6.1 Release (April 1998)....................................................................................................................3
`1.1.10 PC Card Standard 7.0 Release (February 1999)..........................................................................................................3
`1.2 Conventions .........................................................................................................................3
`1.2.1 Signal Naming............................................................................................................................................................................4
`1.2.2 Numeric Representation..........................................................................................................................................................4
`1.2.3 Bit Action Representation.......................................................................................................................................................4
`1.2.4 Signal Summary........................................................................................................................................................................4
`
`2. Common Pin Description ________________________________5
`2.1 Power and Ground Pins ......................................................................................................5
`2.1.1 VCC and GND Pins....................................................................................................................................................................5
`2.1.2 VPP1 and VPP2 Pins...................................................................................................................................................................5
`2.2 Interface Configuration Pins ...............................................................................................6
`2.2.1 Card Detect Pins (CD[2::1]# and CCD[2::1]#)..................................................................................................................6
`2.2.2 Voltage Sense Pins (VS[2::1]# and CVS[2::1]).................................................................................................................6
`
`3. Card Type Detection Mechanism _________________________7
`3.1 PC Card Encodings .............................................................................................................7
`3.2 Socket Key Selection ............................................................................................................8
`3.3 Graceful Rejection in 16—bit PC Card Only Sockets...........................................................8
`3.4 Determining Card Type in CardBus PC Card Capable Sockets........................................9
`4. 16-bit PC Card Electrical Interface _______________________11
`4.1 Compatibility Issues .........................................................................................................11
`4.1.1 RESET and WAIT# Support................................................................................................................................................11
`4.1.2 VS1# replaces RFSH (pin 43)...............................................................................................................................................11
`4.2 Pin Assignments................................................................................................................11
`4.3 16-bit PC Card Features....................................................................................................14
`
`' 1999 PCMCIA/JEIDA
`
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`Kingston Exhibit 1012 - 3
`
`

`

`CONTENTS
`
`4.3.1 Memory Address Space........................................................................................................................................................14
`4.3.2 Memory Only Interface .........................................................................................................................................................15
`4.3.3 I/O Address Space..................................................................................................................................................................15
`4.3.4 I/O Interface..............................................................................................................................................................................16
`4.3.5 Custom Interfaces....................................................................................................................................................................16
`4.3.6 Configurable Cards................................................................................................................................................................17
`4.4 Signal Description..............................................................................................................17
`4.4.1 Address BUS (A[25::0]).........................................................................................................................................................17
`4.4.2 Data BUS (D[15::0])................................................................................................................................................................17
`4.4.3 Card Enable (CE[2::1]#)........................................................................................................................................................17
`4.4.4 Output Enable (OE#) ..............................................................................................................................................................18
`4.4.5 Write Enable (WE#)................................................................................................................................................................18
`4.4.6 Ready (READY).......................................................................................................................................................................18
`4.4.7 Interrupt Request (IREQ#) [I/O and Memory Interface]...........................................................................................19
`4.4.7.1 Interrupt Request Routing......................................................................................................................................19
`4.4.7.2 Level and Pulsed Mode Interrupt Support......................................................................................................20
`4.4.7.2.1 Level Mode Interrupt Signal ......................................................................................................................20
`4.4.7.2.2 Pulsed Mode Interrupt Signal....................................................................................................................20
`4.4.8 Card Detect (CD[2::1]#).........................................................................................................................................................21
`4.4.9 Write Protect (WP) [Memory Only Interface]................................................................................................................21
`4.4.10 I/O Is 16 Bit Port (IOIS16#) [I/O and Memory Interface].....................................................................................21
`4.4.11 Attribute Memory Select (REG#)....................................................................................................................................21
`4.4.12 Battery Voltage Detect (BVD[2::1]) [Memory Only Interface].............................................................................22
`4.4.13 Status Changed (STSCHG#) [I/O and Memory Interface]....................................................................................22
`4.4.14 Audio Digital Waveform (SPKR#) [I/O and Memory Interface].......................................................................22
`4.4.15 Program and Peripheral Voltages (VPP[2::1])............................................................................................................23
`4.4.16 Voltage and Ground (VCC & GND)...............................................................................................................................23
`4.4.16.1 Socket VCC for CIS Read......................................................................................................................................23
`4.4.16.2 PC Card VCC for CIS Read..................................................................................................................................24
`4.4.16.3 Changing PC Card VCC........................................................................................................................................24
`4.4.17 Voltage Sense (VS[2::1]#) ...................................................................................................................................................24
`4.4.18 I/O Read (IORD#) [I/O and Memory Interface] .......................................................................................................25
`4.4.19 I/O Write (IOWR#) [I/O and Memory Interface] .....................................................................................................25
`4.4.20 Card Reset (RESET).............................................................................................................................................................26
`4.4.21 Extend Bus Cycle (WAIT#)................................................................................................................................................26
`4.4.22 Input Port Acknowledge (INPACK#) [I/O and Memory Interface] ...................................................................26
`4.5 DMA Signals Replacing I/O Interface Signals.................................................................26
`4.5.1 DMA Request (DREQ#).........................................................................................................................................................26
`4.5.2 DMA Acknowledge (DACK) [replaces REG#].............................................................................................................27
`4.5.3 DMA Read (IOWR#)..............................................................................................................................................................27
`4.5.4 DMA Write (IORD#)..............................................................................................................................................................27
`4.5.5 Terminal Count (TC#)............................................................................................................................................................27
`4.6 Memory Function...............................................................................................................27
`4.6.1 Common Memory Function.................................................................................................................................................27
`
`iv
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`'1999 PCMCIA/JEIDA
`
`Kingston Exhibit 1012 - 4
`
`

`

`ELECTRICAL SPECIFICATION
`
`4.6.1.1 Common Memory Read Function for PC Cards ...........................................................................................27
`4.6.1.2 Common Memory Write Function for PC Cards..........................................................................................28
`4.6.1.3 Common Memory Write Function for OTPROM, EPROM and Flash Memory...............................28
`4.6.2 Attribute Memory Function.................................................................................................................................................28
`4.6.2.1 Attribute Memory Read Function ......................................................................................................................29
`4.6.2.2 Attribute Memory Write Function.....................................................................................................................29
`4.6.2.3 Attribute Memory Write Function for Dual Supply OTPROM, EPROM and Flash Memory.....29
`4.6.3 Write Protect Function...........................................................................................................................................................30
`4.7 Timing Functions...............................................................................................................30
`4.7.1 Common Memory Read Timing........................................................................................................................................30
`4.7.2 Common and Attribute Memory Write Timing..........................................................................................................32
`4.7.2.1 Common Memory Write Timing........................................................................................................................33
`4.7.3 Attribute Memory Read Timing Specification.............................................................................................................33
`4.7.4 Attribute Memory Write Timing Specification............................................................................................................33
`4.7.5 Memory Timing Diagrams.................................................................................................................................................34
`4.8 DMA Function...................................................................................................................35
`4.8.1 DMA Read Function (Memory Read - I/O Write) ......................................................................................................36
`4.8.2 DMA Read Timing (Memory Read - I/O Write).........................................................................................................36
`4.8.3 DMA Write Function (I/O Read - Memory Write).....................................................................................................37
`4.8.4 DMA Write Timing (I/O Read - Memory Write)........................................................................................................38
`4.9 Electrical Interface .............................................................................................................39
`4.9.1 Signal Interface.........................................................................................................................................................................39
`4.9.2 Memory Address Decoding................................................................................................................................................40
`4.9.2.1 Function Configuration Registers Address Decoding................................................................................41
`4.9.3 I/O Address Space Decoding .............................................................................................................................................41
`4.9.3.1 Independent I/O Address Window..................................................................................................................41
`4.9.3.2 Overlapping I/O Address Window..................................................................................................................42
`4.10 Card Detect......................................................................................................................43
`4.11 Battery Voltage Detect ....................................................................................................43
`4.12 Power-up and Power-down............................................................................................44
`4.12.1 Power-up/Power-down Timing.....................................................................................................................................44
`4.12.2 Average Current During Card Configuration............................................................................................................45
`4.12.3 Data Retention........................................................................................................................................................................46
`4.12.4 Supplement ..............................................................................................................................................................................46
`4.13 I/O Function....................................................................................................................46
`4.13.1 I/O Transfer Function.........................................................................................................................................................46
`4.13.2 I/O Input Function for I/O Cards...................................................................................................................................46
`4.13.3 I/O Output Function for I/O Cards................................................................................................................................47
`4.13.4 I/O Read (Input) Timing Specification.........................................................................................................................48
`4.13.5 I/O Write (Output) Timing Specification.....................................................................................................................50
`4.14 Function Configuration ...................................................................................................51
`4.14.1 Overview..................................................................................................................................................................................51
`4.14.2 Single Function PC Cards...................................................................................................................................................51
`
`' 1999 PCMCIA/JEIDA
`
`v
`
`Kingston Exhibit 1012 - 5
`
`

`

`CONTENTS
`
`4.14.3 Multiple Function PC Cards..............................................................................................................................................51
`4.14.4 Function Configuration Registers (FCRs).....................................................................................................................52
`4.15 Card Configuration .........................................................................................................53
`4.15.1 Configuration Option Register.........................................................................................................................................54
`4.15.2 Configuration and Status Register .................................................................................................................................56
`4.15.3 Pin Replacement Register...................................................................................................................................................58
`4.15.4 Socket and Copy Register...................................................................................................................................................59
`4.15.5 Extended Status Register ...................................................................................................................................................59
`4.15.6 I/O Base Registers (0 .. 3)...................................................................................................................................................60
`4.15.7 I/O Limit Register................................................................................................................................................................60
`4.15.8 Power Management Support Register...........................................................................................................................61
`4.15.9 Address Extension Registers............................................................................................................................................62
`4.16 Indirect Access to PC Card Memory ..............................................................................64
`5. CardBus PC Card Electrical Interface ____________________ 67
`5.1 CardBus PC Card Signal Description...............................................................................67
`5.1.1 Pin Assignments.......................................................................................................................................................................68
`5.1.2 Signal/Pin Description..........................................................................................................................................................72
`5.1.2.1 System Pins.................................................................................................................................................................72
`5.1.2.2 Address and Data Pins..........................................................................................................................................72
`5.1.2.3 Interface Control Pins..............................................................................................................................................73
`5.1.2.4 Arbitration Pins (Bus Masters Only)................................................................................................................73
`5.1.2.5 Error Reporting Pins...............................................................................................................................................74
`5.1.2.6 Interrupt Request Pin...............................................................................................................................................74
`5.1.2.7 Additional Signals..................................................................................................................................................74
`5.1.3 Central Resource Functions..................................................................................................................................................75
`5.2 CardBus PC Card Operation............................................................................................75
`5.2.1 Bus Commands........................................................................................................................................................................75
`5.2.1.1 Command Definition..............................................................................................................................................75
`5.2.1.2 Command Usage Rules..........................................................................................................................................77
`5.2.2 CardBus PC Card Protocol Fundamentals....................................................................................................................78
`5.2.2.1 Basic Transfer Control...........................................................................................................................................79
`5.2.2.2 Addressing.................................................................................................................................................................79
`5.2.2.3 Byte Alignment..........................................................................................................................................................81
`5.2.2.4 Bus Driving and Turnaround..............................................................................................................................8 1
`5.2.3 Bus Transactions .....................................................................................................................................................................82
`5.2.3.1 Read Transaction.....................................................................................................................................................82
`5.2.3.2 Write Transaction....................................................................................................................................................84
`5.2.3.3 Transaction Termination......................................................................................................................................84
`5.2.3.3.1 Master Initiated Termination....................................................................................................................85
`5.2.3.3.2 Target Initiated Termination.....................................................................................................................87
`5.2.4 Arbitration.................................................................................................................................................................................91
`5.2.5 Arbitration Signaling Protocol..........................................................................................................................................91
`5.2.5.1 Fast Back-to-Back Transactions.........................................................................................................................93
`
`vi
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`'1999 PCMCIA/JEIDA
`
`Kingston Exhibit 1012 - 6
`
`

`

`ELECTRICAL SPECIFICATION
`
`5.2.5.2 CardBus PC Card Idle Condition.......................................................................................................................95
`5.2.5.3 Latency.........................................................................................................................................................................95
`5.2.5.3.1 Managing Latency on CardBus PC Card..............................................................................................95
`5.2.5.3.2 Low Latency Design Guidelines...............................................................................................................96
`5.2.6 Exclusive Access......................................................................................................................................................................97
`5.2.6.1 Starting an Exclusive Access................................................................................................................................99
`5.2.6.2 Continuing an Exclusive Access.......................................................................................................................100
`5.2.6.3 Accessing a Locked Agent..................................................................................................................................101
`5.2.6.4 Completing an Exclusive Access......................................................................................................................102
`5.2.6.5 Supporting CBLOCK# and Write-back Cache Coherency......................................................................102
`5.2.6.6 Complete Bus Lock................................................................................................................................................103
`5.2.7 Other Bus Operations..........................................................................................................................................................103
`5.2.7.1 Device Selection......................................................................................................................................................103
`5.2.7.2 Special Cycle............................................................................................................................................................104
`5.2.7.3 Address/Data Stepping......................................................................................................................................105
`5.2.7.4 Configuration Cycle..............................................................................................................................................106
`5.2.7.4.1 Generating Configuration Cycles..........................................................................................................108
`5.2.7.4.1.1 Configuration Mechanism...........................................................................................................108
`5.2.7.4.1.2 Generating Special Cycles with the Configuration Mechanism ....................................110
`5.2.8 Error Functions.....................................................................................................................................................................110
`5.2.8.1 Parity..........................................................................................................................................................................110
`5.2.8.2 Error Reporting......................................................................................................................................................112
`5.2.8.2.1 Parity Error Response and Reporting on CPERR#..........................................................................112
`5.2.8.2.2 Error Response and Reporting on CSERR#.......................................................................................113
`5.2.9 Cache Support.............................................................................................................................................................