RSC-164/ RSC-164iData Book
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`Fully static operation; clock speed from DC to14.32 MHzHighly-Integrated Single-Chip Solution
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`Pulse width modulator for direct speaker driveLow Power Requirements
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`Low-power 32,768 Hz oscillator for clockapplicationsHigh-Quality Recognition and Synthesis
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`GENERAL DESCRIPTIONThe RSC-164 and RSC-164i are low-cost speechrecognition ICs designed for use in consumerelectronics. They combine an 8-bit processor withneural-net algorithms to provide high-qualityspeaker-independent speech recognition, speaker-dependent speech recognition, and speakerverification. The chips also support speech synthesis,voice record/playback, 4-voice music synthesis,speaker verification, and system control. TheseCMOS device includes on-chip RAM, ROM, 16general-purpose I/O lines, A/D and D/A converters,and a 4-MIPS dedicated processor.In addition to providing the horsepower needed toperform speech recognition and speech synthesis, theprocessor has sufficient cycles available for general-purpose product control. The RSC Development Kitallows developers to create custom applications forthe RSC chips. The Development Kit includes anassembler, linker, simulator, in-circuit emulator, andlibrary of Sensory technology object code.The highly-integrated nature of these chips reduceexternal parts count. A complete system may be builtwith few additional parts other than a battery,speaker, microphone, and audio input supportcircuitry. Low power requirements make the RSCchips an ideal solution for battery-powered andhand-held devices.The RSC chips use a pre-trained neural network toperform speaker-independent speech recognition,while high-quality speech synthesis is achieved usinga time-domain compression scheme that improves onconventional ADPCM. Four-voice music synthesisallows multiple, simultaneous instruments forharmonizing. Dynamic AGC control can compensatefor people not optimally positioned with respect tothe microphone or for people who speak too softly orloudly.FEATURESHigh-Performance Processor
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`Recognition accuracy better than 96%(Speaker Independent) and 99% (SpeakerDependent).
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`Synthesis data rates from 5,000-15,000 bitsper second
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`Separate 16-bit Address and 8-bit Data busescompatible with common memory components
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`Separate Code and Data address spaces andmemory strobes
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`Instruction set compatibility between RSC-164and RSC-164i
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`Optional AGC control compensates forvariations in input signalEasily Expanded to larger-scale systems
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`From the Interactive Speech™ Line of Products
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`4-MIPS performance at 14.32 MHz
`12-16 general-purpose I/O lines
`Interrupts, timers and counters
`Internal 64K ROM
`384 bytes RAM
`12-bit A/D (Analog to Digital converter)
`Requires single 3.5 to 5.0 volt supply.
`Typical current drain is 10 mA
`4-voice music synthesis capabilities
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`© 1996 SENSORY, INC.ALL RIGHTS RESERVEDP/N 80-0007-5Sensory is registered by the U.S. Patent and TrademarkOffice. All other trademarks or registered trademarks arethe property of their respective owners.From the Interactive Speech™ Line of ProductsIMPORTANT NOTICESSensory reserves the right to make changes to or to discontinue any product or service identified in this publication at any time without notice in orderto improve design and supply the best possible product. Sensory does not assume responsibility for use of any circuitry other than circuitry entirelyembodied in a Sensory product. Information contained herein is provided gratuitously and without liability to any user.Reasonable efforts have been made to verify the accuracy of this information but no guarantee whatsoever is given as to the accuracy or as to itsapplicability to particular uses.Applications described in this data sheet are for illustrative purposes only, and Sensory makes no warranties or representations that the InteractiveSpeechTM line of products will be suitable for such applications. In every instance, it must be the responsibility of the user to determine the suitability ofthe products for each application. Sensory products are not authorized for use as critical components in life support devices or systems.Sensory conveys no license or title, either expressed or implied, under any patent, copyright, or mask work right to the Interactive SpeechTM line ofproducts, and Sensory makes no warranties or representations that the Interactive SpeechTM line of products are free from patent, copyright, or maskwork right infringement, unless otherwise specified. Nothing contained herein shall be construed as a recommendation to use any product in violationof existing patents or other rights of third parties. The sale of any Sensory product is subject to all Sensory Terms and Conditions of Sales and SalesPolicies.Data Book Revision 2.5August 1996
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`TEL: (408) 744-9000
`FAX: (408) 744-1299
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`East Weddell Drive
`5 21
`Sunnyvale, CA 94089
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`RSC-164/RSC-164iDATA BOOK
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of ProductsTable of Contents1.INTRODUCTION............................................................................................................................................12.RSC-164 ARCHITECTURE............................................................................................................................23.DIFFERENCES BETWEEN THE RSC-164 AND THE RSC-164i................................................................34.MEMORY ORGANIZATION........................................................................................................................45.MEMORY MAP..............................................................................................................................................56.GENERAL PURPOSE I/O..............................................................................................................................67.INTERRUPTS..................................................................................................................................................88.RESET AND CLOCKS.................................................................................................................................109.TIMERS AND COUNTERS..........................................................................................................................1110.ANALOG OUTPUTS...................................................................................................................................1111.HARDWARE DEBUG FEATURES...........................................................................................................1212.DESIGN CONSIDERATIONS....................................................................................................................1313.OMNI-DIRECTIONAL MICROPHONE...................................................................................................1714.POWER CONSUMPTION AND POWER SUPPLY CONSIDERATIONS..............................................1915.DIE BOND PAD, PLCC AND QFP PIN DESCRIPTIONS (VERSION “B”)............................................2016.ABSOLUTE MAXIMUM RATINGS..........................................................................................................2117.D.C. CHARACTERISTICS.........................................................................................................................2118.A.C. CHARACTERISTICS (EXTERNAL MEMORY ACCESSES)........................................................2219.RSC-164 INSTRUCTION SET....................................................................................................................2320.RSC-164 SPECIAL FUNCTION REGISTER (SFR) SUMMARY.............................................................2621.SPECIAL DATA SPACE ADDRESSES SUMMARY................................................................................4022.ORDERING INFORMATION....................................................................................................................42
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products11.IntroductionThe RSC-164 is the first in a family of high-performance 8-bit microprocessors featuring a high level ofintegration, targeted to high-accuracy, low-cost speech recognition applications. The RSC-164 family is designedto bring a high degree of integration and versatility to low-cost, power-sensitive consumer applications.Various functional units have been integrated onto the CPU core in order to reduce total system cost, yet increasesystem reliability, without degrading system performance. By integrating data conversion, recognition andsynthesis functionality, and ROM1 storage with a CPU core on a single chip, dramatic cost and power reductionsare achieved. Thus, the RSC-164 family is able to provide 4 MIPS of integer performance at 14.32 MHz. Thisallows customer applications to achieve maximum performance at minimum cost.The CPU core embedded in the RSC-164 is an 8-bit, variable-length-instruction, microprocessor. The instructionset is loosely based on Intel’s 8051 (cid:212), having a variety of addressing mode mov instructions. But the RSC-164processor avoids the limitations of dedicated A, B, and DPTR registers by having completely symmetrical sourceand destinations for all instructions. The 384 bytes of internal RAM are organized as a Register Space. Allarithmetic operation instructions may be applied to any register. Any pair of adjacent registers (at an even address)may be used as the 16-bit pointer to either the source or destination for a data movement instruction. Instructionclasses allow the pointer to access internal or external Code Space, internal Register Space, or external Data Space.Architecturally, the RSC-164’s separate data and address buses allow use of standard EPROMs, ROMs, andSRAMs with little or no additional decoding. Provision of separate read and write signals for each externalmemory space further simplifies interfacing.Creating applications using the RSC-164 or the RSC-164i requires the development of electronic circuitry,software code, and speech/music data files (“linguistics”). This document provides detailed information on thoseaspects of the RSC-164 architecture that are important to product designers and programmers. It describes thephysical interface to the chip, printed circuit board layout and other design considerations, the RSC-164’sinstruction set, and memory organization. Refer to the RSC Development Kit Manual for information on usingSensory’s technology code for speech recognition, speaker verification, speech synthesis, and voice record andplayback. Description of vocabulary development (“linguistics”) information is beyond the scope of this documentand is covered in Design Note 1 (P/N 80-0014-1).1 The RSC-164 internal ROM contains primarily Sensory library code; The internal ROM in the RSC-164i isapplication specific, with the amount available for user applications decreasing as the number of synthesis words orother technology usage increases.
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`• An 8-bit RISC microprocessor.
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`• On-chip ROM (64 Kbytes) and RAM(384 bytes), and the ability to addressoff-chip RAM or ROM.
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`RSC-164/RSC-164iDATA BOOK 2From the Interactive Speech™ Line of Products2. RSC-164 ArchitectureThe RSC-164 is a highly integrated devicethat combines:
`• An analog-to-digital converter, a digital-to-analog converter, and a pulse widthmodulator.The RSC-164 has an external memoryinterface for accessing external RAMs orROMs. It also has an internal ROM that canbe enabled or disabled (partially or fully) bypin inputs (signals -XMH, -XML; see page4). The RSC-164i does not access externalparallel memory and relies solely on theinternal ROM for its program storage needs.The 8-bit processor can directly access 384on-chip registers (RAM), of which 352 aregeneral purpose registers and 32 are SpecialFunctions Registers (SFRs). The instructionset accessing these registers is completelysymmetrical, allowing movs, arithmetic, andlogical operations with any register as thedestination. Two bi-directional ports provide16 general purpose I/O pins to communicatewith external devices (see page 6). The RSC-164 has a high frequency (14.32 MHz) oscillator as well as a lowfrequency (32,768 Hz) oscillator suitable for timekeeping applications. The processor clock can be selected fromeither source, with a selectable divider value. Sensory’s technology code requires the use of the 14.32 MHz clock.The device performs speech recognition when running at 14.32 MHz, with an optional divide-by-2 CPU clock (seepage 10).There are two programmable 8-bit counters / timers, one derived from each oscillator.A microphone with an external preamp converts sound into two audio signals that are fed into the AIN0 and Ain1inputs of the RSC-164. The gain of the external preamp may be controlled by the RSC-164 in some designs. TheRSC-164 uses an ADC (Analog-to-Digital Converter) and a Sample and Hold (SH) circuit to convert the incominganalog speech signal into digital data. The output audio signal of the RSC-164 is derived either from a DAC(Digital-to-Analog Converter) or a PWM (Pulse Width Modulator).In addition to its on-chip ROM and RAM, the RSC-164 has 8 data lines (D[7:0]) and 16 address lines (A[15:0]),along with associated control signals (-RDC, -RDD, -WRC, -WRD, -XML, -XMH) for interfacing to externalmemory. The memory control signals on the RSC-164 and the processor instruction set provide independent Codeand Data spaces, allowing configuration of systems up to 192 Kbytes with no additional hardware decoding. TheRSC-164i does not contain these address, data, and control signals. The RSC-164 features 16 general-purpose I/Opins (Px.y) for product and memory bank control; the RSC-164i has 12 general purpose I/O lines.ANALOGCONTROLADCEXTERNALMEMORYINTERFACEADCMUXCPUTIMING AND CONTROLTIMER1TIMER2OSC1OSC2PORT0INTERRUPT LOGIC32K x 832K x 8HIGHLOWINTERNAL ROMAIN0AIN1SHDACOUTBUFOUT/PWMXI1, XO1XI2, XO2P0.0-P0.7P1.0-P1.7A[15:0]D[7:0]-RDC-WRD-RDD-WRC384 bytes8 bytes-XMH-XML-RESET-TE1/PWMDACPULSE WIDTHMODULATORSTACK SPACEREGISTER SPACEPORT1BREAK POINTREGISTER Figure 1 -- RSC-164 Block Diagram
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`limited supportVoice record and playback
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products33. Differences Between the RSC-164 and the RSC-164iThe main difference between the RSC-164 and the RSC-164i is that the former can access external memorydevices. Also, the RSC-164 has four more general purpose I/O pins than the RSC-164i. The instruction sets forboth devices are identical2. Although the RSC-164 provides significant and flexible expansion capabilities throughthe use of external RAM or ROM, the RSC-164i must rely on limited internal memory for all of its ROM andRAM requirements. The RSC-164i can also interface to serial memory through the I/O lines for data storage.These finite resources restrict the capabilities of products based on the RSC-164i. The product specification for anRSC-164i must be carefully crafted in consultation with Sensory to maximize the use of on-chip memory. Eachapplication will have its own specific limitations, but the table below summarizes some useful guidelines forplanning purposes. Not all of the maximums can be achieved in a single RSC-164i design. For example, arecognition vocabulary of 40 words may limit the speech synthesis to substantially less than 25 seconds.DescriptionRSC-164RSC-164iCapabilities:Speaker independent (SI) recognition
`not supportedSI Recognition Capacity :Maximum number of words per recognition set31414Total recognition vocabulary size in words, all setsunlimited40 words4SD Recognition Capacity :Maximum number of words per recognition set364645Total recognition vocabulary size in words, all setsunlimited5125Speaker Verification Capacity :Number of speakers identified per set364645Synthesized Speech Capacity:Maximum total length of all messagesunlimited25 seconds4Music Synthesis CapacityNumber of simultaneous independent musical voices44Number of musical octaves available2-462Number of musical tunes availableunlimited6Requirement for custom ROM masks:Use of the RSC-164i requires custom-masked ROMs.Custom-masked parts are not stocked by SensoryCustom masked ROMnot requiredCustom masked ROMrequired 2 Software for RSC-164i applications may be completely developed and verified using the RSC Development Kitand an external 64K ROM memory before committing to an RSC-164i ROM mask.3 Practical limitations to maintain accuracy above 95%.4 Assumes the use of on-chip ROM only.5 Assumes the use of external serial memory devices.6 Depends on choice of musical instrument.
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`Speaker dependent (SD) recognition
`Speech synthesis and special sound effects
`Speaker verification
`Four-voice music generation
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`RSC-164/RSC-164iDATA BOOK 4From the Interactive Speech™ Line of Products4. Memory OrganizationInternal MemoryInternal ROM is organized as two banks of 32K bytes each, both mapped into code space. Either of the twointernal banks may be independently disabled using external inputs; input pin -XML disables the lower 32K[0000h-7FFFh] bank, while input pin -XMH disables the upper 32K [8000h-FFFFh] bank. When a bank isdisabled, read accesses to it are directed to off-chip code space. Write accesses to the code space are directed toexternal memory off-chip. Except for specific addresses in the last page of memory (described on page 5), read andwrite accesses to data space are always directed to external memory.External MemoryThe RSC-164 allows for extended message lengths and expanded program functionality by using external memory.There are 30 pins that provide an interface between the RSC-164 and external ROM or RAM. The 16 address lineoutputs, A[15:0], are shared for accesses to external code space or data space. The 8 data lines, D[7:0], are bi-directional, and are normally inputs except when there is a write to external memory. Refer to MEMORY MAP (onpage 5) for details on accessing external code and data spaces through movc and movx instructions.The RSC-164 uses the -RDC, -WRC, -RDD and -WRD signals to strobe data to or from memory or I/O devices.The -RDC and -WRC strobes are provided for accessing code space, while the -RDD and -WRD strobes are used toaccess data space. These four memory strobes are all active low (see page 22 for timing information). Using thesestrobes, the RSC-164 can directly access 64K of external code space and 64K of external data space in addition toits internal 64K of code space. External memory and I/O devices can reside in either code space or data space, asdetermined by the user application. Executable code must reside in code space; tables and other data may reside incode space or data space. Using I/O bits (from Port 1), additional external decoding can be used to bank selectbetween multiple RAMs or ROMs. This method allows for external storage requirements larger than the combined192K addressed directly by the RSC-164.The RSC-164i does not address external memory, and does not include the address A[15:0], data D[7:0], orcontrol[-RDC, -WRC, -RDD, -WRD, -XML, -XMH] signals for accessing external memory.Use of 100nS or faster external memories is recommended when operating at 14.32 MHz with one wait state.Given below is a simple representation of the internal ROM memory control and a block diagram of an externalmemory implementation illustrating a single 32Kx8 data space RAM and a bank switched 1 megabyte code ROM.The P1.4 signals controls whether -RDD accesses RAM or ROM, and P1.0-P1.3 provide the bank address bits.
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`- RDCP1.0P1.1P1.2P1.3A16A17A18A19
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`ADDRADDRDATADATA158168
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`1M x 8
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`-XML-XMH
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`ADDR[15:0]
`DATA[7:0]
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`32K x 8
`RAM
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`- RDD- WRD
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`Decoding
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`Figure 2-- Internal ROM memory controlFigure 3 --External memory implementation
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products55. Memory MapThe RSC-164 has three address spaces: Code Space, DataSpace, and Register Space. Code space is typically ROM.Data space may be either ROM or RAM. Register space islimited to on-chip SRAM. The instruction set providesseparate instructions for accessing each space. Executablecode must reside in code space; tables and other data mayreside in code space or data space. Register space isintended primarily for variables.The internal ROM and off-chip code space memory maybe accessed using movc instructions. The off-chip dataspace is accessed using movx instructions, while the on-chip register space is accessed using mov instructions. Forthe RSC-164, writes to code space are always directed off-chip, while the RSC-164i ignores writes to code space.The internal ROM is organized as two code space banksof 32K bytes each. The RSC-164 allows the banks to beindependently disabled using external inputs: the lowbank (address range 0000h-7FFFh) can be disabled byasserting pin input -XML while the high bank (addressrange 8000h-FFFFh) can be disabled by asserting pininput -XMH. This feature is used extensively to expandaddressable code space beyond 64K bytes. The RSC-164irelies entirely on the internal ROM for its storage needsand therefore the internal ROM cannot be disabled.The SRAM register space supports 8-bit addresses, soonly 256 bytes may be directly addressed. Generalpurpose registers are located between addresses 000h and0BFh. A 32-byte bank of SFRs (special function registers) resides at addresses 0E0h-0FFh. The 32-byte bank ataddresses 0C0h-0DFh may be mapped to any of the six lower 32-byte banks in page 0 (addresses 000h through0BFh), or to six additional 32-byte banks in page 1 (addresses 100h-1BFh. A special function register controls thismapping, providing a total of 384 bytes of SRAM register space.Off-chip memory (and memory-mapped I/O) is accessed using a 16-bit address bus and an 8-bit data bus. Separateread / write strobes are generated for access to external code and data spaces. This allows the RSC-164 to directlyaccess 64K bytes of external code memory and 64K bytes of external data memory. Bank switching is commonlyimplemented using I/O pins to select additional off-chip memory. Because the RSC-164i lacks the ability to accessexternal parallel memory, it does not have the external address and data buses and the associated read and writestrobe outputs.Certain addresses in the range of 0FF00h-0FFFFh of Data Space are mapped internally, so addresses in this lastpage of data space are not generally accessible in external memory. See Special Data Space Addresses, page 40.The RSC-164 allows software to adjust the speed of off-chip memory access. This allows using fast memory forperformance needs or (if feasible) slower memory for cost savings. The off-chip memory access time can bestretched using wait states defined by the BANK register, and the software can dynamically change the wait statevalue depending on the particular memory or I/O peripheral.There is minimal stack space on chip. The stack is required for interrupts and allows a very limited number ofnested calls. Programmers are encouraged to write inline code instead of making extensive subroutine calls. Theuse of macros simplifies generation of inline code. Sensory’s technology code makes extensive use of a softwarestack to allow more deeply nested calls. Macros using this software stack are accessible to developers.32K x 832K x 8HIGH [8000h-FFFFh]LOW [0000h-7FFFh]INTERNAL ROM-XMH-XMLmovc (Read Access)MAPPED RAM BANKREGISTER SPACE0C0h0E0h100hmov000hSPECIAL FUNCTIONREGISTERS1BFhOFF-CHIPADDRESS SPACE64K x 8 Code Spacemovc (Write Access)64K x 8 Data Spacemovx-RDC-WRC-RDD-WRDSTACK SPACE(Reserved)Mapped toRAM BankFigure 4 -- Memory Map
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`• As outputs, these pins can source or sink 4 mA with a voltage drop of < 0.5V.
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`• As inputs, VIL < 0.75V for all VDD from 3.5 to 5.0V. VIH > 2.5V over the same range.All I/O pins are diode clamped to VDD and ground, and are capable of sinking up to 200 mA if VDD is exceeded.In addition to providing general purpose I/O, port 0 bit P0.0 can serve as an interrupt input (using IMR and IRQregisters).
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`RSC-164/RSC-164iDATA BOOK 6From the Interactive Speech™ Line of Products6. General Purpose I/OThe RSC-164 has 16 general purpose I/O pins (P0.0-P0.7, P1.0-P1.7). Each pin can be programmed as an inputwith weak pull-up (~200KW equivalent device); input with strong pull-up (~10KW equivalent device); inputwithout pull-up, or as an output. This is accomplished by having 32 bits of configuration registers for the I/O pins(Port Control Register A and Port Control Register B for ports 0 and 1).After reset, all of the I/O pins are set to be inputs with weak pull-ups. Designers may make use of this start-upfeature to assure enabling or disabling of particular functions controlled by I/O pins.
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`Latch #1
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`Address
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`n X2n2ndecoded outputsn address inputsdevice select8 I/O bits
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products7It is straightforward to add more I/O capability to the RSC-164 devices using simple logic chips. If a large number ofoutput pins is required for a design, an address decoder canbe used to select from a number of latches as shown inFigure 5.In applications using external memories at least two (andtypically more) of these I/O lines will be used for bankswitching. Some of Sensory’s Library Functions makespecific assumptions about the configuration and operationof particular I/O pins. For example, all code space bankingsystems use P1.6 and P1.7 for controlling the -XML and -XMH signals. Typically some of the remaining pins onport1 are used for selecting externally banked code spaceROM. This may be done by connecting port pins toAddress bit 16 and higher pins of large memory devices(see Figure 3, page 4). Thus, typically Port 1 is used formemory control and Port 0 is used for general I/Ofunctions such as keyboard scanning.Two additional I/O lines (Port 0, bits 6 and 7) are alsoneeded for designs requiring full AGC control of thepreamplifier. However, many applications will be able touse the simpler, fixed-gain preamplifier described on page14, which does not use these I/O lines.
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`8 Lines
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`Figure 5 -- I/O Expansion
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`• Positive edge on Port 0, bit 0
`• Overflow of Timer 1
`• Overflow of Timer 2
`• Sensory Reserved functions
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`RSC-164/RSC-164iDATA BOOK 8From the Interactive Speech™ Line of Products7. InterruptsThe RSC-164 allows for five interrupt sources, as selected by software. Each has its own mask bit and request bit inthe IMR and IRQ registers respectively. The global interrupt enable flag, which enables or disables all interrupts,is located in the FLAGS registers. Bit assignments for the IMR and IRQ registers are listed on page 38. Thefollowing events can generate interrupts:
`• Completion of PWM sample periodIf an IRQ bit is set high and the corresponding IMR bit is set high and the global interrupt enable bit is set high, aninterrupt will occur. Interrupts cannot be nested. The flags register is copied to a holding register and then theglobal interrupt enable is cleared, preventing subsequent interrupts until the IRET instruction is executed. TheIRET instruction will restore the flags register from the holding register.If the corresponding mask register bit is clear, the IRQ bit will not cause an interrupt. However, it can be polled byreading the IRQ register. IRQ bits can be cleared by writing a 0 to the corresponding bit at address 0FEh (the IRQregister). IRQ bits can not be set by writing to 0FEh. Writing a one is a no-op.The IRQ bits must be cleared within the interrupt handler by an explicit write to the IRQ register rather than by animplicit interrupt acknowledge.Important: clear interrupts this way:movIRQ, #BITMASK; rightnot this way:andIRQ, #BITMASK; wrongThe ‘and’ instruction is not atomic, it is a read-modify-write. If an interrupt occurs during an ‘and IRQ’ operationthe interrupt will be cleared before it is seen, possibly disabling the interrupt until the system is reset.Because you cannot set bits in the IRQ register, a ‘mov IRQ’ is a save, effective, and atomic way to clear bits in theIRQ register. Use it the way you would use an ‘and’ in other registers.Note: if Port 0.0 (the external IRQ) is set as an output, the external IRQ flag will be set if the output is driven from0 to 1 under program control.For each interrupt, execution begins at a different code space address:Interrupt #0Address 4Interrupt #1Address 8Interrupt #2Address 0ChInterrupt #3Address 10hInterrupt #4Address 14hNormally the instruction at the interrupt address is a jump to an Interrupt Service Routine (ISR). This jump iscalled a vector. The vectors located at each of these addresses are typically in ROM. If the -XML signal is inactive(high), an internal ROM vector will be used. In this case if the vector address is in the range 0000h-7FFFh, thecode will vector to internal ROM. If the vector address is in the range 8000h-0FFFFh, the code will vector either tointernal ROM or external ROM depending on the setting of the -XMH signal.
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products9If the -XML signal is active (low) when an interrupt occurs, an external ROM vector will be used. If external ROMbanking is being employed, any of several different 64K banks could receive the interrupt, depending on which oneis selected in the banking scheme. This illustrates the importance of paying careful attention to all possibleinterrupt conditions when using code space bank switching.
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`RSC-164/RSC-164iDATA BOOK 10From the Interactive Speech™ Line of Products8. Reset and ClocksResetThe reset pin, -RESET, is an active low Schmitt trigger input. The reset pin is provided with hysteresis in order tofacilitate power-on reset generation via an RC network. Reset is held internally for 10 msec after the -RESET inputsignal is deasserted. This allows the oscillator to stabilize before enabling other processor subsystems.OscillatorsTwo independent oscillators in the RSC-164 provide a high-frequency clock and a 32kHz time-keeping clock. Theoscillator characteristics are as follows:Oscillator #1Pins XI1 and XO114.32 MHz (3.5V-5.0V)Oscillator #2Pins XI2 and XO232,768 Hz (3.5V-5.0V)Oscillator #1 works with an external crystal, a ceramic resonator or LC. Use of Oscillator #2 requires a crystal forprecise timekeeping.Both oscillators have an enable control. When disabled, the inverter is high-impedance, and a weak pull-up device(~100 K(cid:217)) holds the inverter output high. Both oscillators are controlled by the Clock Control Register (CPUregister 0E8h). By default, oscillator #1 is enabled by reset, while oscillator #2 is disabled by reset. The effect ofreset therefore requires that oscillator #1 be functional in all designs. The Clock Control Register also determinesinternal division of the CPU clock source (see below).Each oscillator has an associated timer that is fully programmable. The RSC-164 timers are described on page 11.Processor ClockThe RSC-164 uses a fully static core: the processor can be stopped (by removing the clock source) and restartedwithout causing a reset or losing contents of internal registers. Static operation is guaranteed from DC to 14.32MHz. The processor clock is selected from either the oscillator #1 output (gated by wake-up 10 mS delay) or theoscillator #2 output, based on bit 2 of the Clock Control Register. This bit is cleared by reset, which selectsoscillator #1. It is the responsibility of the firmware not to select oscillator #2 until both oscillators have beenenabled and stabilized.After source selection, the processor clock can be divided-down in order to limit power consumption. Bits 3 and 4of the Clock Control Register determine the divisor for the processor clock. Between zero and seven wait statesmust also be selected for the processor clock. Wait states are inserted on reads or writes to all addresses exceptRegister Space RAM.Sensory technology code must run with a processor clock of 14.32 MHz, a clock divisor of one, and one wait state.This creates internal RAM cycles of 70 nsec duration and internal ROM or external cycles of 140 nsec duration.Careful design of external decoding logic and close analysis of gate delays may allow operation with memorieshaving 120 nsec access times.
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`DATA BOOKRSC-164/RSC-164iFrom the Interactive Speech™ Line of Products119. T