HIGH SPEED SERIALIZED AT ATTACHMENT
`Serial ATA International Organization
`
`
`
`
`
`Serial ATA International Organization:
`
`Serial ATA Revision 2.6
`
`15-February-2007
`
`
`SATA-IO Board Members:
`
`Dell Computer Corporation
`Hewlett Packard Corporation
`Hitachi Global Storage Technologies, Inc.
`Intel Corporation
`Seagate Technology
`Vitesse Semiconductor Corporation
`
`
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`Serial ATA International Organization: Serial ATA Revision 2.6 specification ("Final Specification")
`is available for download at www.sata-io.org.
`
`
`SPECIFICATION DISCLAIMER
`IS PROVIDED TO YOU
`“AS
`IS” WITH NO WARRANTIES
`THIS SPECIFICATION
`WHATSOEVER,
`INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON-
`INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS
`SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF
`ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMNETATION OF INFORMATION
`IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH
`USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO
`YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY
`ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS.
`
`Copyright 2002-2007, Serial ATA International Organization. All rights reserved.
`
`For more information about Serial ATA, refer to the Serial ATA International Organization website
`at www.sata-io.org.
`
`All product names are trademarks, registered trademarks, or servicemarks of their respective
`owners.
`
`
`Serial ATA International Organization contact information:
`
`SATA-IO
`3855 SW 153rd Drive
`Beaverton, Oregon 97006 USA
`Tel: +1 503-619-0572
`Fax: +1 503-644-6708
`E-mail: admin@sata-io.org
`
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`4
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`2
`3
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`TABLE OF CONTENTS
`Revision History....................................................................................................................21
`1
`1.1
`Revision 2.5 (Ratification Date October 27, 2005) ........................................................ 21
`1.2
`Revision 2.6 (Ratification Date February 15, 2007) ...................................................... 21
`Scope....................................................................................................................................23
`Normative references ...........................................................................................................25
`3.1
`Approved references ..................................................................................................... 25
`3.2
`References under development .................................................................................... 27
`3.3
`Other references............................................................................................................ 27
`Definitions, abbreviations, and conventions .........................................................................29
`4.1
`Definitions and abbreviations ........................................................................................ 29
`4.1.1
`Active Port ............................................................................................................. 29
`4.1.2
`ATA (AT Attachment)............................................................................................. 29
`4.1.3
`ATAPI (AT Attachment Packet Interface) device .................................................. 29
`4.1.4
`BER (bit error rate) ................................................................................................ 29
`4.1.5
`bitrate..................................................................................................................... 29
`4.1.6
`bit synchronization ................................................................................................. 29
`4.1.7
`burst....................................................................................................................... 29
`4.1.8
`byte ........................................................................................................................ 29
`4.1.9
`character................................................................................................................ 29
`4.1.10
`character alignment ............................................................................................... 29
`4.1.11
`character slipping................................................................................................... 29
`4.1.12 ClickConnect.......................................................................................................... 30
`4.1.13
`code violation......................................................................................................... 30
`4.1.14
`comma character ................................................................................................... 30
`4.1.15
`comma sequence .................................................................................................. 30
`4.1.16
`command aborted.................................................................................................. 30
`4.1.17
`command completion............................................................................................. 30
`4.1.18
`command packet ................................................................................................... 30
`4.1.19
`concentrator........................................................................................................... 30
`4.1.20 Control Block registers........................................................................................... 31
`4.1.21
`control character .................................................................................................... 31
`4.1.22
`control port............................................................................................................. 31
`4.1.23
`control variable ...................................................................................................... 31
`4.1.24 CRC (Cyclic Redundancy Check) ......................................................................... 31
`4.1.25
`data character........................................................................................................ 31
`4.1.26
`data signal source.................................................................................................. 31
`4.1.27
`device..................................................................................................................... 31
`4.1.28
`device port ............................................................................................................. 31
`4.1.29 DCB (DC block) ..................................................................................................... 31
`4.1.30
`differential signal.................................................................................................... 31
`4.1.31 DJ (deterministic jitter – peak to peak) .................................................................. 32
`4.1.32 DMA (direct memory access) ................................................................................ 32
`4.1.33 Dword..................................................................................................................... 32
`4.1.34 Dword synchronization .......................................................................................... 32
`4.1.35 EMI (Electromagnetic Interference)....................................................................... 32
`4.1.36
`encoded character ................................................................................................. 32
`4.1.37
`endpoint device...................................................................................................... 32
`4.1.38
`elasticity buffer....................................................................................................... 32
`4.1.39
`eSATA.................................................................................................................... 32
`4.1.40
`Fbaud..................................................................................................................... 32
`4.1.41
`FER (frame error rate) ........................................................................................... 33
`4.1.42
`First-party DMA Data Phase.................................................................................. 33
`4.1.43
`First-party DMA access ......................................................................................... 33
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`FIS (Frame Information Structure)......................................................................... 33
`4.1.44
`frame...................................................................................................................... 33
`4.1.45
`4.1.46 Gen1 ...................................................................................................................... 33
`4.1.47 Gen1i ..................................................................................................................... 33
`4.1.48 Gen1m ................................................................................................................... 33
`4.1.49 Gen1x .................................................................................................................... 33
`4.1.50 Gen2 ...................................................................................................................... 33
`4.1.51 Gen2i ..................................................................................................................... 33
`4.1.52 Gen2m ................................................................................................................... 33
`4.1.53 Gen2x .................................................................................................................... 34
`4.1.54 HBA (Host Bus Adapter)........................................................................................ 34
`4.1.55 HBWS (High Bandwidth Scope) ............................................................................ 34
`4.1.56 HFTP (High Frequency Test Pattern).................................................................... 34
`4.1.57
`hot plug .................................................................................................................. 34
`4.1.58
`host port................................................................................................................. 34
`4.1.59
`inactive port ........................................................................................................... 34
`4.1.60
`interrupt pending.................................................................................................... 34
`4.1.61
`ISI (inter-symbol interference) ............................................................................... 34
`4.1.62
`JMD (jitter measuring device)................................................................................ 35
`4.1.63
`junk ........................................................................................................................ 35
`4.1.64
`LBA (Logical Block Address) ................................................................................. 35
`4.1.65
`LBP (lone bit pattern)............................................................................................. 35
`4.1.66
`LED (Light Emitting Diode) .................................................................................... 35
`4.1.67
`legacy mode .......................................................................................................... 35
`4.1.68
`legal character ....................................................................................................... 35
`4.1.69
`LFSR (Linear Feedback Shift Register)................................................................. 35
`4.1.70
`LFTP (low frequency test pattern) ......................................................................... 35
`4.1.71
`LL (laboratory load)................................................................................................ 35
`4.1.72
`LSS (laboratory sourced signal or lab-sourced signal).......................................... 35
`4.1.73 MFTP (mid frequency test pattern)........................................................................ 35
`4.1.74 OOB (Out-of-Band signaling) ................................................................................ 36
`4.1.75 OS-aware hot plug................................................................................................. 36
`4.1.76 OS-aware hot removal........................................................................................... 36
`4.1.77 Phy offline .............................................................................................................. 36
`4.1.78 PIO (programmed input/output)............................................................................. 36
`4.1.79
`port address........................................................................................................... 36
`4.1.80 PRD (Physical Region Descriptor) ........................................................................ 36
`4.1.81
`primitive.................................................................................................................. 36
`4.1.82
`protocol-based port selection ................................................................................ 36
`4.1.83
`quiescent power condition ..................................................................................... 36
`4.1.84 RJ (random jitter) ................................................................................................... 37
`4.1.85
`sector ..................................................................................................................... 37
`4.1.86 SEMB (Serial ATA Enclosure Management Bridge) ............................................. 37
`4.1.87 SEP (Storage Enclosure Processor) ..................................................................... 37
`4.1.88 Shadow Register Block registers........................................................................... 37
`4.1.89
`side-band port selection......................................................................................... 37
`4.1.90 SMART .................................................................................................................. 37
`4.1.91 SSC (spread spectrum clocking) ........................................................................... 37
`4.1.92
`surprise hot plug .................................................................................................... 37
`4.1.93
`surprise hot removal .............................................................................................. 37
`4.1.94 SYNC Escape........................................................................................................ 37
`4.1.95
`TDR (time domain reflectometer) .......................................................................... 38
`4.1.96
`TIA (timing interval analyzer)................................................................................. 38
`4.1.97
`TJ (total jitter)......................................................................................................... 38
`4.1.98 UI (unit interval) ..................................................................................................... 38
`4.1.99
`unrecoverable error ............................................................................................... 38
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`4.1.100 UUT (unit under test) ............................................................................................. 38
`4.1.101 VNA (vector network analyzer).............................................................................. 38
`4.1.102 warm plug .............................................................................................................. 38
`4.1.103 word ....................................................................................................................... 38
`4.1.104 xSATA.................................................................................................................... 38
`4.1.105 zero crossing ......................................................................................................... 38
`4.2
`Conventions................................................................................................................... 39
`4.2.1
`Precedence............................................................................................................ 39
`4.2.2
`Keywords ............................................................................................................... 39
`4.2.3
`Numbering ............................................................................................................. 40
`4.2.4
`Dimensions ............................................................................................................ 40
`4.2.5
`Signal conventions................................................................................................. 40
`4.2.6
`State machine conventions ................................................................................... 41
`4.2.7
`Byte, word and Dword Relationships..................................................................... 41
`General overview..................................................................................................................43
`5.1
`Architecture.................................................................................................................... 44
`5.2
`Usage Models................................................................................................................ 45
`5.2.1
`Internal 1 meter Cabled Host to Device................................................................. 48
`5.2.2
`Short Backplane to Device .................................................................................... 49
`5.2.3
`Long Backplane to Device..................................................................................... 49
`5.2.4
`Internal 4-lane Cabled Disk Arrays........................................................................ 50
`5.2.5
`System-to-System Interconnects – Data Center Applications (xSATA)................ 52
`5.2.6
`System-to-System Interconnects – External Desktop Applications (eSATA)........ 54
`5.2.7
`Proprietary Serial ATA Disk Arrays ....................................................................... 55
`5.2.8
`Serial ATA and SAS .............................................................................................. 55
`5.2.9
`Potential External SATA Incompatibility Issues..................................................... 55
`5.2.10 Mobile Applications................................................................................................ 56
`5.2.11 Port Multiplier Example Applications ..................................................................... 56
`Cables and Connectors ........................................................................................................61
`6.1
`Internal cables and connectors...................................................................................... 61
`6.1.1
`Internal Single Lane Description............................................................................ 61
`6.1.2
`Connector locations ............................................................................................... 64
`6.1.3
`Mating interfaces ................................................................................................... 73
`6.1.4
`Signal cable receptacle connector......................................................................... 77
`6.1.5
`Signal host plug connector .................................................................................... 79
`6.1.6
`Backplane connector ............................................................................................. 82
`6.1.7
`Power cable receptacle connector ........................................................................ 85
`6.1.8
`Internal single lane cable....................................................................................... 87
`6.1.9
`Connector labeling................................................................................................. 88
`6.1.10 Connector and cable assembly requirements and test procedures ...................... 88
`6.1.11
`Internal Multilane cables........................................................................................ 92
`6.1.12 Mini SATA Internal Multilane ................................................................................. 98
`6.2
`Internal Micro SATA Connector for 1.8” HDD ............................................................. 105
`6.2.1
`Usage model........................................................................................................ 105
`6.2.2
`General description.............................................................................................. 105
`6.2.3
`Connector location............................................................................................... 105
`6.2.4
`Mating interfaces ................................................................................................. 108
`6.3
`Internal Slimline cables and connectors...................................................................... 114
`6.3.1
`Usage Models...................................................................................................... 114
`6.3.2
`General description.............................................................................................. 115
`6.3.3
`Connector location and keep out zones .............................................................. 115
`6.3.4
`Mating interfaces ................................................................................................. 118
`6.3.5
`Backplane connector configuration and blind-mating tolerance.......................... 126
`6.3.6
`Connector labeling............................................................................................... 127
`6.3.7
`Connector and cable assembly requirements and test procedures .................... 127
`6.4
`External cables and connectors .................................................................................. 128
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`External Single Lane............................................................................................ 128
`6.4.1
`External Multilane ................................................................................................ 138
`6.4.2
`Mini SATA External Multilane .............................................................................. 142
`6.4.3
`6.5
`Cable and Connector Electrical Specifications............................................................ 145
`6.5.1
`Serial ATA Cable ................................................................................................. 146
`6.5.2
`Cable/Connector Test Methodology.................................................................... 147
`6.6
`Power Segment Pin P11 Definition (Optional) ............................................................ 155
`6.6.1
`Device Activity Signal .......................................................................................... 156
`6.6.2
`Staggered Spin-up Disable Control ..................................................................... 158
`6.7
`Precharge and Device Presence Detection ................................................................ 160
`6.7.1
`Device Requirements .......................................................................................... 160
`6.7.2
`Receptacle Precharge (Informative).................................................................... 160
`6.7.3
`Presence Detection (Informative) ........................................................................ 161
`Phy Layer............................................................................................................................163
`7.1
`Descriptions of Phy Electrical Specifications............................................................... 163
`7.1.1
`List of Services .................................................................................................... 163
`7.1.2
`Low Level Electronics Block Diagrams (Informative) .......................................... 164
`7.1.3
`Compliance Testing............................................................................................. 171
`7.1.4
`Link Performance................................................................................................. 172
`7.2
`Electrical Specifications............................................................................................... 172
`7.2.1
`Physical Layer Requirements Tables .................................................................. 173
`7.2.2
`Phy Layer Requirements Details ......................................................................... 180
`7.2.3
`Loopback ............................................................................................................. 195
`7.2.4
`Test Pattern Requirements.................................................................................. 197
`7.2.5
`Hot Plug Considerations...................................................................................... 211
`7.2.6
`Mated Pair Definition ........................................................................................... 214
`7.2.7
`Compliance Interconnect Channels (Gen1x, Gen2x).......................................... 215
`7.2.8
`Impedance Calibration (Optional)........................................................................ 217
`7.3
`Jitter ............................................................................................................................. 218
`7.3.1
`Definition.............................................................................................................. 218
`7.3.2
`Reference Clock Definition .................................................................................. 219
`7.3.3
`Spread Spectrum Clocking.................................................................................. 219
`7.3.4
`Jitter Budget......................................................................................................... 221
`7.3.5
`Jitter Formulas without SSC (Informative)........................................................... 221
`7.4 Measurements ............................................................................................................. 223
`7.4.1
`Frame Error Rate Testing.................................................................................... 223
`7.4.2
`Measurement of Differential Voltage Amplitudes ................................................ 226
`7.4.3
`Rise and Fall Times............................................................................................. 236
`7.4.4
`Transmitter Amplitude.......................................................................................... 238
`7.4.5
`Receive Amplitude............................................................................................... 239
`7.4.6
`Long Term Frequency Accuracy ......................................................................... 242
`7.4.7
`Jitter Measurements ............................................................................................ 242
`7.4.8
`Transmit Jitter ...................................................................................................... 245
`7.4.9
`Receiver Tolerance.............................................................................................. 246
`7.4.10 Return Loss and Impedance Balance ................................................................. 248
`7.4.11 SSC Profile .......................................................................................................... 252
`7.4.12
`Intra-Pair Skew .................................................................................................... 252
`7.4.13 Sequencing Transient Voltage ............................................................................ 254
`7.4.14 AC Coupling Capacitor ........................................................................................ 255
`7.4.15
`TX Amplitude Imbalance...................................................................................... 255
`7.4.16
`TX Rise/Fall Imbalance........................................................................................ 255
`7.4.17
`TX AC Common Mode Voltage ........................................................................... 256
`7.4.18 OOB Common Mode Delta.................................................................................. 256
`7.4.19 OOB Differential Delta ......................................................................................... 256
`7.4.20 Squelch Detector Tests ....................................................................................... 257
`7.4.21 OOB Signaling Tests ........................................................................................... 258
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`8
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`TDR Differential Impedance (Gen1i / Gen1m) .................................................... 259
`7.4.22
`TDR Single-Ended Impedance (Gen1i / Gen1m)................................................ 260
`7.4.23
`7.4.24 DC Coupled Common Mode Voltage (Gen1i / Gen1m) ...................................... 261
`7.4.25 AC Coupled Common Mode Voltage (Gen1i / Gen1m) ...................................... 261
`7.5
`Interface States............................................................................................................ 262
`7.5.1
`Out Of Band Signaling......................................................................................... 262
`7.5.2
`Idle Bus Condition................................................................................................ 270
`7.6
`Elasticity Buffer Management...................................................................................... 270
`OOB and Phy Power States ...............................................................................................273
`8.1
`Interface Power States ................................................................................................ 273
`8.2
`Asynchronous Signal Recovery (Optional).................................................................. 273
`8.2.1
`Unsolicited COMINIT Usage (Informative) .......................................................... 273
`8.3
`OOB and Signature FIS return (Informative)............................................................... 274
`8.4
`Power-On Sequence State Machine ........................................................................... 274
`8.4.1
`Host Phy Initialization State Machine .................................................................. 274
`8.4.2
`Device Phy Initialization State Machine............................................................... 279
`8.4.3
`Speed Negotiation ............................................................................................... 282
`Link Layer ...........................................................................................................................289
`9.1
`Overview...................................................................................................................... 289
`9.1.1
`Frame Transmission............................................................................................ 289
`9.1.2
`Frame Reception ................................................................................................. 289
`9.2
`Encoding Method......................................................................................................... 289
`9.2.1
`Notation and Conventions ................................................................................... 290
`9.2.2
`Character Code ................................................................................................... 291
`9.2.3
`Transmission Summary....................................................................................... 299
`9.2.4
`Rec