aA
`
`106933869E
`
`(12)
`
`United States Patent
`Starr et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,933,869 Bl
`Aug. 23, 2005
`
`(54)
`
`(75)
`
`INTEGRATED CIRCUITS WITH
`TEMPERATURE-CHANGE AND
`THRESHOLD-VOLTAGE DRIFT
`COMPENSATION
`
`Inventors: Greg Starr, San Jose, CA (US); Samit
`Sengupta, San Jose, CA (US); Hugh
`SungKi O, Fremont, CA (US)
`
`OTHER PUBLICATIONS
`
`John G. Maneatis “Low-Jitter Process-Independent DLL
`and PLL Based on Self-Biased Techniques”, IEEE Journal
`of Solid-State Circuits, vol. 31, No. 11 (Nov. 1996) pp.
`1723-1732.
`Paul R. Gray et al. “Analysis and Design of Analog
`Integrated Circuits”, John Wiley & Sons, Inc. 1993, p. 329,
`no month.
`
`(73)
`
`Assignee: Altera Corporation, San Jose, CA
`(US)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`* cited by examiner
`
`Primary Examiner—Brian Young
`(74) Attorney, Agent, or Firm-—G. Victor Treyz
`
`(57)
`
`ABSTRACT
`
`Appl. No.: 10/802,590
`
`Filed:
`
`Mar. 17, 2004
`
`Tint, C07 eee ceceece tees eeeeeeeeeesseseeeeeeneess HO3M 1/10
`US. Ch.cece cee 341/120; 341/144
`Field of Search oo... 341/120, 118, 119,
`341/121, 122, 144, 155; 365/149, 189.07,
`365/190, 205, 207, 208
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`8/1989 Soneda cee 365/205
`4,858,195 A *
`w 365/149
`1/1999 Chan...
`5,859,794 A *
`
`..........-.. 365/208
`2/2000 Kopley et al.
`6,028,803 A *
`2/2001 MePartland ............ 365/189.05
`6,195,295 BL*
`6,462,986 BL* 10/2002 Bhan oo. eeeee 365/185.2
`
`Integrated circuits are stabilized by monitoring changes that
`affect circuit operation and by compensating for
`those
`changes using power supply adjustments. Changes in oper-
`ating temperature and threshold voltage changes may be
`measured, Difterential measurements may be made in which
`threshold voltages measured in continuously-biased moni-
`toring circuits are comparedto threshold voltages measured
`in intermittently-biased monitoring circuits. Temperature
`changes may be monitored using a temperature monitoring
`circuit based on an adjustable current source and a diode.
`Monitoring and compensation circuitry on the integrated
`circuits may use analog-to-digital and digital-to-analog con-
`verters controlled by a control unit to make temperature and
`threshold voltage measurements and corresponding com-
`pensating changes in power supply voltages.
`
`20 Claims, 13 Drawing Sheets
`
`38
`
`
`CMOS INTEGRATED CIRCUIT
`32
`
`
`34
`
` MONITORING
`
`AND COMPENSATION
`CIRCUITRY
`
`
`
`
`
`
`
`CIRCUIT A
`(E.G., LESS-
`SENSITIVE
`CIRCUITRY)
`
`
`
` CIRCUIT B
`
`(E.G., MORE
`SENSITIVE
`
`
`CIRCUITRY)
`
`
`
`INTEL 1002
`
`INTEL 1002
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 1 of 13
`
`US 6,933,869 B1
`
`
`
`FIG. 1
`
`TO LOWER VOLTAGES
`
`FIG. 2
`
`

`

`U.S. Patent
`
`Aug.23, 2005
`
`Sheet 2 of 13
`
`US 6,933,869 Bl
`
`28
`
`| AGE DRIFT
`OF Vip
`
`30
`
`FIG. 3
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 3 of 13
`
`US 6,933,869 B1
`
`Vcc
`
`Vss
`
`38
`
`38
`
`CMOS INTEGRATED CIRCUIT
`34
`
`39
`
`MONITORING
`AND COMPENSATION
`
`CIRCUITRY
`36 CIRCUIT B
`
`
`CIRCUIT A
`
`
`
`(E.G., LESS-
`SENSITIVE
`CIRCUITRY)
`
`Vcc
`
`Vss
`
`Vec'
`
`Vss
`
`36
`
`(E.G., MORE
`SENSITIVE
`CIRCUITRY)
`
`FIG. 4
`
`

`

`U.S. Patent
`
`Aug.23, 2005
`
`Sheet 4 of 13
`
`US 6,933,869 BI
`
`V
`
`Voc
`
`Vss
`
`0
`
`38
`
`42
`
`Vee
`
`Vcc - Vip
`
`44
`
`40
`
`Ves + Vin
`
`TIME (YEARS)
`
`10
`
`FIG. 5
`(PRIOR ART)
`
`

`

`U.S. Patent
`
`Aug.23, 2005
`
`Sheet 5 of 13
`
`US 6,933,869 B1
`
`V
`
`Vcc
`
`Vss
`
`0
`
`Voc’ = Veco t+ AVtn + AVtp
`
`46
`
`48
`
`Vec'- Vtp
`
`44
`
`40
`
`Vss + Vin
`
`10
`
`TIME (YEARS)
`
`FIG. 6
`
`

`

`72
`
`DETECTOR
`
`FILTER
`
`PHASE - FREQUENCY ul
`(
`LOOP
`[
`
` FREQUENCY
`DIVIDER (N)
`
`
`
`FREQUENCY
`
`DIVIDER (M)
`
`
`yusyed*S°
`
`S007‘¢z“BNY
`CTJO9WOUS
`Td698°E€6°9SN
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 7 of 13
`
`US 6,933,869 Bl
`
`
`
`FIG. 9
`
`

`

` ys
`
`86
`
`100
`
`ISS 106
`9
`
`410
`
`(
`THRESHOLD
`DIGITAL-TO
`NALOG-TO
`vor
`
`MONITORING|9g A “TO- CONTROL ANALOG
`
`
`
`CIRCUIT
`CIRCUIT
`CONVERTER
`CONVERTER
`
`quae‘SN
`
`
`S00z‘Ez“SN
`CIJO8PINS
`TH698°E€6°9SN
`
`
`
`
`
`
`98
`
`TEMPERATURE
`MONITORING
`CIRCUIT
`
`96
`
`104
`
`1
`118
`
`108
`
`112
`
`VCC-HIGH
`vO
`
`116
`
`114
`
`VREF
`
`90
`
`:
`
`
`
`ADDITIONAL
`MONITORING
`CIRCUITS
`
`92
`
`Vec'
`
`420
`
`ETC.)
`
`SENSITIVE
`CIRCUIT
`(E.G., VCO IN PLL
`OR VCO IN DLL,
`TC.
`
`36
`
`FIG. 10
`
`

`

`U.S. Patent
`
`Aug.23, 2005
`
`Sheet 9 of 13
`
`US 6,933,869 B1
`
`re
`
`122
`
`(i
`
`
`
`CONTINUOUSLY-BIASED
`THRESHOLD VOLTAGE
`MONITORING CIRCUIT
`
`
`
`
`
`INTERMITTENTLY-BIASED
`
`
`THRESHOLD VOLTAGE
`MONITORING CIRCUIT
`
`TO ADC
`
`124
`
`FIG. 11
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 10 of 13
`
`US 6,933,869 B1
`
`122
`
`fo
`
`128
`
`130
`
`TO ADC
`
`FIG. 12
`
`
`
`FIG. 13
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 11 of13
`
`US 6,933,869 Bl
`
`144
`
`y7 88
`
`T REF
`
`138
`142
`MONITOR
`OUTPUT
`
`aN
`140
`
`FIG. 14
`
`
`
`Vat Vi Vio Vi-2
`
`FIG. 15
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 12 of 13
`
`US 6,933,869 B1
`
`TIME
`
`FIG. 16
`
`
`
`TIME
`
`FIG. 17
`
`

`

`U.S. Patent
`
`Aug. 23, 2005
`
`Sheet 13 of13
`
`US 6,933,869 B1
`
`
`
`START CIRCUIT OPERATION
`(E.G., BAS CONTINUOUSLY-BIASED
`MONITORING CIRCUITS, ETC.)
`
`150
`
`152
`
`MEASURE TEMPERATURE
`
`MEASURE THRESHOLD
`VOLTAGES (E.G., MEASURE
`THRESHOLD VOLTAGES BY
`APPLYING BIAS TO INTERMITTENTLY-
`BIASED MONITORING CIRCUIT AND
`MAKING DIFFERENTIAL MEASUREMENTS)
`
`154
`CIRCUITS)
`
`COMPENSATE FOR TEMPERATURE
`VARIATIONS AND THRESHOLD VOLTAGE
`DRIFT (E.G., ADJUST POWER
`SUPPLY VOLTAGES FOR APPROPRIATE
`
`156
`
`FIG. 18
`
`

`

`US 6,933,869 BL
`
`1
`INTEGRATED CIRCUITS WITH
`TEMPERATURE-CHANGEAND
`THRESHOLD-VOLTAGE DRIFT
`COMPENSATION
`
`BACKGROUNDOF THE INVENTION
`
`This invention relates to integrated circuits, and more
`particularly, 10 ways in which to improve circuit perfor-
`mance by compensating for
`the effects of metal-oxide-
`semiconductor (MOS)transistor threshold voltage drift and
`temperature changes.
`Integrated circuits based on complementary metal-oxide-
`semiconductor (CMOS) transistor technology are widely
`used in modern electronic systems. The proper performance
`of CMOSintegratedcircuits is often critically dependent on
`the stable operation ofits MOStransistors, Even relatively
`small changes in transistor performance can have a strong
`impact on the operation ofsensitive circuitry on a high-
`performance CMOSchip.
`The operation of a transistor can be significantly affected
`byvariations in temperature and changes in the transistor’s
`threshold voltage due to aging. If a transistor’s threshold
`voltage increases even slightly,
`the transistor’s ability to
`drive current may be reduced sufficiently that a sensitive
`digital logic circuit in whichthe transistor is operating will
`slow downsubstantially or no longer function properly and
`the gain ofcertain sensitive analog circuits may be degraded.
`This can disrupt the proper functioning of the entire inte-
`grated circuit.
`CMOSintegratedcircuits contain p-channel (PMOS)and
`n-channel (NMOS)transistors. The threshold voltage of a
`PMOStransistor can change over time due to negative bias
`temperature instability (NBTI). Negative bias temperature
`instability arises when MOSdevices are exposed to low gate
`bias voltages under
`elevated operating temperatures.
`Threshold voltage
`increases due
`to NBTI may
`be
`significant—i.c., on the order of tens of millivolts over the
`lifetime of a circuit. The threshold voltages in NMOS
`transistors may also increase over time due to the accumu-
`lation of gate-oxide charge from hot carrier effects.
`It is an object ofthe present invention to provide ways in
`which to overcome variations in transistor performance due
`to changes in operating temperature and shifts in threshold
`voltages.
`
`SUMMARY OF THE INVENTION
`
`In accordance with the present invention, integrated cir-
`cuils are provided with monitoring and compensation cir-
`cullry for measuring changes in temperature andtransistor
`threshold voltages that may affect circuit performance.
`Powersupply adjustments may be made by the monitoring
`and compensationcircuilry to compensate for the effects of
`the measured changes. For example,
`the monitoring and
`compensation circuitry can boost the power supply voltage
`lo Sensitive circuits Whenever temperatures rise or threshold
`voltages increase. The increase in power supply voltage can
`réduce or eliminate the negative impact of changes in
`temperature and threshold vollage.
`Measurements of changes in threshold voltage may be
`made by comparing the measured threshold voltage ofa
`continuously-biased transistor circuit
`to the measured
`threshold voltage of an intermittently-biased transistor cir-
`cuit. Because the inlermittently-biased transistor circuit is
`not exposed to bias signals,
`the threshold voltage of this
`transistor will be relatively stable and can be used as an
`
`as
`
`10
`
`— an
`
`nNaD
`
`becS
`
`bsmn
`
`40
`
`wn an
`
`6
`
`2
`on-cireuit baseline measurement. The continuously-biased
`transistor circuit will exhibit significant
`threshold voltage
`drift. Accurate measurements of threshold voltage changes
`can be made using a differential measurement scheme in
`which the baseline measurements from the intermittently-
`biased circuit are subtracted from the threshold voltage
`measurements made on the continuously-biased circuil.
`Measurements of changes in temperature may be made
`using a temperature monitoring circuit based on an adjust-
`able current source and a diode.
`The monitoring and compensation circuitry on the inte-
`grated circuit may have multiplexer circuitry for switching
`between multiple monitoring circuits (¢.g., monitoring cir-
`cults for threshold voltage measurements, temperature mea-
`surements, etc.). An analog-to-digital converter in the moni-
`toring and compensation circuitry may be used to make
`signal measurements on the monitoring circuils. A digital-
`to-analog converter and an associated output buller may be
`used to provide sensitive circuits on the integrated circuit
`with adjusted powersupply signals. A control circuit in the
`moniloring and compensation circuitry may control opera-
`tion of the monitoring circuits, multiplexer, and analog-to-
`digital and digital-to-analog converters.
`Further features of the invention, its nature and various
`advantages will be more apparent from the accompanying
`drawings and the following detailed description of the
`preferred embodiments.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`is a cross-sectional side view of an illusirative
`I
`FIG.
`p-channel metal-oxide-semiconductor transistor.
`fIG. 2 is a circuit diagram of the p-channel metal-oxide-
`semiconductor transistor of FIG. 1.
`FIG. 3 is a circuit diagram of the current-vollage charac-
`teristic for an illustrative metal-oxide-semiconductor tran-
`sistor showing the effects of age-induced threshold-vollage
`drift.
`FIG. 4 is a diagram ofan illustrative integrated circuit
`having monitoring and compensation circuitry for stabiliz-
`ing operation in accordance with the present invention.
`FIG. 5 is
`a graph showing bow PMOS and NMOS
`threshold voltages drift with age in conventional CMOS
`circuits.
`
`FIG. 6 is a graph showing how monitoring and compen-
`sation circuitry may be used to compensate forthe effects of
`thresholdvoltage drift in accordance with the present inven-
`tion.
`
`FIG. 7 is a schematic circuit diagram of an illustrative
`CMOS phase-locked-loop circuit
`that may be stabilized
`using the monitoring and compensation circuitry of the
`present invenuon.
`FIG. § is a schematic circuit diagram of an illustrative
`four-stage vollage-controlled oscillator for a phase-locked
`loop of the type shown in FIG. 7.
`FIG. 9 shows illustrative circuitry that may be used in
`each stage of a voltage-controlled oscillator of the type
`shown tn FIG. 8.
`
`a diagram of illustrative monitoring and
`FIG. 10 is
`compensating, circuitry that may be used to automatically
`adjust the power supply vollage of sensitive circuitry en an
`integrated circuit in accordance with the present invention.
`FIG. LL is a diagram of anillustrative differential mom-
`toring circuit arrangement that may be used in a monitoring
`and compensation circuit
`in accordance with the present
`invenuon.
`
`

`

`US 6,933,869 BI
`
`3
`FIG. 12 is a circuit diagram ofan illustrative conunu-
`ously-biased circuit
`for a monitoring and compensation
`circuit in accordance with the present invention.
`FIG. 13 is a circuit diagram of an illustrative intermit-
`tently-biased circuit for a monitoring and compensation
`circuit in accordance with the present invention.
`FIG. 14 is an illustrative temperature-monitoring circull
`for a monitoring and compensation circuit
`in accordance
`with the present invention.
`FIG. 15 is a graph showing howthe circuit of FIG. 14 may
`be used in measuring the operating temperature of a CMOS
`integrated circuit in accordance with the present invention.
`FIG. 16 is a graph showing howthe operating temperature
`of an illustrative CMOS integrated circuit might vary as a
`function of time.
`FIG. 17 is a graph showing how a monitoring and
`compensation circuit may adjust the positive power supply
`voltage for a sensitive circuit in real time to compensate for
`temperature changes of the type shown in FIG. 16 in
`accordance with the present invention.
`FIG, 18 is a flow chart of illustrative steps involved in
`using monitoring and compensation circuitry to compensate
`for the effects of temperature changes andthresholdvoltage
`drift on the operation ofcircuitry on a CMOSintegrated
`circuit in accordance with the present invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`
`The present invention relates to complementary metal-
`oxide-semiconductor (CMOS)
`integrated circuits baving
`n-channel metal-oxide-semiconductor (NMOS) transistors
`
`and p-channel metal-oxide-semiconductor (PMOS)transis-
`tors. The inventionalso relates to circuitry and methods for
`ensuring proper operation of CMOSintegrated circuits that
`are exposed to changes in temperature and changes in
`transistor threshold voltages due to aging.
`A cross-section of a typical PMOS transistor 10 on a
`CMOSintegratedcircuit is shown in FIG. L. Transistor 10
`may be formedin an n-type well 12 on asilicon substrate 14.
`IIcavily-doped p+ regions are used to form a source 16 (S)
`and drain 18 (D). The transistor is controlled by applying
`signals to gate 20 (G). Gate 20 has a gate conductor 22,
`whichis separated from an underlying channel region 24 in
`well 12 by a gate oxide 26. A heavily-doped n+ region 28 is
`used to form a “substrate” or bulk contact (SUB).
`Transistors such as transistor LO may be used in a varicly
`of different circuits on a CMOS integrated circuit. For
`example, transistors such as transistor 10 may be used to
`form digital and analog circuitry including NOR gates,
`inverters, and other logic gates, voltage and current sources,
`buffers, cte.
`Although the precise operating environment of a given
`PMOStransistors depends on the application lor whichthat
`PMOStransistor is being used, PMOStransistors are fre-
`quently used in configurations in which the source andgate
`terminals are exposed to relatively low voltages and the
`drain and SUBterminals have higher voltages. Por example,
`as shown in the diagram of FIG.
`L and the corresponding
`circuit-schematic version oftransistor LO that
`is shown in
`FIG. 2, the drain and substrate terminals oftransistor 10 may
`be connected to a positive power supply voltage of Vec,
`whereas the source and gale terminals may be connectedto
`lower voltages in the remainder of the circui.
`Underthese operating conditions, the threshold voltage of
`transistor 10 will drift over
`lime due to the effects of
`negative bias temperature instability (NBTT). Whena circuit
`
`10
`
`in
`
`20
`
`hwan
`
`a?an
`
`40
`
`n a
`
`60
`
`4
`is usedfor a relatively long period of time (e.g., 10 years or
`more) or when the temperature and bias-inducedstress on a
`transistor is particularly high,
`the threshold voltage of a
`PMOStransistor may increase by tens of millivolts due to
`NBTIL. Similar, though generally less severe, changes to the
`threshold voltage of NMOStransistors occur due to charge
`accumulation in gate oxide layer 26 from hot electrons.
`The impact ofthreshold voltage drift in a typical PMOS
`transistor is shownin the transistor current-voltage charac-
`teristic of FIG. 3. Initially,
`the source-drain current of a
`PMOStransistor may follow curve 28. As the transistor
`ages,its thresholdvoltage V,,, will Increase due to NBTL For
`example, after several years of operation,
`the threshold
`voltage of the transistor may be 10 mV higher. This makes
`the transistor harder to turn on, so that the current-voltage
`characteristic of the transistor follows curve 30. Similar
`reductions in the current are exhibited when the operating
`temperature of a transistor increases or when an NMOS
`transistor experiences gate-oxide charge accumulation due
`to aging.
`A CMOScircuit may need to operate in a system for a
`long period of time (c.g., LO years or more) and/or at an
`elevated temperature (e.g., 100 C or more), Under these
`conditions, changesin transistor behavior can be significant.
`Particularly in CMOScircuits that contain sensitive circuitry
`(such as high-performance analog and/or digital circuits),
`transistor performance must be stabilized if reliable high-
`performance operation is desired.
`In accordance with the present invention, a CMOSinte-
`grated circuit is provided that operates properly even when
`subjected to temperature changes or changes in the threshold
`voltages ofits transistors. As shown in FIG. 4, a CMOS
`integrated circuit 32 in accordance with the present inven-
`tion may have monitoring and compensation circuitry 34.
`Cireuitry 34 may be used to measure changes in operating
`temperature andshifts in threshold voltage. These measure-
`ments are used by circuitry 34 to produce adjusted power
`supply voltages. The adjusted power supply voltages com-
`pensate for the effects of temperature changes andthreshold
`voltage shifts and thereby help to ensure that the circuitry of
`integrated circuit 32 workssatisfactorily.
`A circuit such as integrated circuit 32 may be supplicd
`with power supply voltages such as a positive powersupply
`voltage of Vee (e.g., 1.2 V) and a ground voltage of Vss
`(e.g., OV) using pins 38. These are merelyillustrative power
`supply vollages that may be used by CMOS integrated
`circuit 32. In general, there may be any suitable number of
`different powersupply voltages providedto circuit 32 at any
`suitable voltages levels. Moreover, power supply voltages
`may be generated on circuit 32 using on-chip circuitry such
`as charge pumpcircuitry if desired.
`In the following dis-
`cussion, some circuits are shown as being powered by power
`supply voltages of Vee and Vss fer clarity.
`In general,
`however, any suitable power supply voltages may be used
`with the circuitry of CMOS integrated circuit 32.
`As shown in FIG. 4, a CMOS circuit such as CMOS
`integrated circuit 32 may have multiple sub-circuits 36 (¢.g.,
`circuil Aandcircuil B). Not all of the circuitry on integrated
`circuit 32 will be equally sensitive to temperature and
`threshold-voltage changes. Some circuits (e.g, circuit A)
`may contain relatively less-sensitive circuitry such as low-
`speed (DC)logic. Other circuits (e.g., circuit B) may contain
`sensitive high-performance digital or analog circuits such as
`phase-locked loops, delay-locked loops, input-output bull-
`ers, etc. The proper operationof such sensitive circuits may
`dependcritically on the voliages usedto drive the circuit, the
`
`

`

`US 6,933,869 BI
`
`~>
`
`
`
`operating temperature of the circuit, and the threshold volt-
`ages associated with the cireuit’s transistors.
`The monitoring and compensation circuitry 34 can com-
`pensate for changes in temperature and threshold voltage by
`changing the power supply voltages used byall or substan-
`tially all of the circuitry on integrated circuit 32. If desired,
`the amount of resources required for monitoring and com-
`pensation circuitry 34 may be minimized by supplying
`adjusted power supply voltages to only sensitive circuits
`such as circuit B. With one suitable approach, the ground
`voltage Vss is left unchangedandthe positive powersupply
`voltage is adjusted to produce an adjusted power supply
`voltage Vec' that compensates for temperature changes and
`threshold-voltage drift effects.
`If desired, other power supply voltages can be adjustedto
`stabilize circuit 32. For example, Vss could be adjusted
`while Vee is held constant, Vss and Vee could both be
`adjusted, the voltages used to bias substrate terminals such
`as the SUB terminal of FIGS. 1 and 2 could be adjusted
`(alone or in combination with other power supply voltage
`adjustments), or other circuit voltages could be adjusted.
`‘The invention will be discussed primarily in the context of
`monitoring and compensation circuitry that produces an
`adjusted positive power supply voltage Vec'
`to stabilize
`operation of the circuit 32, but this is merely illustrative.
`The effects of NBTI andgate-oxide charge accumulation
`in PMOS and NMOStransistors on a conventional CMOS
`integrated circuit are shown in FIG. 5. The graph of FIG. 5
`contains a line 38 that represents the conventional (unad-
`jusied) positive power supply voltage Vee. Because no
`adjustments are made to Vee in a conventional circuit, Vee
`is a constant, andthe line 38 is flat. Over time, the threshold
`voltage Vin of the NMOStransistors on the circuit increases,
`as shownby line 40. The threshold voltage Vtp of the PMOS
`transistors on the circuil also increases, as shown byline 42.
`As the threshold voltages Vip and Vin drift higher over
`time, the operating voltage range 44 for circuits powered by
`Vee and Vss, which is represented by the distance between
`lines 40 and42, decreases. When the operating voltage range
`44 is too small, sensitive circuitry on the CMOS device no
`longer operates satisfactorily. As a result, the useful life of
`a conventional CMOSintegrated circuit may be shorter than
`desired. Similar changes in the operating voltage range 44
`occur when a conventional integrated circuit is operated at
`elevated temperatures, which may undesirably restrict
`the
`allowed operating temperatures for such circuits.
`When the monitoring and compensation circuitry 34 of a
`CMOSintegrated circuit 32 in accordance with the present
`inventionis used, the changes in temperature and/or thresh-
`old voltage drift are detected and suitable compensating
`adjustments are made to appropriate powersupplyvoltages.
`In particular, when CMOS integrated circuit 32 experiences
`increases in Vin and Vip due to NBTT and gate-oxide charge
`accumulation effects, monitoring and compensation cir-
`cuitry 34 may produce a positive powersupply vollage Vee"
`that compensates for these inercases, as shown in FIG. 6.
`As shownby line 46 in FIG. 6, the value of Veco’ may be
`increased over Vee by an amount equal to the measured
`increase in the NMOS threshold vollage (AVtn) plus the
`measured increase in the PMOSthreshold voltage (AVip).
`The resulting operating range 44, which is given by the
`distance between the Line 48 (Vec’-Vip) and Hine 40
`(Vss+Vin), remains constant as a function of time, rather
`than decreasing with age as with the conventional arrange-
`
`ment of FIG. §. Changes
`incircuit operation due to increases
`(or decreases)
`in operating temperature T may also be
`compensated by increasing (or decreasing) Vee’. By provid-
`
`10
`
`br a
`
`wan
`
`40
`
`SO
`
`“an mn
`
`oO
`
`6
`ing the sensitive circuits on CMOSintegratedcircuit 32 such
`as sensitive circuit B of FIG. 4 with the adjusted value of
`power supply voltage Vec’, proper operation of the sensitive
`circuits and therefore proper operation of the entire inte-
`grated circuit 32 may be ensured.
`Providing the adjusted value of power supply voltage Vcc’
`also helps the sensitive circuits by providing a level of
`isolation from the integrated circuit’s main power supply.
`Conventional integrated circuits sometimes containcircuitry
`for performing on-chip power supply sub-regulation, which
`helps to reduce noise effects. With the present invention, the
`adjusted value of power supply voltage Vcc’ may be pro-
`vided using a sub-regulation arrangement. The additional
`isolation provided by this type of arrangement may helpto
`reduce power supply noise effects in addition to ensuring
`proper operation of sensitive circuits due to changes in
`temperature and threshold vollage.
`In general, any suitable MOS integrated circuit may be
`stabilized using monitoring and compensationcircuitry such
`as monitoring and compensationcircuitry 34 of FIG, 4. For
`example, circuits containing high-speed digital signal paths
`can be stabilized to ensure critical timing constraints are
`satisfied. Circuits containing high-performance analog cir-
`cuits can also be stabilized to ensure accurate operation.
`An example of a circuit that may benefit from the stabi-
`lization provided by monitoring and compensationcircuitry
`34 is a phase-locked-loop circuit. Phase-locked loops may
`be usedin a variety of applications, including clock anddata
`recovery and other high-frequency operations. Another
`example of a circuit that may benefit from the stabilization
`provided by monitoring and compensationcircuitry 34 is a
`delay-locked loop.
`Anillustrative phase-locked-loop circuit 50 that may be
`used on integrated circuit 32 is shown in FIG. 7. Phase-
`locked-loop circuit 50 has an input 52 and an output 54. A
`frequency divider such as frequency divider 56 (e.g., a
`counter) may be usedto reduce the input frequency [yy(e-g.,
`to f,/N). A frequencydivider such as frequency divider 58
`may, if desired, be usedto divide the feedback signal fo;
`from output 54 (e.g., to produce a divided-down feedback
`signal fyp-7/M). The divided-down input frequency [,,//N
`and feedback signal fo../M may be provided to inputs 60
`and 62 of phase-frequency detector 64. Phase-frequency
`detector 64 compares these signals and gencrates corre-
`sponding output signals on outputs 66. The phase-frequency
`detector 64 provides fvo output signals on its outputs 62.
`Whenthe signal on input 60 is ahead ofthe signal on input
`62, a first control signal onafirst output 66 is taken high and
`a second control signal on a second output 66 is taken low.
`When the signal on input 60is behindthe signal on input 62,
`the first control signal is taken low and the second control
`signal is taken high. The outputs provided by the phase-
`frequency detector therefore act as control signals for the
`rest of the phase-lockedloop. These contrel signals are used
`to adjust the frequency ofthe feedback signal produced by
`the voltage-controlled oscillator (VCO) 76 at output 54, so
`that fogr7/M matches f,,/N.
`The output signals from the phase-frequency detector 64
`are provided to charge pump 68. The charge pump 68
`produces output currents on outputs 70 that are proportional
`to the incoming control signals (.e.,
`the detector outpul
`signals). These currents are provided to loop filter 72. Loop
`filter 72 fillers the output signals from charge pump 68 to
`remove undesirable frequency components. Loop filter 72
`also converts the current-based signals on lines 70 into
`corresponding voltage-based signals. The resulting filtered
`vollage signals are provided over Lines 74 to voltage-
`
`

`

`US 6,933,869 B1
`
`7
`controlled oscillator 76. Voltage-controlled oscillator 76
`produces an output signal f,,,, whose frequencyis propor-
`tional to the voltages on lines 74. The output signals fromthe
`voltage-controlledoscillator 76 may be feedback to input 62
`of the phase/frequency detector 64 via frequency divider 58.
`Someportions of circuit 50 such as charge pump 68 and
`voltage-controlled oscillator 76 are particularly sensitive to
`changes in temperature and transistor threshold voltage. The
`accuracyof phasc-locked-loop circuit 50is therefore depen-
`dent on the proper operation of charge pump68 andvoltage-
`controlled-oseillator 76.
`Although the illustrative circuit of FIG. 7 is a phase-
`lockedloop, sensitive circuitry 36 (FIG. 4) may be circuitry
`such as a delay-locked loop circuit in which a delay line is
`used to insert a controllable delay between its clock input
`and output lines or any other suitable sensitive circuitry.
`Sensilive circuits such as these may be provided with
`modified power supply voltages from monitoring and com-
`pensation circuit 34 (FIG. 4). The charge pump 68 and
`voltage-controtled oscillator 76 may, for example, be pro-
`vided with a modified positive power supply voltage Vcc’
`and an unmodified ground potential Vss at power supply
`inputs 78. By adjusting the power supply voltages used by
`charge pump68 andvoltage-controlled oscillator 76, phase-
`locked-loop circuit 50 (or a delay-locked loop circuit) will
`function accurately, evenif the operating temperature and/or
`threshold voltages of the transistors of circuit 32 change.
`Voltage-controlledoscillator 76 may have fourstages 80
`(for example), as shownin FIG. 8. The outputs ofeachstage
`are passed to the next slage in series, until the differential
`outputs of the last stage 80 are inverted and fed back to the
`input of the first stage 80. This type of arrangement produces
`an oscillating signal whose period is determined by the
`propagation delay between stages.
`Anillustrative stage 80 is shown in FIG. 9. As shownin
`FIG. 9, each stage 80 has differential inputs IN-N and IN-P
`and corresponding differential outputs OUT-N and OUT-P.
`The circuitry of stage 80 may be powered by an adjusted
`power supply voltage Vec' and a groundvoltage Vss. Bias
`voltages Varasp and Vpzas.a, Which are received from loop
`filler 72 on lines 74 (FIG. 7) may be appliedto the gates of
`transistors 82 and 84 to control the speedofstage 80. With
`oneillustrative arrangement, Vcc’ may be on the order of 1.2
`volts. The ground voltage may be provided by a source of
`constant ground potential. The voltage level tor Vi,45. pp May
`be about 0.85 volts and Vass.may be about 0.35 volts.
`Under
`these biasing conditions,
`the NMOS and PMOS
`transistors ofcircuit 80 are susceptible to threshold voltage
`drift.
`During operation ofthe integratedcircuit 32, monitoring
`and compensation circuitry 34 measures changes in tem-
`perature and changes in transistor threshold voltage. To
`ensure that
`the measured changes in threshold voltage are
`accurate, a differential measurement technique may be used
`in which measurements are made on both a continuously-
`biased circuit (where the threshold changes duc to NBTT and
`gate oxide charge accumulation are will be greatest) and on
`an intermittently-biasedcircuit (where the threshold voltage
`will change much less and can serve as a baseline). By
`comparing measurements from these twocircuits (Le., by
`taking the difference between these measurements),
`the
`changes in threshold voltage AVin and AVip may be accu-
`rately determined.
`Any suitable monitoring and compensation circuitry 34
`may be used to compensate for the effects of changes in
`temperature andthresbold voltage in integrated ciremt 32.
`Ilustrative monitoring and compensation circulry 34 is
`
`8
`shown in FIG. 10. Monitoring and compensation circuitry
`34 may take measurements from various circuits such as one
`or more threshold monitoring circuits 86, one or more
`temperature monitoring circuits 88, and one or more addi-
`tional monitoring circuits 90. These measurements are pro-
`cessed by the monitoring and compensation circuitry 34 and
`one or more corresponding adjusted power supply voltages
`are provided accordingly.
`In the example of FIG. 10, monitoring and compensation
`circuitry 34 produces an adjusted value of the normal
`positive power supply voltage Vec, called Vec'. Vee’
`is
`generally higher than the nominal value of Vee (i.¢., Vcc’is
`boostedrelative to Vec) to overcome the shrinking operating
`voltage range 44 due to increases of Vin and Vtp, as
`discussed in connection with FIG. 6.
`
`The operation of monitoring and compensation circuitry
`34 may be controlled using a control circuit 94. Control
`circuit 94 may be implemented using custom logic, a pro-
`cessor, memory, etc. Control circuit 94 may be used to
`implement
`the functions of a state machine that makes
`decisions on how to adjust Vec' based on the measurements
`from circuits such as circuits 86, 88, and 90.
`A multiplexer 96 or other suitable switching circuitry
`under the control of control circuitry 94 may be used to
`select which circuit
`to monitor. Multiplexer 96 can be
`controlled to selectively connect each ofils inputs 98 toa
`corresponding output 100. The signals on output 100 maybe
`digitized using an analog-to-digital converter 102. Measure-
`ments may be made on circuits 86, 88, and 90 in serics (..c.,
`by selectively measuring signals from cach ofthese circuits
`using multiplexer 96) or multiple multiplexers and signal
`paths may be connectedto analog-to-digital converters such
`as analog-to-digital converter 102 to make measurementsin
`parallel. Control lines such as control lines 106 maybe used
`to control circuits such as circuits 86, 88, 90, and multiplexer
`96.
`
`Digital signals from analog-to-digital converter 102 may
`be providedto control circuitry 94 over paths such as path
`104. The control circuitry 94 may process raw measure-
`ments from the monitoring circuits to determine AVip and
`AVin. The control circuitry may then determine how to
`adjust Vec'
`to compensate for t