a2) United States Patent
`US 7,577,859 B2
`(10) Patent No.:
`Aug. 18, 2009
`(45) Date of Patent:
`Bilak
`
`US007577859B2
`
`(54)
`
`SYSTEM AND METHOD OF CONTROLLING
`POWER CONSUMPTIONIN AN
`ELECTRONIC SYSTEM BY APPLYING A
`UNIQUELY DETERMINED MINIMUM
`OPERATING VOLTAGETO AN INTEGRATED
`CIRCUIT RATHER THAN A
`PREDETERMINED NOMINAL VOLTAGE
`SELECTED FOR A FAMILY OF INTEGRATED
`CIRCUITS
`
`(75)
`
`Inventor: Mark Bilak, Sandy Hook, CT (US)
`
`(73)
`
`Assignee:
`
`International Business Machines
`Corporation, Armonk, NY (US)
`
`Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 359 days.
`
`(21)
`
`Appl. No.: 10/708,270
`
`(22)
`
`Filed:
`
`Feb. 20, 2004
`
`Prior Publication Data
`
`US 2005/0188230 Al
`
`Aug. 25, 2005
`
`Int. Cl.
`GO6F 1/00
`
`(2006.01)
`(2006.01)
`GO6F 1/32
`(2006.01)
`GOIR 15/00
`US» Chi
`saves cwesesnecsees 713/320; 713/300; 702/57;
`702/62; 702/64; 702/117
`Field of Classification Search................. 713/300,
`713/320, 322, 500, 600; 702/57, 62, 64,
`702/117, 118, 122
`See application file for complete search history.
`References Cited
`
`(65)
`
`GS)
`
`(52)
`
`(58)
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`3,881,181 A
`4,670,731 A
`
`4/1975 Khajezadeh
`6/1987 Zeile etal.
`
`5,086,501 A *
`5,557,558 A
`
`2/1992 DeLucaetal... 713/300
`9/1996 Daito
`
`(Continued)
`FOREIGN PATENT DOCUMENTS
`
`JP
`
`2001142589 A *
`
`5/2001
`
`OTHER PUBLICATIONS
`
`Justice Tricia, What is guard band?, Apr. 1997, Credence Systems
`Corp.*
`
`Primary Examiner—Mark Connolly
`(74) Attorney, Agent, or Firm—Joseph P. Abate; Mark Bilak;
`Daryl K. Neff
`
`(57)
`
`ABSTRACT
`
`A methodand apparatus for adaptively adjusting the operat-
`ing voltage of an integrated circuit in response to tester-to-
`system variations, worst-case testing techniques, process
`variations,
`temperature variations, or reliability wearout
`mechanisms. The minimum operating voltage of an inte-
`grated circuit is determined either during external testing of
`the integrated circuit or during built-in-selftesting. The mini-
`mum operating voltage is transmitted to a variable voltage
`regulator where it is used to set the output ofthe regulator. The
`output of the regulator supplies the integrated circuit with its
`operating voltage. This technique enables tailoring of the
`operating voltage ofintegrated circuits on a part-by-part basis
`whichresults in power consumption optimization by adapt-
`ing operating voltage in response to tester-to-system varia-
`tions, worst-case testing techniques, process variations, tem-
`perature variations or
`reliability wearout mechanisms.
`Alternatively, the invention enables adaptive adjustment of
`the operating frequency of an integrated circuit. The inven-
`tion enables system designers to adaptively optimize either
`system performance or power consumption on a part-by-part
`basis in response to tester-to system variations, worst-case
`testing techniques, process variations, temperature variations
`or reliability wearout mechanisms.
`
`17 Claims, 9 Drawing Sheets
`
`200
`
`Communication®
`Link Idle
`
`42210
`
`Transmit
`+/- V Signal
`
`
`
`
`
`Voperating
`= Vmin?
`
`
`
`
`
`
` ‘es
`
`x
`
`Communication
`Link Idle
`
`24
`
`230
`
`INTEL 1003
`
`INTEL 1003
`
`

`

`US 7,577,859 B2
`
`Page 2
`
`U.S. PATENT DOCUMENTS
`
`6/1997 Krick etal.
`5,638,382 A
`11/1997 Walker
`5,689,179 A
`5,692,201 A * LI/1997 Yato wc eeccceceeeeeee 713/322
`5,764,655 A
`6/1998 Kirihataet al.
`6,009,139 A
`12/1999 Austin etal.
`6,035,407 A *
`3/2000 Gebaraet al. «0.0... 713/300
`6,040,725 A
`3/2000 Lee et al.
`6,046,492 A
`4/2000 Machidaet al.
`6,058,030 A
`5/2000 Hawkesetal.
`6,061,811 A
`5/2000 Bondi etal.
`
`6,425,086 Bl
`6,433,525 B2
`6,496,729 B2
`6,515,530 B1
`6,522,207 Bl
`6,564,348 Bl
`6,601,179 B1
`6,912,665 B2*
`7,017,063 B2*
`7,100,061 B2*
`
`7/2002 Clark etal.
`8/2002 Muratovetal.
`12/2002 Thompson
`2/2003 Boerstleret al.
`2/2003 Boerstler et al.
`5/2003 Barenyset al.
`7/2003 Jacksonetal.
`6/2005 Ellisetal. wc. 713/401
`
`..
`3/2006 Morseet al.
`.. 713/340
`............. 713/322
`8/2006 Halepeteet al.
`
`* cited by examiner
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 1 of 9
`
`US 7,577,859 B2
`
`Voltage
`
`Figure 1. (PRIOR ART)
`
`Frequency
`32
`
`Temperature
`
`Delta T
`
`a —
`
`Figure 2. (PRIOR ART)
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 2 of 9
`
`US 7,577,859 B2
`
`
`
` », Voperating
`
`Communication
`
`Zd0
`
` Transmit
`
`+/- V Signal
`
`Zl
`
`53
`
`370 -
`
`Transmit
`
`Vmin Signal
`
`Voperating
`=Vmin?
`
` »
`
`2
`
`ao tink &
`
`
`
`
`
`
`
`
`
`
`Figure 4b.
`
`
`Communication
`Link Idle
`
`Communication
`Link Idle
`
`Figure 4a.
`
`250
`
`23 0
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 3 of 9
`
`US 7,577,859 B2
`
`
`
`Communication
`
` ay Voperating
`a”© Link K
` (+ / -V or Vmin value)
`
`
`Joe
`
`Figure 5,
`
`
`
`.| Vmin Routine
`
`320 |
`
`522
`
`324
`
`306
`
`perso
`
`oO
`
`N
`
`Increment
`
`Figure 6.
`
`30G
`
`30
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 4 of 9
`
`US 7,577,859 B2
`
`Increment
`Vmin
`
`Increment
`More?
`
`340
`
`342
`
`3 44
`
`IC
`Initialization
`Failure
`
`34 &
`
`343
`
`Figure 7a.
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 5 of 9
`
`US 7,577,859 B2
`
`Bel
`
`330
`
`
`
`
`3 7 2, c7lo
`
`Ic
`Initialization
`Failure
`
`Yes
`
`Yes
`
`°
`
`Se
`
`5G7_
`
`bolo
`368
`
`370
`
`BIZ
`
`|
`
`Yes
`
`Decrement?
`
`374
`
`y No
`
`Figure 7b.
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 6 of 9
`
`US 7,577,859 B2
`
`S90
`
`Store Vmin
`
`
`
`3G2. >1}Decrement
`Vmin
`
`400
`
`34
`
`34 (
`
`398
`
`Store Vmin
`
`No
`
`BIST Idle
`
`Figure 8a.
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 7 of 9
`
`US 7,577,859 B2
`
`
`
`Set Vmin =
`
`
`Regulator Vin
`
`4 | (
`
`
`
`
`
`om
`
`HID -
`
`Hy
`
`414
`
`41
`
`O4e
`
`422
`
`424
`
`/
`
`41
`
`BIsT
`
`Pass?
`
`SNe
`
`Yes
`
`\
`
`Decrement?
`
`y ves
`
`Decrement
`
`
`Ls
`
`BIST Idle
`
`1/2 Delta
`
`ye
`
`Figure 8b.
`
`

`

`U.S. Patent
`
`Aug. 18, 2009
`
`Sheet 8 of 9
`
`US 7,577,859 B2
`
`SVL
`
`Temp.
`
`Variable Vregulator
`
`ue)$08
`
`S 10
`
`SO lo
`
`Variable Vregulator|
`
`Communication
`
`§00
`
`cor
`
`Soe
`
`GIO
`
`(p00
`
`
`
`
`
`
`an Sensor
`
`|
`Communication
`ao Link
`
`
`{renin
`Figure 9.
`
`
`
`
`
`
`
`
` Charge Pumps
`and Filters
`
`Reference
`Clock
`
`(pil
`
`iyby
`
`
`(04
`
`Figure 11, (PRIOR ART)
`
`

`

`U.S. Patent
`
`Sheet 9 of 9
`
`US 7,577,859 B2
`
`620 ~
`
`(o22
`
`(024
`
`62 &
`
`(030
`
`(034 Aug. 18, 2009
`
`Increment
`Programmable
`PLL
`
`IC initialized
`at nominal
`frequency
`
`Fopt
`determined
`
`Fopt - Fvco
`
`Decrement
`Programmable
`PLL
`
`Figure 12.
`
`

`

`US 7,577,859 B2
`
`1
`SYSTEM AND METHOD OF CONTROLLING
`POWER CONSUMPTIONIN AN
`ELECTRONIC SYSTEM BY APPLYING A
`UNIQUELY DETERMINED MINIMUM
`OPERATING VOLTAGE TO AN INTEGRATED
`CIRCUIT RATHER THAN A
`PREDETERMINED NOMINAL VOLTAGE
`SELECTED FOR A FAMILY OF INTEGRATED
`CIRCUITS
`
`BACKGROUNDOF INVENTION
`
`The present invention relates to controlling power con-
`sumption of an electronic component within an electronic
`system. Alternatively, the present inventionrelates to control-
`ling operating frequency of an electronic component within
`an electronic system.
`Power consumption increasingly has become a major
`obstacle to circuit and system designers. Advances in inte-
`grated circuit (IC) technology have resulted in millions of
`transistors being placed on single ICs. Additionally, IC tech-
`nology advancesalso enable circuits to switch at increasingly
`faster speeds. As the physical sizes of ICs continue to shrink
`while at the same time performance (i.e. switching speed)
`increases, power density substantially increases. This sub-
`stantial increase in power density causes power management
`problemsfor system designers. Power management problems
`take form in both heat dissipation and battery life issues.
`Greater power dissipated by ICs with ever decreasing area
`causes significant temperature control issues at the system
`level. The problem has become sopervasive that conventional
`forced air cooling systemsare no longerable to dissipate the
`powergenerated by modern ICs. System designers are being
`forced to utilize liquid cooled solutions for dissipating ever
`increasing power requirements. Increased power consump-
`tion also creates battery life issues in portable systems and can
`significantly impact the usefulness of portable devices.
`Power consumption in ICs comes from two components:
`Static and Dynamic power. Static power consumption (Py)
`results from (1) leakage current and (2) sub-threshold con-
`ductance and is characterized by the following equation:
`Prraticleakage¥pp: Dynamic power consumption (Py,amic)
`results from (1) capacitive powerdue to charging/discharging
`of capacitive loads and (2) short-circuit power dueto direct
`path currents whenthere is a temporary connection between
`powerand ground(e.g. when both p and n transistors are “on”
`in CMOScircuits) and is characterized by the following
`equation: Pgmamid~2&CERVpp:SFoperatic Further compli-
`cating increases in IC power consumption is manufacturing
`test. Cost considerationslimit the amountoftest time that can
`
`be dedicated to each IC. Manufacturing test cost concerns
`often limit the amount of characterization testing that can be
`done on any one IC (testing the part across a range of tem-
`perature, voltage and frequency to ensure robust operation).
`ICs are often tested at worst-case system operating conditions
`and at somefixed frequency(e.g. “speed” sorting) to assure
`all ICs shipped will function properly in the end system.
`For example, microprocessors may be tested at somefixed
`frequency (at which they are expected to function in a sys-
`tem), a maximum temperature and a minimumoperating
`voltage. Although a few of these processors may operate
`marginally at those conditions (and somewill fail), most that
`function at those minimum requirements will operate well
`beyond those limits. This is mainly due to variations within
`the semiconductor manufacturing process (e.g.
`threshold
`voltage, transistor channel length, and gate oxide variations).
`A normaldistribution often describes how a sample ofparts
`
`2
`will behave beyond those limits. Except for that small number
`ofparts that are marginal, most parts are capable of operating
`at frequencies above the minimum test frequency. However,
`becauseoftime constraints, this maximum operating speedis
`not determined. It is well known in the art that a circuit’s
`
`operating speed is proportionalto its operating voltage. The
`lower the voltage, the lower the speed (and vice-versa). See
`FIG.1 for an illustration ofthe frequency/voltage response 10
`wherethe slope of the curve 12 (Delta V/Delta F) represents
`the amount of performance change (Delta F) expected for
`some change in operating voltage (Delta V). The extreme
`operating conditions of the IC are identified by the mintmum
`operating voltage 14 (Vmin), minimum operating frequency
`16 (Fmin), maximum operating voltage 18 (Vmax), and
`maximum operating frequency 20 (Fmax). Beyondthese con-
`ditions, the IC no longer functions properly.
`Therefore, for the majority of ICs that are capable of func-
`tioning beyond the minimum test frequency, their operating
`voltage may be lowered until the part functions just abovethe
`minimum system frequency.
`Furthermore, it is well known in the art that a circuit’s
`operating speed is inversely proportional to temperature. The
`lower the system temperature, the faster the speed (and vice-
`versa). See FIG. 2 for an illustration of the frequency/tem-
`perature response 30 where the slope of the curve 32 (Delta
`T/Delta F) represents the amount of performance change
`(Delta F) expected for some change in operating temperature
`(Delta T). The extreme operating conditions of the IC are
`identified by the minimum operating temperature 34 (Tmin),
`minimum operating frequency 36 (Fmin), maximum operat-
`ing temperature 38 (Tmax), and maximum operating fre-
`quency 40 (Fmax). Beyondthese conditions, the IC no longer
`functions properly.
`By limiting manufacturing testing to pass/fail testing at
`worst-case system requirements, end system power con-
`sumption is adversely affected in two ways: (1) most ICsthat
`function at the minimum system speedat test will function
`well beyond it in the end system and (2) most ICs do not
`operate at the maximum system temperatures at which they
`are typically tested; and thus, their operating voltage may be
`lowered. Additionally, variations in the tester environment
`may also add to measurement inaccuracies.
`For example, an IC which has enough margin to function at
`the required system operating frequencyat a voltage of 1.6V
`instead of a nominal voltage of 1.8V, the powersavingsreal-
`ized by operating the IC at 1.6V instead of 1.8V wouldbe: (1)
`21% dynamic power reduction and (2) 11% static power
`reduction.
`
`This problem is exasperated in portable devices because
`battery life is unnecessarily degraded whenan IC is operated
`at worst-case system conditions although the system rarely
`(or never) actually operates at such worst-case conditions and
`the IC is capable of functioning properly below the worst-
`case conditions.
`
`Finally, the problems associated with manufacturing test
`and end system operation previously described maybe uti-
`lized to achieve more than reduced power consumption.
`Because system components are tested at worst-case condi-
`tions as previously described, many parts have additional
`performance margin. Instead of, or in addition to, adjusting
`operating voltage to reduce power consumption, the voltage
`may remain at nominal system conditions, or increased, so
`that an IC may function at
`increased frequencies,
`thus
`improving system performance. The same temperature/volt-
`age relationships previously mentioned may beutilized to
`achieve suchresults.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`

`

`US 7,577,859 B2
`
`3
`(1) Clock Control: numerous techniques exist for manag-
`ing power consumption by controlling clocking. Depending
`on processing demand, clock frequency may be increased or
`decreased to meet that demand. Thus, during low demand
`periods, clock frequency may be lowered, thereby saving
`power. Clock frequency is increased only to satisfy demand.
`Also, clock throttling is common.
`(2) U.S. Pat. No. 6,496,729, entitled Power consumption
`reduction in medical devices employing multiple supply volt-
`ages and clock frequency control, by Thompson: Teaches a
`methodfor tailoring supply voltagesto specific circuits. Thus,
`each circuit receives a tailored operating voltage as opposed
`to all circuits receiving the same voltage. For example, low
`performance circuits may be powered at a lower operating
`voltage because they do not need to operate at maximum
`speeds. Only thosecircuits requiring maximum performance
`receive higher operating voltages. Additionally, this patent
`teaches alternating between a lower operating voltage and a
`higher operating voltage depending on the expected workload
`for a given cycle. For example, if cycle one does not require
`peak performance, a lower operating voltage is supplied. If
`cycle two requires maximum performance,a higher operating
`voltage is supplied. This patent does not teach or suggest a
`means for adjusting operating voltage based upontester-to-
`system variations, worst-case testing techniques, or process
`variations. Furthermore, this patent does not teach or suggest
`the use ofa built-in-self-test engine for determining the mini-
`mum operating voltage of an integrated circuit throughoutits
`useful life.
`
`(3) US. Pat. No. 6,601,179, entitled Circuit and method for
`controlling power and performance based on operating envi-
`ronment, by Jackson et al.: Teaches a system and method for
`adjusting processor clock frequency and operating voltage
`based upon the operating environment. For example, if the
`processoris “docked”into a system that has cooling capabili-
`ties, the processor can be run at lower operating conditions,
`thereby lowering power. This patent does not teach or suggest
`a meansfor adjusting operating voltage based upontester-to-
`system variations, worst-case testing techniques, or process
`variations. Furthermore, this patent does not teach or suggest
`the use ofa built-in-self-test engine for determining the mini-
`mum operating voltage of an integrated circuit throughoutits
`usefullife.
`
`(4) US. Pat. No. 6,425,086, entitled Method and apparatus
`for dynamic powercontrol ofa low powerprocessor, by Clark
`et al.: Teaches a method and apparatus for dynamically con-
`trolling power of a microprocessorby adjusting the operating
`voltage of the microprocessor. The method and apparatus
`includesa variable voltage regulator, a memory element and
`a processor. The output of the regulator is adjusted according
`to the processing load ofthe processor. The memory contains
`processorinstructions, that when executed by the processor,
`result in modifications to the operating frequencyofthe pro-
`cessor. The regulator is adjusted accordingly depending upon
`the dynamic changesin the processing loadof the processor.
`This patent does not teach or suggest a means for adjusting
`operating voltage based upon tester-to-system variations,
`worst-case testing techniques, or process variations. Further-
`more, this patent does not teach or suggest the use of a
`built-in-self-test engine for determining the minimumoper-
`ating voltage of an integrated circuit through its usefullife.
`
`SUMMARY OF INVENTION
`
`The present inventor believes that the prior art has at least
`the following drawbacks: An object of the invention is to
`adaptively adjustthe operating voltageof an integratedcircuit
`
`4
`in responseto tester-to-system variations, worst-case testing
`techniques or process variations.
`Another object of the invention is to adaptively adjust the
`operating voltage of an integrated circuit in responseto built-
`in-self-test results.
`
`Another object of the invention is to adaptively adjust the
`operating voltage of an integrated circuit throughout the use-
`ful life ofthe integrated circuit in responseto built-in-self-test
`results.
`
`Another object of the invention is to adaptively adjust the
`operating voltage of an integrated circuit in response to the
`operating temperature of the integrated circuit.
`Another object of the invention is to adaptively adjust the
`operating frequency of an integrated circuit in response to
`tester-to-system variations, worst-case testing techniques or
`process variations.
`Another object of the invention is to adaptively adjust the
`operating frequency of an integrated circuit in response to
`built-in-self-test results.
`
`
`
`
`
`Another object of the invention is to adaptively adjust the
`operating frequency of an integrated circuit throughout the
`usefullife ofthe integrated circuit in responseto built-in-self+
`test results.
`
`Another object of the invention is to adaptively adjust the
`operating frequency of an integrated circuit in responseto the
`operating temperature of the integrated circuit.
`Further andstill other objects of the present invention will
`become morereadily apparent when the following detailed
`description is taken in conjunction with the accompanying
`drawingfigures.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`40
`
`45
`
`FIG. 1 is a diagram illustrating the frequency/voltage
`response of an integrated circuit according to thepriorart.
`FIG. 2 is a diagram illustrating the frequency/temperature
`response of an integrated circuit according to thepriorart.
`FIG.3 is a diagramillustrating an end system incorporating
`an adaptive feedback mechanism for controlling the operat-
`ing voltage of an integrated circuit according to the present
`invention.
`
`FIG.4ais a diagram illustrating a methodfor transmitting
`voltage control information from an integrated circuit to a
`variable voltage regulator according to the present invention.
`FIG. 44 is a diagram illustrating an alternate method for
`transmitting voltage control information from an integrated
`circuit to a variable voltage regulator according to the present
`invention.
`
`FIG.5 is a diagram illustrating an end system incorporating
`an adaptive feedback mechanism for controlling the operat-
`ing voltage ofan integrated circuit in responseto built-in-self-
`test results according to the present invention.
`FIG.6 is a diagram illustrating a method for determining
`the minimum operating voltage of an integrated circuit in
`response to built-in-self-test results according to the present
`invention.
`
`FIG. 7ais a diagram illustrating a method for incrementing
`the minimum operating voltage of an integrated circuit in
`response to built-in-self-test results according to the present
`invention.
`
`FIG. 76 is a diagram illustrating an alternate method for
`incrementing the minimum operating voltage of an integrated
`circuit in responseto built-in-self-test results according to the
`present invention.
`
`

`

`US 7,577,859 B2
`
`5
`FIG.8a is a diagram illustrating a method for decrementing
`the minimum operating voltage of an integrated circuit in
`responseto built-in-self-test results according to the present
`invention.
`
`FIG. 86 is a diagram illustrating an alternate method for
`decrementing the minimum operating voltage of an inte-
`grated circuit in responseto built-in-self-test results accord-
`ing to the present invention.
`FIG. 9 is a diagram illustrating an end system incorporating
`an adaptive feedback mechanismfor controlling the operat-
`ing voltage of an integrated circuit in response to operating
`temperature ofthe integrated circuit according to the present
`invention.
`FIG.10 is a diagram illustrating an end system incorporat-
`ing an adaptive feedback mechanism for controlling the oper-
`ating frequency of an integrated circuit according to the
`present invention.
`FIG. 11 is a diagram illustrating a programmable phase-
`locked-loop according to thepriorart.
`FIG. 12 is a diagram illustrating a method for determining
`the optimum operating frequency of an integrated circuit
`according to the present invention.
`
`DETAILED DESCRIPTION
`
`FIG.3 illustrates the preferred embodimentof the inven-
`tion. The integrated circuit 100 (IC) and variable voltage
`regulator 110 (Vregulator) are two components contained
`within an end system such as a personal computer, portable
`electronic device, printer, etc. IC 100 may be any integrated
`circuit type. Vregulator 110 may be any variable voltage
`regulator capable of supplying somerange ofvoltage to the
`IC. For example, variable regulator 110 may be capable of
`supplying 1.8V+200 mV at 50 mV increments. The output
`140 of Vregulator 110 is supplied to IC 100 as its operating
`voltage over a powerline. Powerline connections between
`powersupplies and electronic components are well known in
`the art. Variable voltage regulators, like the one illustrated in
`FIG. 3, are well knownin the art. For example, such regula-
`tors are described more fully in: U.S. Pat. No. 5,689,179,
`entitled Variable Voltage Regulator System, by Walker; U.S.
`Pat. No. 6,058,030, entitled Multiple Output DC-to-DC Con-
`verter Having Enhanced Noise Margin and Related Methods,
`by Hawkeset al.; and U.S. Pat. No. 6,433,525, entitled DC to
`DC Converter Method and Circuitry, by Muratovet al., the
`subject matter of which are hereby incorporated by reference
`in their entirety.
`IC 100 is linked with Vregulator 110 via communication
`link 120 so that the IC may communicate with the regulator,
`thus enabling transmission of data from IC 100 to Vregulator
`110. Methods for providing communication links between
`electronic equipment are well knownin the art. For example,
`the IC maybelinked to the regulator by a simple unidirec-
`tional signal line, a bus or a wireless link.
`The minimum operating voltage (“Vmin’’) of IC 100 is the
`minimum voltage at which the IC will function properly(e.g.
`all functional paths of the IC work properly) at somefixed
`frequency. In other words, Vmin represents the minimum
`voltage at which the slowest functional path(s) within the IC
`will still function properly at somefixed frequency. The slow-
`est functional path(s) within the IC will not function properly
`if the operating voltage of the IC drops below Vmin. Vmin of
`IC 100 is stored in the IC during externaltest (e.g. manufac-
`turing test). This may be accomplished using a number of
`components well known in the art such as EEPROM,non-
`volatile memory, ROM, flash memory, fuses, antifuses, etc.
`Vmin may be reduced by some amountto account for inac-
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`curacies in the test measurement(e.g. guardband). The stored
`Vmin value is the minimum voltage at which the IC will
`function properly in the end system. IC 100 transmits voltage
`control
`information 130 (e.g. Vmin plus guardband) to
`Vregulator 110 over link 120 as either an increment/decre-
`mentsignalor as a data signal representing the value ofVmin.
`The process by whichthe variable regulator’s output volt-
`age is set to Vmin is illustrated in FIG.4a, or alternatively,
`FIG.48. FIG.4aillustrates one embodimentfor setting the
`output of the Vregulator to Vmin. In this embodiment, the
`value of Vmin is transmitted as a signal that represents that
`value. Upon system power up,
`the system is initialized,
`includingall of its components. Initially, the communication
`link is idle 200. Duringinitialization, the Vregulator provides
`some predetermined voltage to the IC. This predetermined
`value is a value at whichall ICs are expected to function in the
`end system (e.g. nominal or worse-cast value). Because only
`a few of the ICs will actually need to operate at this value to
`meet performance requirements, most ICs can be operated at
`a lower voltage andstill satisfy the performance require-
`ments.
`
`Based upon the stored value of Vmin, the IC determines
`whether the Vregulator must
`increase, decrease, or not
`change the predetermined voltage value 210. This determi-
`nation is made by the IC using a comparison technique
`whereby the IC comparesthe predetermined voltage with the
`stored value of Vmin.If the IC determinesthat the predeter-
`mined value must be changed, the IC transmits a signal that
`represents the value ofVmin to the Vregulator over the com-
`munication link 220. Ifno changeis required, the IC transmits
`nothing to the Vregulator and the link remainsidle 200. When
`the Vregulator receives a Vmin signal from the IC, it pro-
`gramsits output voltage in accordance with the Vmin signal.
`The output of the Vregulator is supplied to the IC as its
`operating voltage (Voperating). Therefore, Voperating will
`either remain the same as the predetermined voltage, be
`increased by some amount abovethe predetermined voltage,
`or be decreased by some amount below the predetermined
`voltage. When the IC is not communicating with the Vregu-
`lator, the communication link remainsidle 230 (i.e. no signal
`transmissions).
`FIG.46 illustrates an alternate embodimentfor setting the
`output of the Vregulator to Vmin.In this embodiment, Vmin
`is transmitted as an increment/decrementsignal. This signal
`represents a fixed amount by which the Vregulator will either
`increment or decrementits output by. During system power
`up, the system is initialized, includingall of its components.
`Initially, the communication link is idle 200. During initial-
`ization, the variable voltage regulator provides some prede-
`termined voltage to the IC. This predetermined value is a
`value at which all ICs are expected to function in the end
`system (e.g. nominal or worse-cast value). Because only a
`few of the ICs will actually need to operate at this value to
`meet performance requirements, most ICs can be operated at
`a lower voltage and still satisfy the performance require-
`ments.
`
`Based upon the stored value of Vmin, the IC determines
`whether the Vregulator must
`increase, decrease, or not
`change the predetermined voltage value 210. This determi-
`nation is made by the IC using a comparison technique
`whereby the IC comparesthe predetermined voltage with the
`stored value of Vmin. If no change is required, the IC trans-
`mits nothing to the Vregulator andthe link remainsidle 200.
`If the IC determines that the predetermined value must be
`changed, the IC transmits the increment/decrementsignal to
`the Vregulator over the communication link 212 (e.g. incre-
`mentsignals ifthe output ofthe Vregulator mustbe increased,
`
`

`

`US 7,577,859 B2
`
`7
`decrement if it must be decreased). When the Vregulator
`receives the increment/decrement signal from the IC, it pro-
`gramsits output voltage in accordance with that signal. The
`IC then determines whether the Vregulator must further
`increase or decreaseits outputso that it matches Vmin 214. If
`the output of the Vregulator does not match Vmin as deter-
`mined bythe IC, the IC again transmits the increment/decre-
`ment signal to the Vregulator over the communication link
`212. This processis repeated until the output ofthe Vregulator
`matches Vmin(or is within some tolerance amount). The
`output of the Vregulator is supplied to the IC as its operating
`voltage (Voperating). Therefore, Voperating will either
`remain the same as the predetermined voltage, be increased
`by some amount above the predetermined voltage, or be
`decreased by some amountbelow the predeterminedvoltage.
`When the IC is not communicating with the regulator, the
`communication link remainsidle 230 (i.e. no signal transmis-
`sions).
`This process enables Voperating to be uniquely tailored for
`individual ICs. This process of adjusting the output of the
`Vregulator may occur during the IC initialization routineor at
`some pointlater in time (e.g. during normal operation).
`Vimin is determined during testing of the IC (typically by
`an external tester during manufacturing test). Various tech-
`niques are well knownin the art for determining the Vmin of
`an IC using an external tester. For example, a microproces-
`sor’s Vmin may be determined with an external tester by
`exercising the microprocessor with functionalpatterns(in the
`form of instructions) at some fixed frequency and at various
`operating voltages. This process may begin at a relatively
`high voltage and then be repeated at successively lowervolt-
`ages until
`the microprocessor no longer
`functions as
`expected. The last voltage where the IC functioned properly
`would beits Vmin. Another techniqueis testing the IC with an
`external tester at a relatively low voltage and then repeating
`that test at successively lower voltages until the microproces-
`sor no functions as expected. The first voltage where the IC
`functioned properly would be its Vmin. Another technique is
`testing the IC with an external tester at a relatively high
`voltage and then repeating the test at a relatively low voltage.
`If the part functions at both extremes, its Vmin would be the
`lowest test voltage. If the part fails, the tester would test the
`processorat a voltage halfway in between the upper and lower
`voltages. This process would continue until the processor’s
`Vmin is determined. Vmin is then stored in the IC. Other
`
`techniques for determining Vmin using external testers are
`well know in the art and this invention is not limited by the
`ones previously described.
`FIG. 5 illustrates a second embodiment where IC 302 is
`
`capableofself-testing, which is performedbya built-in-self-
`test (“BIST”) engine, so that Vmin may be determined while
`the IC is in the end system. Preferably, self-testing is per-
`formed during IC initialization in order to minimizepotential
`system interruption. This may occur during each IC initial-
`ization or may occur at some interval of initializations (e.g.
`every 10th initialization, self-testing is performed). Self-test-
`ing may be performed during normaloperating conditions or
`any other time when the IC is in the end system (e.g.idle
`state). In addition to optimizing power consumption, this
`embodiment also provides a means for adjusting the operat-
`ing voltage ofan IC throughoutits usefullife. As is well know
`in the art, IC performance degrades over time as a result of
`reliability wearout mechanisms. For example, IC perfor-
`mance will decrease as a result of hot electron degradation
`which causes damageatthe gate/draininterface oftransistors,
`thus raising the threshold voltage (Vt) ofthe transistor. As a
`transistor’s Vt is increased, more time is requiredto invert the
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`channelofthe transistor, thus degrading the transistor’s per-
`formance. Another reliability wearout mechanism is elec-
`tromigration. Electromigration results in the displacementof
`metal wiring within ICs due to movement of electrons
`through the wires. This displacement increases wire resis-
`tance and possibility coupling capacitance, thus degrading
`the performance of an IC. Vmin of an IC may be adjusted to
`compensate for wearout-induced performance degradation.
`By increasing Vmin sufficiently enough, the performance
`requirements of an IC still may besatisfied, thus preventing
`failure of an IC in the end system. Wearout-inducedperfor-
`mance degradation may be compensated for by adjusting
`Vmin according to the self-test embodiment described
`herein. Because the IC has the capability of routinely deter-
`mining Vmin throughout its useful life, any performance
`degradation may be compensated for using the system and
`method described herein.
`
`BISTengine 300 may exist separately from IC 302 or may
`be physically contained within IC 302asillustrated in FIG. 5.
`BIST engine 300 mayinclude an interrupt procedure, IC 302
`may include an interrupt procedure or IC 302 maybeinter-
`rupted e