US007583555B2
`
`a2) United States Patent
`US 7,583,555 B2
`(10) Patent No.:
`Sep. 1, 2009
`(45) Date of Patent:
`Kanget al.
`
`(54)
`
`ROBUST AND EFFICIENT DYNAMIC
`VOLTAGE SCALING FOR PORTABLE
`DEVICES
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(75)
`
`Inventors:
`
`Inyup Kang, San Diego, CA (US);
`Karthikeyan Ethirajan, San Diego, CA
`(US); Matthew Levi Severson,
`Oceanside, CA (US); Mohamed
`Elgebaly, San Diego, CA (US); Manoj
`Sachdev, Waterloo (CA); Amr Fahim,
`Newport Beach, CA (US)
`
`6,134,152 A * 10/2000 Mullarkey .........0.. 365/189.01
`6,813,210 B2* 11/2004 Okamoto etal.
`......0.... 365/222
`6,992,405 B2*
`1/2006 Zhang elal. ........0. 307/140
`7,075,276 B2*
`7/2006 Morales .........c cece 323/246
`7,294,976 BL* 11/2007 Andric etal. 0.000... 315/291
`
`* cited by examiner
`
`(73)
`
`Assignee: QUALCOMMIncorporated, San
`Diego, CA (US)
`
`Primary Examiner—Matthew V Nguyen
`(74) Attorney, Agent, or Firm—Niayu Xu
`
`Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 279 days.
`
`(21)
`
`Appl. No.: 10/814,935
`
`(22)
`
`Filed:
`
`Mar.30, 2004
`
`(65)
`
`Prior Publication Data
`
`US 2005/0218871 Al
`
`Oct. 6, 2005
`
`Related U.S. Application Data
`
`(60)
`
`Provisional application No. 60/462,667, filed on Apr.
`11, 2003.
`
`6S)
`
`Int. Cl.
`
`(52)
`(58)
`
`(2006.01)
`GUC 7/00
`(2006.01)
`GOSF 1/40
`US. C1.
`cccccccecceeteetecsteneeeeneeaes 365/226; 323/282
`Field of Classification Search ................. 323/268,
`323/270, 271, 273, 282, 283; 365/189.02,
`365/189.07, 226-228; 713/300, 320, 324
`See application file for complete search history.
`
`(57)
`
`ABSTRACT
`
`A method and apparatus for voltage regulation uses, in one
`aspect, worst-case supply voltages specific to the processsplit
`of the integrated device at issue. In another aspect, a two-
`phase voltage regulation system and methodidentifies the
`characterization data pertinentto a family ofintegrated circuit
`devices in a first phase, and identifies an associated process
`split ofa candidate integrated circuit device in a second phase.
`The characterization data from the first phase is then used to
`provide supply voltages that correspondto target frequencies
`of operation for the candidate device. In another aspect, a
`hybrid voltage regulator circuit includes an open loop circuit
`which automatically identifies the process split of the inte-
`grated circuit device and allowsa regulator to modify supply
`voltage based on characterization data specific to that process
`split, and a closed loop circuit which fine-tunes the supply
`voltage. In one embodiment, the closed-loop circuit includes
`a critical path replica for providing estimated frequencies of
`operation necessary for a critical path in the integrated circuit
`device. A ring oscillator circuit may be used in one embodi-
`ment in the critical path and/or in the open loop circuit.
`
`13 Claims, 6 Drawing Sheets
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`

`

`U.S. Patent
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`Sep. 1, 2009
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`Sheet 1 of 6
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`US 7,583,555 B2
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`CTearoamnce|VOLTAGE
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`REGULATOR
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`US 7,583,555 B2
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`U.S. Patent
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`Sep. 1, 2009
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`U.S. Patent
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`Sep. 1, 2009
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`Sheet 3 of 6
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`US 7,583,555 B2
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`FIG. 5
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`U.S. Patent
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`Sep. 1, 2009
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`Sheet 4 of 6
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`US 7,583,555 B2
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`U.S. Patent
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`Sep. 1, 2009
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`Sheet 5 of 6
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`US 7,583,555 B2
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`U.S. Patent
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`Sep. 1, 2009
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`Sheet 6 of 6
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`US 7,583,555 B2
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`

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`US 7,583,555 B2
`
`1
`ROBUST AND EFFICIENT DYNAMIC
`VOLTAGE SCALING FOR PORTABLE
`DEVICES
`
`CONTINUING DATA
`
`This application claims benefits of 60/462,667filed on Apr.
`11, 2003.
`
`BACKGROUND
`
`1. Field
`
`The present invention relates to integrated circuit technol-
`ogy, and more specifically to voltage source regulation.
`2. Background
`Portable electronic devices are becoming a mainstream in
`an increasing body of applications. Devices such as personal
`digital assistants (PDAs), mobile telephones, and portable
`computers are commonly usedin the marketplace. The ever-
`growing demandfrom users of such devices for more appli-
`cations and greater functionality from the services has pushed
`the envelope of design trends toward greater integration and
`moresophisticated processing on a single chip. In addition, as
`the demandfor greater functionality in portable devices has
`increased, so to hasthe push for continued decreasesin device
`form factor. These two demands have spurred the develop-
`ment of “system on a chip” designs that typically contain
`many processing functions on a single silicon chip.
`The more functionally sophisticated the portable device
`becomes, the more energy the device will invariably consume
`and hence, the smaller the battery life. Long battery life,
`however, is a very important design and marketing parameter
`that the portable electronics industries continually strives to
`improve. Naturally, the desire for increased functionality and
`decreased size must be measured within the context of the
`
`practical limitations associated with existing battery tech-
`nologies.
`Designing more versatile portable devices is nevertheless
`becoming more feasible as the silicon-based technology
`scales down. For example, transistor-based technology is
`becoming progressively smaller. Smaller form factors for
`silicon devices permit increased circuit functionality within
`the same area as devices using larger form factors. With
`smaller feature size, more integration and greater amounts of
`circuitry with added functionality can be built within a given
`area on a silicon die. Further, smaller integrated circuits
`require and consumeless energy.
`Silicon based technologies have, as a practical matter, geo-
`metrical limits. Accordingly, more sophisticated integrated
`circuits require for optimal performancethe design of energy
`reduction techniques, including integrated circuits used in a
`variety ofportable devices. These techniques can be essential
`to the design of such devices. Currently, the most effective
`energy reduction methodis to perform supply voltage regu-
`lation and to scale down the supply voltage to the chip where
`possible. Voltage regulation is a product of the industry’s
`recognition that consumed energy has a quadratic depen-
`dence on voltage, and hencedirectly relates to the amount of
`power consumedbythe battery or power source. In an illus-
`tration using complimentary metal-oxide-semiconductor
`(CMOS)technology, the active dynamic energy dissipation
`for CMOStransistors is given by the relationship
`
`E=CovgVop-
`
`where V,,, is the supply voltage, C,,,. represents the average
`switching capacitance, and E representsthe dissipated energy
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`resulting from a changeofstate of the transistor. From this
`relationship, it can be seen that reducing the supply voltage
`will correspondingly reduce the dissipated energy in the cir-
`cuit.
`
`Regardless of the silicon technology at issue, peak supply
`voltage is generally selected based on peak performance
`requirements of the integrated circuit. Frequently, peak per-
`formance maynotbe required by the processing unit(s) on the
`integrated circuit. Accordingly, supply voltage as a general
`matter can be scaled down when peak performance is not
`required. A classic example involves a cellular telephone in
`standby mode. Another illustration includes a portable data-
`receiving device whoseprocessing circuitry recognizes thatit
`can receive a given data stream at a much smaller data rate
`thanthecircuitry is capable of handling. In this instance, the
`device may not require a peak supply voltage to receive the
`data stream, and may activate some mechanism to reduce the
`voltage for this application. In many portable devices, a soft-
`ware interface is used to provide information about perfor-
`mancerequirements. That information may be used, in turn,
`by a voltage regulator to reduce supply voltage based on the
`required speedat a given instance. The voltage regulator may
`be on-chipor off-chip, depending onthe specific application.
`A numberof techniques for voltage regulation have been
`implementedin the industry or proposedin the literature. One
`such class of techniques include Dynamic Voltage Scaling
`(DVS). DVSis a voltage regulation feedback system that is
`used to dynamically control supply voltage accordingto per-
`formance requirements. By exploiting the variations associ-
`ated with different computational requirementsfor a device at
`different times, the average energy of the device can be
`reduced while maintaining the same data throughput. When
`supply voltage and operating frequency are controlled
`dynamically according to a required computational
`load
`reported by a performance managementcircuit, the average
`energy of a transistor-based silicon device can be reduced
`significantly. From this reduction in energy, it logically fol-
`lowsthat battery lifetime can be extended.
`Existing DVS techniques are not without their significant
`drawbacks. For example,situations exist where the micropro-
`cessor on a chip suddenly demands high performance. This
`performance requirement may exceed the time response
`capabilities ofthe DVS system in place. In such situations, the
`supply voltage mustbe raised to the maximum power supply
`to guarantee peak performance underall adverse conditions
`and across all variables. Only after this rapid raise in supply
`voltage, and assumingrelative stability in the ensuing oper-
`ating frequency requirement, can the voltage regulator
`attempt to lowerthe voltage, if possible, to an optimum value
`which minimizes power consumption while guaranteeing a
`sufficient voltage swing for peak processor performance.
`Other DVS techniques,
`including closed-loop voltage
`regulation systems, may rely on considerable trial-and-error
`testing prior to implementing a reliable model. Such trial-
`and-error techniques can be costly in terms of manpower,
`equipment, and time to market. In addition, such techniques
`maynotbe able to accurately track critical paths used in the
`processor for the purpose of estimating processor frequency
`requirements.
`Still other DVS techniques may notbe sensitive to all ofthe
`variations that impact device performance. For instance, the
`speed of an integrated circuit device depends on voltage,
`temperature, memory/logic structure,
`transistor threshold
`voltage, and process variations. DVS techniquesthat are not
`designed to account for each of these variations may not be
`efficient, and in some cases, may be inaccurate or may result
`in degraded or interrupted performance. When sudden per-
`
`

`

`US 7,583,555 B2
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`3
`formance increases are required, certain DVS techniques in
`this latter category must often raise supply voltage to a peak
`value that is the minimum value necessary to sustain perfor-
`mance requirements across all of these variables. However,
`this voltage may be unnecessarily high in light of one or more
`unaccounted-for variables, often resulting in an unnecessary
`taxation of battery power. If, as an illustration, a DVS regu-
`lator is not designed to recognize that a particular integrated
`circuit is operating at a fast process split, a larger than neces-
`sary supply voltage will likely be imposed onthe system in
`the event of a sudden performanceincrease requirement. This
`unnecessary voltage margin can be unacceptable in the con-
`text of mobile applications, where preservation of battery
`poweris particularly important.
`A need exists in the art for a more robust and efficient
`dynamic voltage scaling architecture especially suitable for
`highly integrated mobile devices.
`
`SUMMARY
`
`In one aspect of the present invention, a method of regu-
`lating supply voltage of an integrated circuit device includes
`calculating a reference voltage at which the integratedcircuit
`device is substantially insensitive to temperature variations,
`identifying a process split of the integrated circuit device by
`setting the supply voltage to the reference voltage and by
`measuring a corresponding reference frequency on the inte-
`grated circuit device, and regulating the supply voltage using
`characterization data correspondingto the identified process
`split.
`In another aspect of the invention, a method of regulating
`supply voltage of an integrated circuit includes determining a
`process split for the integrated circuit, associating a plurality
`ofvoltages to the process split, each voltage corresponding to
`a target frequency of operation of a processing unit on the
`integrated circuit, and regulating the supply voltageto attain
`one of the target frequencies for the processing unit using a
`corresponding oneofthe voltages associated with the deter-
`mined process split.
`In yet another aspect of the invention, a voltage regulation
`apparatus for use on an integrated circuit device includes an
`automatic process identifier configured to identify a process
`split ofthe device, amemory circuit coupled to the automatic
`process identifier, the memory circuit configuredto store data
`comprising target voltages for different processsplits, a pro-
`cessing unit, a power supply, and a voltage regulator circuit
`coupled to the memory circuit and to the power supply, the
`regulator configured to adjust the power supply value accord-
`ing to the automatic process identifier and the memory circuit,
`the adjusted power supply causing the processing unit to
`operate substantially at a target frequency.
`In yet another aspect of the invention, a methodof regulat-
`ing supply voltage of an integrated circuit device using a ring
`oscillator circuit for measuring frequencies corresponding to
`different voltages includes recording ring oscillator frequen-
`cies for different voltages at a plurality of process splits asso-
`ciated with a family ofsilicon devices in which the integrated
`circuit device is included, each ofthering oscillator frequen-
`cies corresponding to a target frequency of operation for a
`processing unit on the integrated circuit device, the voltages
`and corresponding frequencies comprising respective sets of
`characterization data for each process split, measuring, for
`the different voltages, an additionalset of frequencies output
`from a ring oscillator on the integrated circuit device, identi-
`fying the two sets of characterization data representing two
`process
`splits having performance characteristics most
`closely above and below the performance characteristics
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`characterized by the additional frequencies at the different
`voltages measured for the integrated circuit device, interpo-
`lating between the identified two sets of characterization data
`using the additional frequenciesto identify a third set of data
`characterizing the integrated circuit device and comprising
`supply voltages necessary to achieve the correspondingtarget
`operating frequencies, and regulating the supply voltage to
`achieve thetarget frequencies using the supply voltages from
`the third set.
`
`In yet another aspect of the invention, a voltage regulation
`apparatus for use in an integrated circuit device includes a
`processing unit, an identifier circuit configured to identify a
`process split for the integrated circuit device, a memory cir-
`cuit coupled to the identifier circuit, the memory circuit con-
`taining characterization data for the identified process split, a
`critical path replica circuit comprising an output for provid-
`ing frequency information approximating a critical path of
`the integratedcircuit, a switch coupled to the memory circuit
`and the output ofthe critical path replica circuit, and a voltage
`regulator circuit coupled to the switch anda supply voltage of
`the integrated circuit device, the regulator circuit configured
`to adjust the supply voltage to achieve a desired target fre-
`quencyof the processing unit.
`In yet another aspect of the invention, computer readable
`media embodying a program ofinstructions executable by a
`computer program to perform a methodofregulating a supply
`voltage of an integrated circuit device includes determining a
`process split for the integrated circuit, associating a plurality
`ofvoltages to the process split, each voltage corresponding to
`a target frequency of operation of a processing unit on the
`integrated circuit, and regulating the supply voltageto attain
`one of the target frequencies for a processing unit on the
`integrated circuit using a corresponding oneofthe voltages
`associated with the determined process split.
`In yet another aspect of the invention, an integrated circuit
`device includes a processing unit, process identification
`meansfor identifying the process split of the integrated cir-
`cuit, memory meansfor storing characterization data of the
`family of integrated circuit devices to which the integrated
`circuit device belongs, means for determining the character-
`ization datafor the integrated circuit device using the memory
`meansand the processidentification means, and voltage regu-
`lation meansfor adjusting the supply voltage using the char-
`acterization data for the integrated circuit device to achieve a
`desired target frequency of operation for the processing unit.
`It is understood that other embodiments of the present
`invention will becomereadily apparent to those skilled in the
`art from the following detailed description, wherein it is
`shown and described only several embodimentsof the inven-
`tion by wayofillustration. As will be realized, the invention
`is capable ofother and different embodiments andits several
`details are capable of modification in various other respects,
`all without departing from the spirit and scopeofthe present
`invention. Accordingly, the drawings anddetailed description
`are to be regardedas illustrative in nature and notasrestric-
`tive.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Aspects of the present invention are illustrated by way of
`example, and not by wayoflimitation, in the accompanying
`drawings, wherein:
`FIG. 1 is a block diagram of a dynamic voltage scaling
`architecture.
`
`FIG. 2 is a block diagram of an architecture of the voltage
`regulation system in accordance with an embodiment of the
`present invention.
`
`

`

`US 7,583,555 B2
`
`5
`FIG. 3A is a ring oscillator look-up table in accordance
`with an embodimentof the present invention.
`FIG.3B is amain look-up table containing characterization
`data in accordance with an embodimentofthe present inven-
`tion.
`
`FIG. 4 is a graph showing a Gaussian distribution of a
`semiconductoryield.
`FIG.5 is a ring oscillator in accordance with an embodi-
`mentof the present invention.
`FIG.6 is an illustration of a silicon die including a core
`processor and a group ofring oscillators in accordance with
`an embodimentof the present invention.
`FIG.7 is a circuit configured to produce a direct measure-
`mentof on-die ring oscillators in accordance with an embodi-
`mentof the present invention.
`FIG. 8 is a circuit configured to produce a relative mea-
`surement of an on-die ring oscillator in accordance with an
`embodimentof the present invention.
`FIG. 9 is a graph of processing frequency versus ring
`oscillator frequency at room temperature in accordance with
`an embodimentof the present invention.
`FIG. 10A is a table showing characterization data at two
`process splits in accordance with an embodiment of the
`present invention.
`FIG. 10B is a table showing characterization data of a
`candidate integrated circuit device in accordance with an
`embodimentof the present invention.
`FIG. 11 is a graph showing characterization data for a
`family of integrated circuit devices and a device undertest, in
`accordance with an embodimentofthe present invention.
`
`DETAILED DESCRIPTION
`
`The detailed description set forth below in connection with
`the appended drawingsis intendedas a description of various
`embodiments of the present invention andis not intended to
`represent the only embodiments in which the present inven-
`tion may be practiced. Each embodiment described in this
`disclosure is provided merely as an example orillustration of
`the present invention, and should not necessarily be construed
`as preferred or advantageous over other embodiments. The
`detailed description includes specific details for the purpose
`of providing a thorough understanding ofthe present inven-
`tion. However, it will be apparent to those skilled in the art
`that the present invention may be practiced without these
`specitic details. In some instances, well-knownstructures and
`devices are shown in block diagram form in order to avoid
`obscuring the concepts of the present invention. Acronyms
`and other descriptive terminology may be used merely for
`convenience andclarity and are not intendedto limit the scope
`of the invention. For the purposes of this disclosure, the term
`“coupled” mayrefer to either a direct connection or, where
`appropriate in the context, a connection through intermediary
`circuitry or means.
`Dynamic Voltage Scaling (DVS) can save power by low-
`ering the supply voltage whenparts are running faster than
`required. This phenomenoncan occur, for example, for fast
`process splits from a silicon wafer yield, or operation of the
`integrated circuit device at cool temperatures. Performance
`can also be dictated by software, such as wherethefull target
`frequency of operation is not required in light of an impend-
`ing application that may be less-computationally intense than
`the circuit is capable of handling. For faster processsplits,
`parts can run at higher frequency and hence waste unneces-
`sary power. The DVSaccording to the present invention can
`lower the voltage automatically for these faster parts and
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`thereby conserve battery power while still maintaining,
`across all variables, the desired performancetarget.
`FIG. 1 showsan illustrative block diagram of a dynamic
`voltage scaling system architecture 100. The performance
`manager 102 may be implementedas a software or firmware
`routine onthechip, or it may be included in a dedicated circuit
`or set of circuits. The performance manager 102 may use a
`software user interface to predict performance requirements
`and to convey information, in some configurations, to a user
`or another circuit or device. Once performance requirements
`for the impending task are determined by the performance
`manager 102, the performance manager 102 sets the supply
`voltage and frequency of the chip just necessary to accom-
`plish the identified task(s). The target frequencyf,,,.¢, iden-
`tified by the performance manager 102 is transmitted to a
`phase-locked loop (PLL) 104 over path 114 to accomplish
`frequency scaling. Thatis, the PLL 104 tracksthe input f,,,.¢2
`value and outputs an appropriate operating frequency for use
`by the on-chip CPU 106. Further, based onthe target voltage
`Viarger Sent by the performance manager 102 to the voltage
`regulator circuitry 108 via line 112, the voltage regulator 108
`scales the supply voltage to meet this target, as shown byline
`110.
`
`The performance manager, which can be implemented
`using a variety of known configurations, may adjust the sup-
`ply voltage according to performance requirements. Such
`requirements will vary dramatically depending on the par-
`ticular application. In addition, more than one processing unit
`may reside on the samesilicon device. In this instance, the
`performance manager may regulate the operating character-
`istics of more than one processor. In other implementations,
`more than one performance manager may be used.
`In one open-loop performance manager configuration,
`voltage setting by the performance manager can bea one-time
`setting based on the entries contained within a lookup table
`(LUT). Alternatively, voltage setting can be based on the
`actual system performance as tracked by the performance
`manager. In implementations utilizing an LUT,differenttar-
`get operating frequencies along with the correspondingvolt-
`age supply settings may be used to set the voltage to the
`optimal value for minimizing power consumption. The LUT
`entries may be determined through characterization of the
`behaviorofthe silicon device at various extremes. In design-
`ing these characterization methodologies, sufficient margin
`should be added to the voltage supply to accommodate for
`worst case process and temperature variations. When the
`target voltage is set for a given application, an analog-to-
`digital converter (ADC) maybe used to indicate when the
`voltage regulator has completed its voltage adjustment.
`Another performance manager configuration involves a
`closed-loop feedback system. Actual system performance
`may be measuredusingeither a ring oscillator or a replica of
`the critical path of the processing circuitry. Using this con-
`figuration, when system performance requires a change, the
`performance managersets the target frequency. The error
`betweenthe target and the measured frequencies is used by a
`feedback system to adjust the voltage to achieve the target
`performance.
`Whether an open or closed-loop system performance
`monitoring system is chosen depends on a numberoffactors.
`Stability against temperature is a significant design param-
`eter. The conventional LUT DVSstores the worst case per-
`formance numbers. In this event, operation under worst case
`process variation is ensured and temperature stability is guar-
`anteed. Unfortunately, the large margin added to compensate
`for process and temperature variations can reduce energy
`
`

`

`US 7,583,555 B2
`
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`where V,,, 1s the supply voltage, 1(T) is the channel mobility
`at temperature T, and V,,,(T) is the threshold voltage at zero
`bias and at temperature T. Channel mobility and threshold
`voltage dependence on temperature can be represented as
`follows:
`
`aT) = MTT)
`
`and
`
`Vru(P) = Vrr(To) — KT — To)
`
`8
`In certain implementations, calibration may be accom-
`plished by fixing the voltage of the environment adjacent and
`within the integrated circuit to a specific value where circuit
`performance is insensitive to temperature. Generally, when
`temperature changes, the performance of logic path on a
`silicon device such as aCMOScircuit is affected by two main
`parameters:
`threshold voltage and channel mobility. Fre-
`quency at which a logic path can operate is approximated by
`
`7
`savings significantly. Various aspects of the present invention
`address this shortcoming, as discussed below.
`In a configuration where actual system performance is
`monitored, the system dynamically compensates for tem-
`perature variation using a closed-loop feedback system.
`Closed loop parameters and system response determine the
`time required by the closed loop to adjust voltage in response
`to an arbitrary temperature change. If the rate of change of
`temperature is faster than the closed-loop responsetime, the
`voltage regulatorin this instance needs to temporarily depart
`from the closed-loop feedback system and ramp upthe volt-
`age to its worst case setting. The worst case setting may
`correspondto the worst case process and worst case tempera-
`ture in order to guarantee the integrity of operation overall
`ranges. This panic mode—namely, where voltage must be
`changed to guarantee the maximum performance underall
`circumstances—mayresult in unacceptable consumption of
`battery power, and has not been addressed properly in con-
`ventional closed loop systems.
`In one aspect ofthe present invention, a hybrid open/closed
`loop voltage regulator is disclosed. The voltage regulator
`includes mechanisms for one-time voltage setting and con-
`tinuous performance monitoring. The disclosed voltage regu-
`lator may save significant amounts of energy by automati-
`cally identifying the process ofthe silicon device. Once the
`process is identified, the system selects supply voltage and
`operating frequency data points which correspond notto the
`worst case process split, but to the process split identified.
`Once the voltage reaches the target value as dictated by the
`LUT, the system starts monitoring the system performance
`using a closed-loop feedback system. In some configurations,
`the system monitorsa critical path for temperature variations,
`and adjusts the supply voltage accordingly. Other implemen-
`tations involvetheuseof a critical path replica for performing
`this “fine tuning”of the supply voltage after the initial setting
`where T,_300K, M is the mobility temperature exponent, and
`by the open-loop system. During panic mode, the system
`k is the threshold voltage temperature coefficient. Typical
`switches back to consulting the entries in the LUT and ramps
`values for M and k are 1.5 and 1.8 mV/K,respectively.
`up the supply voltage to the maximum specified according to
`The aboverelationships reflect that, by lowering the supply
`the particular split.
`voltage, the temperature effect on threshold voltagestarts to
`Accordingly, in one embodiment, the disclosed system
`cancel out the temperature’s effect on channel mobility. A
`operates in two distinct configurations: LUT modeandper-
`specific voltage is reached where logic performance becomes
`formance monitoring mode. An initial calibration step may be
`insensitive to temperature. Becausethe effect of temperature
`implementedfor a particular silicon device. During this cali-
`has been cancelled out, the only influence on performance
`bration step, some mechanism may be used to identify the
`relates to process variations. As a result, this voltage can be
`specific process corner to which the chip belongs. When
`usedto identify the process split for the device at issue.
`performance needs to be adjusted, the system commences
`Referring back to FIG.2, the voltage V,,,, supplied to the
`operation using the LUT configuration. Once voltage is
`API 202 is set to its temperature insensitive value, using in
`adjusted according to the values dictated in the LUT, the
`one embodimentthe equations above. The API 202 includes
`system switches to performance monitoring modeto fine tune
`a ring oscillator 204 which outputs a signal at a frequency
`performance and to compensate dynamically for temperature
`variations.
`specific to that temperature insensitive voltage. A counter 206
`in some implementations reads the frequency of the ring
`FIG. 2 shows a block diagram of the architecture of a
`oscillator 204. The counter 206 is coupled to a small ring
`voltage regulator system 200 in accordance with an embodi-
`oscillator look-up table (RO LUT) 208. The look up table 208
`ment ofthe present invention. An automatic process identifier
`circuit (API) 202 may be usedto identify the process corer
`may contain entries characterizing the various processsplits
`
`during the calibration step. The API may includearing oscil- at the voltage-insensitive temperature. In one embodiment,
`lator circuit 204, a counter 206, and a ring oscillator look up
`the table 208 has only the numberofentries corresponding to
`table (RO LUT) 208. The API 202 may be used to accomplish
`the numberofsplits to be considered. Thering oscillator look
`automatic process
`identification. However,
`temperature
`up table may be indexedbythering oscillator frequency from
`variations mayaffect the correct determinationofthe process
`the counter 206 as indicated by the exemplary ring oscillator
`split in measuring a particular device. Process variations and
`look up table in FIG. 3A. The first entry in the look-up table,
`temperature are typically the main factors affecting integrated
`Vscarp represents the calculated value ofvoltage insensitive
`circuit performance. For example, a slow process split at a
`to temperature. The remainderof the entries may be indexed
`cold temperature may be faster than a typical split at a hot
`by the ring oscillator frequency. In the example of FIG. 3A, a
`temperature. The API 202 should be designed so that an
`first output ring oscillator frequency f,, corresponds to PRO-
`accurate process split determination can be made without
`CESS, (e.g., slow), a second output ring oscillator frequency
`regard to temperature.
`f, corresponds to PROCESS,(e.g., typical), and so on. In
`
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