United States Patent
`(12)
`(10) Patent No.:
`US 6,535,735 B2
`Underbrinket al.
`(45) Date of Patent:
`Mar. 18, 2003
`
`
`US006535735B2
`
`(54) CRITICAL PATH ADAPTIVE POWER
`CONTROL
`
`(75)
`
`Inventors: Paul A. Underbrink, Lake Forest, CA
`(US); Daryush Shamlou, Laguna
`°
`i
`\.
`De
`Niguel, CA (US); Ricke W.Clark,
`Invine, (CA (US); Josepht H:'Colles,
`Bonsall, CA (US); Guangming Yin,
`Foothill Ranch, CA (US); Patrick D.
`Ryan, Yorba Linda, CA (US); Kelly H.
`Hale, Aliso Viejo, CA (US)
`(73) Assignee: Skyworks Solutions, Inc., Irvine, CA
`(US)
`
`5,166,959 A * 11/1992 Chuetal. wee 377/20
`
`5,264,745 A * 11/1993 WoO vceccseccssssseeseeeseees 307/475
`5,327,131 A *
`7/1994 Ueno etal. we. 341/136
`5,438,259 A :
`8/1995 Orihashi et ale cece 324/158
`
`9/1995 Shin et al. oc 327/525
`5,450,030 A
`5,457,719 A * 10/1995 Guo et al. 375/373
`6,121,758 A *
`9/2000 Bellina et al. wees 323/211
`6,204,650 Bl *
`3/2001 Shimamori et al. ....... 323/283
`
`* cited by examiner
`
`Primary Examiner—Rajnikant B. Patel
`74) Attorney, Agent, or Firm—Foley & Lardner
`(74)
`Dare
`:
`(57)
`
`ABSTRACT
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`Modern digital integrated circuits are commonly synchro-
`nized in their workings by clock circuits. The clock fre-
`quency for a circuit must take into account the propagation
`delay of signals within the critical path of the circuit. If the
`clock time is not adequate to allow propagation of signals
`(21) Appl. No.: 09/814,921
`through the critical path, improper circuit operation may
`=
`phe
`Noe
`?
`result. The propagation delay is not a constant from circuit
`(22)
`Filed:
`Mar. 22, 2001
`to circuit, and even in a single circuit may change due to
`(65)
`Prior
`Publication Dat
`:
`ior Publication
`Data
`temperature, power supply voltage and the like. Commonly,
`this variation is handled by assuming a worse case propa-
`US 2002/0135343 A1 Sep. 26, 2002
`gation delay ofthe critical path, and then designing the clock
`7
`frequency and minimum powersupply voltageofthe circuit
`Int. Ch? oe H04Q 7/20; HO3K 5/159
`(51)
`so that the circuit will function under worst case conditions.
`(52) US. Ch. cece 455/432; 307/591; 323/283
`Ilowever, instead of assuming a worse case propagation
`(58) Field of Search oo... 323/283, 282,
`delay of the critical path,
`the propagation delay may be
`323/280, 211, 267, 273; 307/591, 603,
`measured in an actual circuit path that has been constructed
`303; 363/65, 71, 95, 97; 327/525; 379/61,
`to be the equivalent to, or slightly worse than, the propaga-
`62; 455/69, 89, 432, 466, 550
`tion delay of the critical path. By knowing the actual worst
`.
`case propagation delay,
`the circuit may be modified to
`References Cited
`operate with lower power supply voltages, conserving
`U.S. PATENT DOCUMENTS
`powerand/or to controlling the frequency of the clock, so
`~~
`that the clock may be operated at or near the circuit’s actual,
`1/1978 Gyugyi oc 323/211
`4,068,159 A *
`
`not theoretical worst case limit. Such modifications of power
`2/1979 Rudiset al.
`4,137,776 A *
`supply voltage and/or clock frequency may occur during
`1/1981 Hoffman wesc 307/238
`4,245,165 A *
`6/1986 weesbsdesttiestetenetieets 73).2 circuit operation and thus, adapt the circuit to the different
`4,596,143 A :
`os ae operating parameters of each circuit.
`ices te “
`tecetat ‘ “
`
`cscs. 307/591
`4,980,586 A * 12/1990 Sullivan et al.
`5,047,664 A *
`9/1991 Moyal wees 307/303
`
`18 Claims, 9 Drawing Sheets
`
`/
`(56)
`
`SPEAKER
`
`ANTENKA
`203
`201
`207
`205
`205\
`\
`\ \
`
`
`\ 5
`
`+
`BROADCAST
`
`
`
`CIRCUITRY.
`PPOR
`
`
`
`
`rans
`
`
`
`
`
`228
`
`
`
`
`200
`
`213
`
`CLOCK
`219
`
`DISPLAY
`
`20
`ef
`18
`
`|
`
`
`
`
`MICROPHONE
` REGULATOR
`
`
`
`BATTERY
`
`
`3700
`JOO 21
`Joo
`
`aes
`
`INTEL 1009
`
`INTEL 1009
`
`

`

`U.S. Patent
`
`Mar. 18,2003
`
`Sheet 1 of 9
`
`US 6,535,735 B2
`
`01
`
`203
`
`ANTENNA
`
`205 BROADCAST a
`DUPLEXOR
` DIGITAL
`DISPLAY KEYPAD
`
`SPEAKER
`
`207
`
`CIRCUITRY
`
`CIRCUITRY
`
`
`
`FIG. 1
`
`

`

`U.S. Patent
`
`Mar.18, 2003.
`
`‘Sheet 2 of 9
`
`US 6,535,735 B2
`
`307
`
`311
`
`315
`
`301
`
`303
`INPUT
`
`305
`
`309
`
`313
`
`FIG. 2
`
`317
`
`1.
`
`303
`
`307
`
`311
`
`315
`
`AMPLITUDE
`
`TIME
`
`

`

`U.S. Patent
`
`Mar. 18, 2003
`
`Sheet 3 of 9
`
`US 6,535,735 B2
`
`
`
`vl
`
`AMPLITUDE
`
`PD#419
`
`PD#411
`
`PD#413
`
`|
`
`TIME
`
`401
`
`413
`
`411
`
`4l5
`
`FIG. 5
`
`

`

`U.S. Patent
`
`Mar. 18, 2003
`
`Sheet 4 of 9
`
`US 6,535,735 B2
`
`501 POWER SUPPLY VOLTAGE
`
`Vmax
`
`503
`
`Vain
`
`505
`
`515
`
`fo
`
`CIRCUIT #
`nN
`
`
`
`
`CIRCUIT #
`509
`
`CIRCUIT #
`907
`
` GATE DELAY TIME
`
`913
`
`FIG. 6
`
`

`

`U.S. Patent
`
`Mar. 18,2003
`
`Sheet 5 of 9
`
`US 6,535,735 B2
`
` 600
`
`INPUT
`
`603
`
`FIG. 7
`
`613
`
`615
`
`601
`
`Vt
`
`WM
`
`io
`\
`|
`
`601
`
`1
`foro |
`
`oo
`1
`
`609
`
`609
`
`61) ws
`
`611 aa
`
`SHORTER
`MAXIMUM PROPAGATION DELAY
`
`LONGER
`MAXIMUM PROPAGATION DELAY
`
`FIG. 8
`
`

`

`U.S. Patent
`
`Mar. 18, 2003.
`
`Sheet 6 of 9
`
`US 6,535,735 B2
`
`iF MAXIMUM -
`PROPAGATION F-©
`DELAY
`701
`713
`
`
`
`INPUT TL ENABLE—|CONVERT703
`
`
`
`COUNTER
`
`
`
`717
`719
`COUNT
`723
`QUTPUT
`
`715“
`CLOCK
`
`FIC 9
`
`725
`
`727
`
`709
`
`709
`
`SHORTER
`MAXIMUM PROPAGATION DELAY
`
`LONGER
`MAXIMUM PROPAGATION DELAY
`
`FIG. 10
`
`

`

`U.S. Patent
`
`Mar. 18,2003
`
`Sheet 7 of 9
`
`US 6,535,735 B2
`
`
`
`
`VOLTAGE
`REGULATOR
`
`
`DIGITAL
`
`ELECTRONICS
`
`
`
`
`
`DELAY
`
`MEASUREMENT
`CIRCUIT
`
`
`807
`
`FIG. 11
`
`

`

`U.S. Patent
`
`Mar. 18, 2003
`
`Sheet 8 of 9
`
`US 6,535,735 B2
`
`913
`
`901
`
`903
`
`905
`
`907
`
`909
`
`911
`
`FIG. 12
`
`

`

`U.S. Patent
`
`Mar. 18, 2003.
`
`Sheet 9 of 9
`
`US 6,535,735 B2
`
`1001
`
`CIRCUIT
`# 1003
`
`eRe
`#1007
`
`CIRCUIT
`#1005
`
`PIRCUIT
`# 1009
`
`DELAY CIRCUIT #1019
`
`MEASUREMENTCIRCUITS
`
`DELAY CIRCUIT #1013
`DELAY CIRCUIT #1015
`
`DELAY CIRCUIT #1017
`
`FIG. 13
`
`

`

`US 6,535,735 B2
`
`1
`CRITICAL PATH ADAPTIVE POWER
`CONTROL
`
`BACKGROUND OF ‘THE INVENTION
`
`1. Field of the Invention.
`
`The invention relates to personal communications sys-
`tems that minimize powerdissipation by controlling power
`supply voltage and clock frequency.
`2. Related Art.
`
`10
`
`2
`supply voltage, the more power will be dissipated when the
`device switches. Digital devices also tend to switch faster at
`higher power supply voltages. For the forgoing reasons,
`manufacturers of digital circuits, particularly in the case of
`portable applications, may find it advantageous to design
`circuits with the slowest possible clock rate at the lowest
`possible power supply voltage. Circuits designed for the
`slowest possible clock rate and the lowest possible power
`supply voltage are commonly submitted to a design method
`called worst case analysis.
`In a worst case analysis, the circuit variables are assumed
`to be skewedso as to provide the worst conditionsfor circuit
`operation. For example, if a minimum clock rate of 1 MHz
`weredesired, it would be assumedthat the power supply was
`at it’s lowest(i.e. worst case) operating voltage. If the worst
`case voltage could support a 1 MHz operation,
`then the
`reasoning is, higher operating voltages could support oper-
`ating frequencies greater than 1 MHz because increasing
`power supply voltage generally tends to allow digital
`devices to switch faster. Operating voltages higher than the
`worst case minimum could support clock rates above 1
`MHz. Worst case design assumesthat all parameters are at
`their worst, and then calculates parameters, such as operat-
`ing voltage, to determine what minimum value of operating
`voltage will guarantee that the circuitry will continue to
`function.
`
`A problem with worst case design is that worst cases
`rarely, if ever occur. The worst case actually may have only
`a statistically infinitesimal chance of occurring, and be
`unrealistic in practice. Because circuitry may be designed
`for the case, the worst case, that may not ever occur the
`circuitry does not operate as efficiently as if it had been
`designed for normal operating conditions. In some cases,
`circuitry designed for normal conditions could be operated
`moreefficiently at lower power supply voltages than a worst
`case design would indicate is possible. Thus,a circuit design
`for operation under worst case conditions may not result in
`the most efficient design.
`SUMMARY
`
`Dynamically adjusting the power supply voltage and
`clock frequency of digital circuitry, may be particularly
`useful in powersensitive applications. Worst case design for
`digital circuits may be calculated based on propagation time
`within the digital circuits. Propagation time is commonly
`defined as the time that a signal takes to travel through a
`digital circuit and to become stable at the output of the
`circuit. In general, digital circuits are synchronouscircuits,
`typically synchronized by means of a clock. A clock func-
`tions to synchronize the changingofdigital values within the
`circuit. A clock cycle may be commonly divided into two
`different portions. The first, or active, portion of the clock
`cycle is when signallevels are inputinto to a circuit. During
`the active portion of the clack cycle, it is commonto refer
`to the values as being clocked into the circuit.
`The second portion,or settling portion, of the clock cycle
`is the time period when no signals are input to the circuit.
`During the settling portion of the clock cycle, the signals,
`that were presented to the inputs of the circuit during the
`active portion of the clock cycle, propagate through the
`circuits. At the end ofthe settling portion of the clock cycle,
`
`15
`
`°
`
`Portable electronic devices have become part of many
`aspects of personal, business and recreational activities and
`tasks. The popularity of various portable personal electronic
`communications systems, such as portable phones, portable
`televisions, and personal pagers, continues to increase. As
`the popularity of portable electronic systems has increased,
`so has the demand for smaller, lighter and more power
`efficient devices, that may operate for longer periods of time.
`Manufacturers continually try to increase the time a portable
`device mayoperate on a set of batteries or between battery
`charges. Increased time between battery charges or changes
`may be a significant marketing advantage.
`Manufacturers have attempted to increase operational
`time of portable devices by producing batteries with higher
`energy densities, and attempting to produce circuitry that
`consumes less power. A benefit of reduced power
`consumption, in addition to an increase in operational time,
`is an increased reliability due to reduction of temperature
`increasesin the devices during operation. Reduced operating
`temperatures are generally a consequence of reduced power
`dissipation.
`One method to reduce power consumption is to employ
`digital designs. One reason for replacing analog communi-
`cation systems with digital communications systemsis that
`digital systems, generally may offer increased performance
`and lower overall power consumption than those of analog
`systems. Digital systems may dissipate less power than
`analog systems because digital systems typically operate
`using only twodistinct values, ones and zeroes. These values
`are commonly created by semiconductors that are in a
`saturated state or a cut off state. In the saturation state,
`current flows through the device, but the voltage across the
`device is low. Powerdissipated is equal to the voltage across
`the device multiplied by the current flowing through the
`device. The power dissipated by a device in the saturation
`state is equal to the amount of current flowing through the
`device multiplied by the saturation voltage. Because the
`saturation voltage across the device is low, the poweris also
`low. In the cut off state, the voltage across a device isusually ;
`at a maximum. The current through the device, however,is
`low and may commonly be zero or a low leakage value.
`Because the cut off current is low, the powerdissipated in the
`device is also low. Digital circuits commonly are in either a
`cutoff or saturation state during operation, except for the
`times when they are switching betweenstates.
`Generally, digital devices dissipale most of their power
`during the period when they are switching states. The
`amount of power dissipated during switching is generally
`dependent on the voltage of the power supply that powers
`the digital devices. In other words, the higher the power
`
`40
`
`45
`
`60
`
`65
`
`

`

`US 6,535,735 B2
`
`3
`all signals should have propagated through the circuit and
`becomestable. If the settling time portion of the clock cycle
`is not sufficiently long, some signals maybestill propagat-
`ing through the circuit at the end ofthe settling time portion
`of the clock cycle and may not be stable at the end of the
`settling time. If signals are still changing when the active
`portion of the clock cycle occurs, incorrect values may be
`coupled into circuit inputs. If the settling time of the clock
`cycle is not long enough, the circuit input values that are
`being coupled from one circuit
`to another may still be
`changing whenthe active portion of the clock cycle arrives.
`If conditions are such that input values are changing,
`whenthe active portion of a clock cycle occurs, the condi-
`tion is commonly knownas a “race.” Race conditions exist
`when the propagation delay, i.e. the time a signal takes to
`travel through a circuit, exceeds the settling time portion of
`the clock cycle. When a race condition exists the perfor-
`mance of the circuit may be degraded, and the circuit may -
`be unpredictable or may even be inoperativefor its intended
`purpose. To avoid problems due to inadequate settling time,
`the settling time of the clock circuit must be long enough to
`avoid all circuit races. To avoid a race condition within a
`
`10
`
`15
`
`4
`FIG. 3 is a graphical illustration of a pulse signal wave-
`form propagation through the circuit of FIG. 2.
`FIG. 4 is a block diagram illustrating divergent circuit
`paths for electronic signals.
`FIG. 5 is a graphical illustration of wavetorm propagation
`delays in the circuit of FIG. 4.
`FIG. 6 is a graphical illustration of variations of gate
`delays in different circuits having different power supply
`voltages.
`TIG. 7 is a circuit diagram of a propagation delay mea-
`surement mechanism.
`
`FIG. 8 is a series of graphs illustrating signal waveforms
`during the operation of the circuit of FIG. 7.
`FIG. 9 is a circuit diagram of a circuil delay measurement
`mechanism.
`
`FIG. 10 is a series of graphsillustrating signal waveforms
`during the operation of the circuit of FIG. 9.
`FIG. 11 is a block diagram illustration of a digital circuit
`in which the clock is controlled by a circuit delay measure-
`ment mechanism.
`
`FIG. 12 is an block diagram illustrating a delay measure-
`ment circuit that may be used with either variable power
`supply voltage or variable clock frequency.
`FIG. 13 is block diagramillustrating a digital electronic
`circuit with subcircuits and delay paths.
`DETAILED DESCRIPTION
`
`This invention relates to power dissipation within syn-
`chronousdigital circuits. In particular, the invention relates
`to powerdissipation within wireless digital systems, such as
`wireless communication devices. In many wireless commu-
`nications applications, it is desirable to reduce the power
`dissipation within the internal electronics of the portable
`units. One result of reduced power dissipation may be
`increased talk time between battery recharges.
`FIG. 1 is a block diagram illustrating an cxample implc-
`mentation in hardware of a cellular phone 201. The phone
`201 has a microphone 217, for receiving a user’s voice. The
`microphone 217 is coupled to an analog to digital converter
`215 capable of converting voice signals to a digital signal for
`processing within the digital circuitry 211. The digital signal
`is processed and is then coupled by broadcastcircuitry 207
`that encodes the digitized voice signal, modulates a carrier
`signal based on the voice information, and amplifies the
`modulated signalfor broadcast. The modulated signalis then
`coupled into a duplexor 205 that transmits the signal to the
`antenna 203 for broadcasting.
`The antenna 203 is also used for receiving incoming
`signals. The incoming signals received by the antenna 203
`are conveyed to the duplexor 205 and then further coupled
`by the duplexor 205 to the digital circuitry 211. The digital
`circuitry 211 demodulates and processes the received signal
`and presents a representation of the voice signal to a digital
`to analog converter 209. The digital to analog converter 209
`changesthe signal into an analog form that is then presented
`to an amplifier 225 for amplification. The amplified signal
`from the amplifier 225 is then coupled into a speaker 229
`where sound waves are produced for perception by the user.
`The cellular phone 201 also contains a keypad 221 for
`entering commands. The cellular phone 201 also contains a
`
`,
`
`40
`
`45
`
`the circuit clock may be slowed to allow more °
`circuit,
`propagation time for the signals in the circuit, or the propa-
`gation speed of the signal
`through the circuit may be
`increased. Increasing the power supply voltage of a digital
`circuit will generally increase the speed of signal propaga-
`tion through that circuit.
`The propagation speed of a circuit may be changed by
`adjusting the power supply voltage in order to adjust the
`propagation speed of signals in the circuit, for example, to
`avoid race conditions. By actively measuring the propaga-
`tion delay of signals through a circuit, and adjusting the
`powersupply voltages accordingly, a circuit design may be
`free from the constraint of selecting the power supply
`voltage for a theoretical worst case signal propagation time.
`Instead of designing the circuit for the theoretical worst case
`propagation time, the speed of propagation may be dynami-
`cally adjusted to match the actual propagation time within a
`circuit. By setting the power supply, in order to achieve the
`propagation speed needed, circuitry may be run at lower
`voltages. By running circuitry at
`lower voltages than a
`theoretical worst case, power dissipation may be lowered.
`Other systems, methods, features and advantages of the
`iovention will be or will become apparent to one with skill
`in the art upon examination of the following figures and
`detailed description. It is intended that all such additional
`systems, methods, features and advantages be included
`within this description, be within the scope of the invention,
`and be protected by the accompanying claims.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The components in the figures are not necessarily to scale,
`emphasis instead being placed upon illustrating the prin-
`ciples of the invention. Morcover, in the figures, like refer-
`ence numerals designate corresponding parts throughout the
`different views.
`
`FIG. 1 is a block diagram of hardware for a cellular
`telephone.
`FIG. 2 is a block diagram of propagation delay digital
`circuit.
`
`60
`
`65
`
`

`

`US 6,535,735 B2
`
`6
`5
`coupled to input 303 of the buffer string, must elapse before
`display 219 for communication of phone parameters to a
`that signal is available at the output 315 of the buffer string.
`user. The cellular phone 201 also contains a power source
`such as a battery 223 for powering the clectronic compo-
`Anattempt to couple the signal output 315 of the buffer
`nents within the phone. Also provided is a clock circuit 213
`string to a succeeding circuit before the propagation time,
`that provides the clocking signals for the digital circuitry
`Tp, has elapsed will result
`in an incorrect value being
`211. The cellular phone 201 maycontain a regulator 227 for
`coupled to the succeeding circuit because the waveform 301
`regulating the power supply voltage received by the digital
`has not had the time to propagate through the chain. The
`circuitry 211.
`total propagation delay is dependent on how manylevels of
`circuitry the signal must travel through before reaching an
`The voltage output of the regulator 227 that powers the
`output. If there are more buffers in a chain, the propagation
`digital circuitry 211 is adjusted depending uponthe circuitry
`delay increases. Conversely, removing a buffer fromaseries
`conditions in order to conserve battery 223 energy. By
`of buffers, decreases the propagation delay of the series of
`adjusting the power supply voltage of the digital circuitry
`buffers by an amount equal to the propagation delay of the
`211, power consumed by digital circuitry 211 may be
`removed buffer.
`decreased, and the operating time between battery charges or
`replacements may be increased. The frequency of the clock
`213 that synchronizes the digital circuitry 211 may be
`adjusted depending uponthe circuitry conditions,in order to
`permit lower power supply voltages to be used without
`incurring races within the digital circuitry 211. A combina-
`tion of regulator output voltage and clock frequency adjust-
`ments may be made to conserve power, depending on the
`circuitry conditions in order to conserve power.
`The propagation delay of signals through digital circuitry 2
`is affected by many parameters. The material that makes up
`the digital devices affects the propagation speed of signals
`through the digital circuitry. The propagation speed of
`signals through the circuitry is also affected by the circuitry
`temperature, power supply voltage, fabrication variables,
`packaging variables, and other factors. It may be difficult to
`handle quantitatively the myriad of variables present in a
`system. Because of the difficulty in handling multiple
`variables, simplifying worst case assumptions, such as abso-
`lute maximum and minimum values,are often made. Digital
`circuits may be designed to meet a worst case specification,
`using such simplifying assumptions. A worst case specifi-
`cation may be overly pessimistic however, and individual
`circuits may often operate adequately under conditions that
`exceed the “worst case” specifications.
`FIG. 2 is a block diagram illustration of propagation delay
`within a circuit. FIG. 2 illustrates a string of commondigital
`buffers, 305, 309, and 313 arranged in a series connection.
`FIG. 3 illustrates a pulse signal waveform propagation
`through the circuit of FIG. 2. A pulse signal waveform 301
`is coupled into the input 303 of the first buffer 305, at time
`t,. The signal travels through the circuitry of the first buffer
`305 and al lime L, appears al the output 307. The signal is
`then transmitted to the input of the second buffer 309. The
`signal travels through the circuitry of the second buffer 309
`and at time t, appears at the output 311 of the second buffer
`309. The signal travels through the circuitry of the third 5
`buffer 313 and at time t, appears at the output 315 of the
`third buffer 313.
`
`Commonly, there is more than one path that a signal may
`take through complex circuitry. There may be a plurality of
`divergent signal paths in modern complex integrated cir-
`cuits. Thus, a modem complex integrated circuit may exhibit
`various propagation delays depending upon the signal path
`in the circuit.
`
`FIG. 4 is an illustration of divergent signal paths through
`circuitry. Signal 401 is transmitted as input 403. Signal 401
`is then further transmitted through circuitry path 405, cir-
`cuitry path 407 and circuitry path 409. The graph 421 in
`FIG. 5 illustrates the various propagation delays encoun-
`tered in the circuitry of FIG. 4. Signal 411 has a propagation
`delay, PD# 411, Signal 413 has a propagation delay, PD#
`413 and Signal 415 has a propagation delay, PD# 415.
`Modem integrated circuits may have many such paths
`through which a signal maytravel. Adding complexity to the
`analysis of propagation delay is the fact that all paths may
`not alwaysbeactive. Generally, the longest path that a signal
`may take in traveling through a circuit is referred to as the
`“critical path.” The critical path is the active circuit path
`containing the longest propagation delay. Thecritical path is
`so named becauseofthecriticality of allowing enough time
`be allowed so that a signal may travel through the critical
`path. If there is enough time allowed suchthat a signal may
`safely traverse the critical path,
`then it safely may be
`assumed that cnough time has been allowedto traverse all
`the sub-critical, i.e. shorter, paths.
`Propagation delay is often measured in terms of “gate
`delays.” A gate delay is commonly defined as the amount of
`time that it takes a signal to traverse a logic gate. In other
`words, a gate delay is the propagation delay of a single gate.
`In general, the propagation delay of a simple single gate in
`an integrated circuit is considered to be essentially constant,
`no matter what type the gate is. That is an AND gate is
`considered to have essentially the same delay as an OR gale,
`that is considered to have essentially the same delay as an
`inverter, etc. Because gate delays tend to be similar, for
`simple gates, the critical path is some times referred to as
`being an integer numberof gate delays. By identifying the
`number of gate delays in the critical path for each input
`signal of an integrated circuit, the critical path for each
`signal input may be determined. If all of the critical paths of
`the circuit may be quantified in termsof gate delays, then the
`path having the largest number of gate delays becomesthe
`critical path for the entire circuit. Identifying all the signal
`paths through a circuit may be a difficult task. With the aid
`of modem computer aided design tools, the task may be
`simplified.
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`The graph 317,illustrates the timing of the appearances of
`the pulses at the input 303, of the first buffer 305, as well as
`the outputs, 307, 311, and 315, of buffers 305, 309, and 313
`respectively. The propagation time, T,, of the waveform
`301, as il propagates through the three buffers,
`is the
`difference in time between when the time when waveform
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`301 appearsat the first input 303 and the time the waveform
`subsequently appears at the third output 315. The propaga-
`tion timeis the waiting time that must elapse before a signal,
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`US 6,535,735 B2
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`By identifying the number of gate delays in a circuit’s
`critical path, a maximum clock rate may be determined. The
`maximum clock rate must allow a scttling timethat is longer
`than the propagation delay in the critical path of the circuit.
`A difficulty may arise because the longest critical path for a
`particular type of integrated circuit is commonly defined as
`an integer numberof gate delays. For each integrated circuit
`produced,the gate delay ofthat circuit is somewhatdifferent
`than other “identical” integrated circuits. Furthermore, gate
`delays will commonly vary according to the power supply
`voltage of the circuit.
`FIG. 6 illustrates example variations of gate delay for
`different circuits over differing power supply voltages.
`Graph 515 illustrates the gate delay verses voltage for 3
`circuits 507, 509 and 511. Circuit 507 is the fastest circuit,
`that
`is the gate delay propagation time, plotted on the
`horizontal axis 513, is the smallest for any power supply
`voltage between Vy, 505,
`the minimum power supply
`voltage and Vj,4+ 503, the maximum powersupply voltage.
`The power supply voltage of the circuits is plotted on the
`vertical axis 501. Circuit 511 represents the slowest circuit.
`All three circuits may be the same type of integrated circuit.
`The difference in propagation delay may be due to such
`factors as temperature, the fabrication process, or a variety -
`of other factors. It may be difficult to predict the effect of
`each factor because of imprecise circuit models, and because
`many of the factors may interact in unknown ways. It is
`however, easier to measure the effect of the factors than it is
`to predict them.
`The critical path for the circuit may be duplicated on the
`chip, gate for gate. In such a case,
`the critical path is
`emulated by a second,identical path that is duplicated on the
`chip. By duplicating the critical circuit path on the chip and;
`perhaps adding a gate delay as a safety margin, a maximum
`propagation delay circuit may be created. Because the
`maximum propagation delay circuit is created on the same
`integrated circuilas the critical propagation delay, they share
`the same process and are exposed to the same temperature,
`power supply voltage, etc., as the actual critical circuit path.
`Because the emulated propagation delay circuit contains
`similar gates and similar gate delays, the actual critical path
`of the circuit and is exposed to the same conditions as the
`emulated critical path. The maximum propagation delay of
`an emulated critical path will closely track the propagation
`delay of the actual critical path of the circuit. The delay of
`the emulated propagation delay circuit may be easily mea-
`sured and used to create an output signalthat is proportional
`to the propagation delay in the actual critical path of the
`circuit.
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`A critical path may also be simulated by fabricating a
`circuit with a number of gate delays similar to the number
`of gate delays in the critical path. Because the simulated
`propagation delaycircuit contains similar gate delays, even
`though the gates in the actual critical path are not the same,
`the overall propagation delay may closely match the simu-
`lated propagation delay. The actualcritical path ofthe circuit
`is exposed to the same conditions as the simulatedcritical
`path, and the simulated propagation delay will closely track
`the propagation delay of the critical path of the circuit. The
`delay of the simulated propagation delay circuit may be
`measured and used to create a timing signal that is propor-
`tional to the propagation delay in the critical path of the
`circuit.
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`FIG. 7 is a circuit diagram of circuit delay measurement
`mechanism that maybe used to measure propagation delay.
`FIG. 8 showsa scrics of graphsillustrating the operation of
`the delay measurementcircuit. FIG.7 illustrates an embodi-
`ment of a circuit that may be used to measure critical path
`delay by the measurement of the maximum propagation
`delay 603. The maximum propagation delay 603 may be an
`emulated critical path, a simulated critical path or the actual
`critical path. An emulated critical path would comprise a
`virtual copy ofthe critical path of the circuit. By duplicating
`the gates in the critical path, and hence the actual circuit
`delays in the critical path, an accurate measurement of the
`delay in the critical path may be made.
`A simulated maximum propagation delay 603 may pro-
`vide a delay that would be an approximate measurement of
`the gate delays in the critical path. Such a simulation could
`be fabricated by creating a circuit with the same numberof
`gate delays as the actual critical path circuit. ‘The simulated
`maximum propagation delay 603 could also be obtained by
`a variety of other methods, such as measuring the critical
`path delay and matchingit to a delay circuit, by trimming a
`delay resistor, selecting delay paths, or the like. The actual
`critical path could also be used. If the actual critical path
`were used, the path might be measured when the path were
`not in use by circuitry. That is, a test signal could be applied
`when the path were not in use. The critical path could also
`be measured when signals passed through the path in the
`course of normal operation. In the case where the critical
`path was measured when signals passed through in the
`course of normal operation, no stimulus circuitry would be
`needed. Instead, there would needto be circuitry to time the
`signal traversing the critical path.
`FIG. 7 shows how a stimulus signal might be applied to
`measure the maximum propagation delay 605 (whether
`emulated, simulated, or actual) ofthe critical path. A square
`wave 600 is coupled into the input 601 of circuit 615 and
`then becomesinput 606 of the EXCLUSIVE-OR gate 607.
`The square wave 600 may be coupled into the maximum
`propagation delay circuit 603. The square wave 600 may be
`delayed by the maximum propagation delay circuit 603. The
`delayed square wave emerges from the maximum propaga-
`tion delay circuit 603 and is coupled to input 605 of a
`comparator circuit, such as the EXCLUSIVE-OR gate 607.
`The timing of the input square wave 600 that is coupled
`to the input 606 of the EXCLUSIVE-ORgate 607, and the
`output of the maximum propagation delaycircuit 603 that is
`coupled to input 605 of the EXCLUSIVE-ORgate 607, is
`shown in graphs 613 and 615. Graph 613 illustrates a
`maximum propagation delay, that is shorter than the maxi-
`mum propagation delay, depicted in graph 615. This differ-
`ence in timing is reflected by waveform 609 representing the
`output of the EXCLUSIVE-ORgate 607. The length of the
`pulse at 609 is equal to the delay time of a signal propagating
`through the maximum propagation delay circuit 603.
`Graph 613 depicts a shorter delay time of the maximum
`propagation delay circuit 603 than graph 615. That
`is,
`maximum propagation delay in 615 is greater than the
`maximum propagation delay in 613. This is indicated by the
`resultant output waveform 609 of the EXCLUSIVE-ORgate
`607 and has a shorter duty cycle in graph 613 than it does
`in graph 615. The output of the EXCLUSIVE-OR gate 607
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`9
`is coupled into a low pass RC filter. The output 611 of the
`RCfilter is a DC sign