US007423475B2
`
`US 7,423,475 B2
`(10) Patent No.:
`az) United States Patent
`Sahaet al.
`(45) Date of Patent:
`Sep. 9, 2008
`
`
`(54) PROVIDING OPTIMAL SUPPLY VOLTAGE
`TO INTEGRATED CIRCUITS
`
`6,211,727 BL*
`7,088,172 BL*
`2002/0014913 Al*
`
`4/2001 Carobolante wo... 327/543
`8/2006 Lesea etal.
`.....
`
`2/2002 Casper occ eeeeeeeeeeee 327/543
`
`(75)
`
`Inventors: Anindya Saha, Bangalore (IN); Vivek
`Gorakhnath Pawar, Bangalore (IN);
`Sudheer Prasad, Bangalore (IN);
`Anmol Sharma, Bangalore (IN); Suresh
`R. Puthucode, Bangalore (IN)
`
`(73) Assignee: Texas Instruments Incorporated,
`Dallas, TX (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 724 days.
`
`(21) Appl. No.: 10/710,861
`
`(22)
`
`Filed:
`
`Aug. 9, 2004
`
`(65)
`
`Prior Publication Data
`
`US 2005/0057230 Al
`
`Mar. 17, 2005
`
`Related U.S. Application Data
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`10322019 A
`2000066746 A
`
`5/1997
`8/1998
`
`OTHER PUBLICATIONS
`
`Peter Macken, Mare Degrauwe, Mark Van Paemel, Henri Oguey, “A
`Voltage Reduction Technique for Digital Systems” in ISSCC 90/
`Session 15. Innovative Circuit design, Swiss Center for Electronics
`and Microtechnology (CSEM) Neuchel Switzerland/ FPM 15.2, pp.
`238-239/ Friday, Feb. 16, 1990.
`Thomas D. Burd and Robert W Brodersen, “Design Issues for
`Dynamic Voltage Scaling”, ISLPED ’00 Rapallo, Italy, Berkeley
`Wireless Research center, University of California, CA/ pp. 09-14,
`ACM,2000.
`
`(Continued)
`
`Primary Examiner—Quan Tra
`Assistant Examiner—Khareem E Almo
`(74) Attorney, Agent, or Firm—Steven A. Shaw; W. James
`Brady; Frederick J. Telecky, Jr.
`
`(60) Provisional application No. 60/498,304, filed on Aug.
`28, 2003.
`
`(57)
`
`ABSTRACT
`
`(51)
`
`Int. Cl.
`(2006.01)
`GOSF 1/10
`(52) US. C1.eee cece ceecesenenseeseneesenee 327/543
`(58) Field of Classification Search .......0.......... 327/543
`See application file for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`A characteristic is measured on multiple portions of an inte-
`grated circuit, and the supply voltage adjusted based on the
`measurements. In an embodiment, the characteristic corre-
`sponds to propagation delay which indicates whether the
`integrated circuit is implemented with a strong, weak or
`nominalprocess corner. In general, the supply voltage can be
`increased in the case of a weak process commer and decreased
`in the case of a strong process comer.
`
`5,648,766 A
`
`7/1997 Stengelet al.
`
`13 Claims, 5 Drawing Sheets
`
`320
`
`614
`
`3 =F52
`
`MONITOR BLOCK
`
`0
`
`i
`
`634
`
`INTEL 1017
`
`320
`
`;FREQUENCY| MULTIPLEXER
`,FREQUENCY">
`
`DIVIDER
`
`DIVIDER
`
`630
`
`INTEL 1017
`
`

`

`US 7,423,475 B2
`Page 2
`
`OTHER PUBLICATIONS
`
`Thomas Burd, Trovor Pering, Anthony Stratakos and Robert
`Brodersen, “A Dynamic Voltage Sealed Microprocessor System’.
`ISSCC 2000/Session 17/ Logic and Systems/Paper WA 17.4, Berke-
`ley Wireless Research center, University of California, CA, pp. 294-
`295, 466, IEEE 2000.
`Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter Glynn and
`Giovanni De Micheli. Dynamic Voltage Scaling and Power Manage-
`ment for Portable Systems, pp. 524-529, Las Vegas, Nevada, USA,
`DAC 2001, Jun. 18-22, 2001.
`Kevin J. Nowka, Gary D.Carpenter, Eric W. Mac Donald, Hung C.
`Ngo, Bishop C. Brock, Koji I. Ishii, Twyet Y. Nguyen and Jeffrey L.
`Bums. A 32-bit PowerPC System-on-a-Chip with support for
`Dynamic Voltage Scaling and Dynamic Frequency Scaling, inIEEE
`
`Journal of Solid State Circuits vol. 37, pp. 1441-1447, No. 11 Nov.
`2002.
`Rex Min, Travis Furrer and Anantha Chandrakasan,“Dynamic Volt-
`age Scaling Techniques for Distributed Microsensor Networks”,
`Department of EECS, Massachusetts Institute of Technology. 2002.
`MohamedElgebaly, Amr Fahim, Inyup Kang and Manoj Sachdev,
`“Robust and Efficient Dynamic Voltage Scaling Architecture”
`Department of Electrical and Computer Engineering, University of
`Waterloo, Ontario, N2L 3G1 Canada, Qualcomm Inc, San Diego,
`CA, 92121 USA.in IEEE,pp. 155-158, 2003.
`A.Soto. A De Castro, P. Alou, J.A. Caobos, J. Uceda and A. Lotfi.
`“Analysis of the Buck Converter for Scaling the Supply Voltage of
`Digital Circuits”. Universidad Politecinica de Madrid(UPM), Spain
`and Enpirion Inc, USA, in IEEE, pp. 711-717, 2003.
`
`* cited by examiner
`
`

`

`U.S. Patent
`
`Sep. 9, 2008
`
`Sheet 1 of 5
`
`US 7,423,475 B2
`
`100
`
`FIG. |
`
`CORE
`mous
`
`POWER
`|__. aK
`
`210
`
`220%
`
`PROVIDE A SUPPLY VOLTAGE
`TO AN INTEGRATED CIRCUIT
`
`MEASUREA CHARACTERISTIC
`AT MULTIPLE PORTIONSOF
`
`100
`
`FIG. 3
`
`PLLYOSC
`
`321-1
`352
`
`230
`
`310-2
`
`312-2
`
`312-4
`
`321-4
`
`280
`THE INTEGRATED CIRCUIT
`
`
`
`MONITOR BLOCK ee) a21-2
`
`320 112
`
`Co
`
`SOWEA
`321-3
`312-3
`429~]MANAGEMENT
`310-3
`BLOCK
`310-4
`
`121
`
`

`

`U.S. Patent
`
`Sep. 9, 2008
`
`Sheet 2 of 5
`
`US 7,423,475 B2
`
`
`
`588
`
`980
`
`
`
`
`540
`
`RIPPLE
`COUNTER
`
`5A4
`
`
`
`FIG. 6
`
`320
`rad
`
`332
`
`660
`312-2 i
`
`%
`614
`70
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`
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`
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`
`645
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`

`

`U.S. Patent
`
`Sep. 9, 2008
`
`Sheet 3 of 5
`
`US 7,423,475 B2
`
`710
`
`720
`
`810
`
`820
`
`850
`
`890
`
`TIME
`
`TIME
`
`
`

`

`U.S. Patent
`
`Sep. 9, 2008
`
`Sheet 4 of 5
`
`US 7,423,475 B2
`
`FIG. 9
`
`FREQUENCY 915%
`
`9117
`
`VOLTAGE
`
`1040
`
`1050
`
`FIG. 10
`
`
`
`
`
`1060
`
`1070
`
`41080
`
`
`
`
`
`
`
`
`
`1140
`
`1150
`
`1160
`
`1170
`
`1180
`
`
`
`

`

`U.S. Patent
`
`Sep. 9, 2008
`
`Sheet 5 of 5
`
`US 7,423,475 B2
`
`"201
`
`1210
`
`DETERMINE THE LARGEST (Cmax)
`AND LOWEST(Cmin) COUNT VALUES
`
`FIG. 12
`
`aCOUNT VALUES AS Cmax
`
`NO
`
`1230
`
`1240
`
`
`
`DETERMINE COUNT VALUES(C1S, C2S,
`AND C3S) CORRESPONDING TO WEAK,
`NOMINAL AND STRONG PROCESS
`CORNERS FOR A PRESENT SUPPLY
`VOLTAGE FROM A LOOKUP TABLE
`
`
`
`1250
`
`NO
`
`IS 1.10*
`C1S>Cmax>0.90
`*C3S?
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`CONCLUDE THAT
`iS 1.10%
`
`
`
`C1iS>Cmax>0.95*
`INTEGRATED CIRCUIT IS OF
`
`
`C3S?
`WEAK PROCESS CORNER
`
`
`
`
`IS 1.05*
`CONCLUDE THAT
`
`
`
`C3S>Cmax>0.90*
`INTEGRATED CIRCUIT IS OF
`
`
`C3S?
`STRONG PROCESS CORNER
`
`
`
`IS 0.95*
`
`
`C1S>Cmax>1.05*
`C3S?
`
`DISCARD
`INTEGRATED CIRCUIT
`
`1255
`
`

`

`US 7,423,475 B2
`
`1
`PROVIDING OPTIMAL SUPPLY VOLTAGE
`TO INTEGRATED CIRCUITS
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`The present application is related to and claims priority
`from co-pending USprovisional patent application entitled,
`“Providing Optimal Supply Voltage to Integrated Circuits”,
`Filed on: Aug. 28, 2003, Ser. No. 60/498,304, naming as
`inventors: SAHA et al, and is incorporated in its entirety
`herewith into the present application.
`
`BACKGROUNDOF INVENTION
`
`1. Field of the Invention
`
`The present invention relates to integrated circuits, and
`more specifically to a method and apparatus for providing
`optimal supply voltage to integratedcircuits.
`2. Related Art
`
`Integrated circuits (ICs) are generally driven by supply
`voltages. Various components (e.g., transistors) in the ICs
`require the supply voltage during operation as is well known
`in the relevantarts.
`
`It may be desirable to provide optimal supply voltage to
`ICs. As an illustration, a high supply voltage generally leads
`to low propagation delays which maybe useful in increasing
`the throughput performance of an IC. However, a substan-
`tially higher supply voltage may lead to unusability of ICs due
`to gate oxide layerfailure, etc.
`On the other hand, a low supply voltage minimizes such
`failures, but could lead to high propagation delay (and a
`correspondingly slower speed of operation) in the operation
`of an IC.
`
`At least for such reasons, there is a recognised need to
`adjust the supply voltage dynamically during the operation of
`an integrated circuit.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`10
`
`15
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`20
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`25
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`40
`
`2
`FIG. 9 is a graph illustrating the manner in which the speed
`of operation changes with different supply voltages forinte-
`grated circuits implemented with weak, strong and nominal
`process corners.
`FIG. 10 is a lookup table depicting the details of the fre-
`quencyof operation of a GROatdifferent process corners in
`one embodiment.
`
`FIG. 11 is a lookup table depicting the details of counter
`values for the corresponding frequencies depicted in lookup
`table of FIG. 10 at different process comers for various pro-
`grammable voltagelevels.
`FIG. 12 is a flowchart illustrating the manner in which the
`process corner may be determined using a lookup table in one
`embodiment.
`
`DETAILED DESCRIPTION
`
`1. Overview
`
`An integrated circuit (IC) provided according to an aspect
`of the present invention contains multiple portions (on the
`silicon die), which generate respective signals (digital or ana-
`log) providing a measureof a characteristic (e.g., propagation
`delay) of the corresponding portion. A power management
`block adjusts the supply voltage based on the measured val-
`ues. Due to such measurements at different portions of an
`integrated circuit, the supply voltage can be adjusted taking
`into consideration the status at several portions of the inte-
`grated circuit.
`In an embodimentofthe present invention, each measure-
`ment indicates whether the corresponding portion is fabri-
`cated using strong, nominal or weak process, and the voltage
`is adjusted to derive higher throughput performance from
`portions of weak process corner, while ensuring that even the
`portions of strong process cornerare not exposed to voltages
`exceeding acceptable threshold value. As a result, integrated
`circuits of weak process corners can also be potentially used
`to attain a desired throughput performance, thereby increas-
`ing the overall yield (percentage of acceptable units of IC) in
`a fabrication environment.
`
`Another aspect of the present invention integrates the
`power managementblock also into the integrated circuit,
`The present invention will be described with reference to
`which may provide several advantages. In one embodiment, a
`the following accompanying drawings.
`non-volatile memory (e.g., in the form of an efuse) is pro-
`FIG. 1 is a block diagram of a die illustrating an example
`grammed with an adjustment value, which controls the
`device in which the present invention may be implemented.
`strength ofthe supply voltage at the timeofinitialization. The
`FIG. 2 is a flowchart illustrating a manner in which the
`supply voltage may be adjusted further according to various
`supply voltage for/of an integrated circuit may be adjusted
`features ofthe present invention. However, by measuring the
`according to an aspect of the present invention.
`strength of the process corner (for example, while testing/
`FIG. 3 is a block diagram illustrating the details of an
`qualifying the IC) and setting the value in the non-volatile
`example integrated circuit
`implemented according to an
`memory accordingto the optimal desired voltage, the supply
`aspect of the present invention.
`voltage can be adjusted quickly to an optimum desired volt-
`FIG. 4 is a block diagram illustrating the details of a power
`age.
`managementblock implemented according to an aspect ofthe
`One more aspectof the present invention reduces the num-
`present invention.
`ber of transistors by using a multiplexor to receive the mea-
`FIG. 5A is a circuit diagram illustrating the details of a
`sured values, and processing the measured values using a
`gated ring oscillator (GRO) in one embodiment.
`sharedcircuit. Die size and power consumption requirements
`FIG. 5B is a circuit diagram illustrating the details of a
`may be minimizedasaresult.
`gated ring oscillator in an alternative embodiment.
`Various aspects of the present invention are described
`FIG.6 is a block diagram illustrating the details of a moni-
`below with reference to an example problem. Several aspects
`of the invention are described below with reference to
`tor block in an embodimentofthe present invention.
`FIG. 7 is a timing diagram depicting the details of changes
`in various signals in the monitor block in an embodiment of
`the present invention.
`FIG. 8 is a timing diagram depicting the details of changes
`in various signals in the monitor block in an alternative
`embodimentof the present invention.
`
`60
`
`65
`
`examples for illustration. It should be understood that numer-
`ous specific details, relationships, and methodsaresetforth to
`provide a full understanding of the invention. One skilled in
`the relevant art, however, will readily recognize that the
`invention can be practiced without one or moreofthe specific
`details, or with other methods, etc.
`In other instances,
`
`45
`
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`55
`
`

`

`US 7,423,475 B2
`
`3
`well_knownstructures or operations are not shownin detail
`to avoid obscuring the invention.
`
`2. Example Integrated Circuit
`FIG. 1 is a block diagram of an integrated circuit illustrat-
`ing an example environment in which the present invention
`may be implemented. Integrated circuit 100 is shown con-
`taining core module 110 and power management block 120.
`Both core module 110 and power managementblock 120 may
`be fabricated/implemented ona single die. In an embodiment,
`the core module 110 consists of everything on the die/chip
`minus/except the power management block 120 (if it
`is
`on_chip).
`Power managementblock 120 provides the supply voltage
`on path 121 to core module 110 based on a control signal
`received on path 112. Power management block 120 is
`designed such that the supply voltage provided on path 121
`can be adjusted based on control signal 112. Power manage-
`ment block 120 is shown implemented in integrated circuit
`100, however power managementblock 120 can be imple-
`mented external to integrated circuit 100 as well.
`Core module 110 may be designed to perform various
`operations to support various user applications, as desired.
`Integrated circuit 100 may operate in one of different process
`corners due to the variations (or unpredictability) that are
`typical of semiconductor manufacturing processes, tempera-
`ture, voltage, etc. Similarly, different portions of a single
`integrated circuit (IC) may also operate in different process
`corners due to similar reasons.
`
`In general, the speed of operation of a portion of an IC is
`lowifthe corresponding process corner is weak and the speed
`of operation is high if the process corner is strong. In a prior
`approach, an IC may be deemedto be unacceptable to provide
`a desired throughput performanceif the IC is fabricated at a
`weak process corner. An aspect of the present invention may
`enable some of such ICs to be used, in addition to ensuring
`that ICs operate at an appropriate speed (performance) as
`described below with reference to FIG.2.
`
`3. Method
`FIG. 2 is a flowchart illustrating a manner in which the
`performanceofan integrated circuit may be adjusted accord-
`ing to an aspect of the present invention. The method is
`described with reference to FIG. 1 forillustration. However,
`the method may be implemented in other environments as
`well. The method begins in step 201, in which control imme-
`diately passes to step 210.
`In step 210, a supply voltage is provided to an integrated
`circuit (IC). With reference to FIG. 1, power management
`block 120 provides supply voltage to core module 110. In
`general, supply voltage is required for operation of various
`components in the integrated circuit.
`In step 220, a characteristic is measured at multiple por-
`tions of the IC. In an embodiment, propagation delay at each
`portion is measured and the propagation delay represents the
`process corner atthe portion.
`In step 280, the supply voltage is adjusted based on the
`measured (analog/digital) values.
`In an embodiment
`described in sections below, the core module sends a control
`signal to the power managementblock to adjust the supply
`voltage. For example, core module 110 sends a control signal
`to increase the supply voltage if the propagation delay is high
`(i.e., in case of a weak process corner). The method then ends
`in step 299.
`From the above, it may be notedthat a desired performance
`level may be attained for an IC by appropriate adjustment of
`the supply voltage irrespective of the process corner at which
`the IC (or portions) is manufactured to operate at. As a result,
`
`20
`
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`45
`
`55
`
`4
`integrated circuits with weak or strong process corners may
`also be put into use, thereby increasing the effective yield. In
`addition, the change in the characteristic due to temperature,
`voltage, etc., may also be automatically adjusted due to the
`operation of various features. The description is continued
`with reference to an example integrated circuit, which mea-
`sures a characteristic and adjusts the supply voltage.
`
`4. Example Integrated Circuit
`FIG. 3 is a block diagram illustrating the details of an
`example integrated circuit, which adjusts the supply voltage
`according to an aspect of the present invention. Integrated
`circuit 100 is shown containing four gated ring oscillators
`(GROs) 310-1 through 310-4, monitor block 320, central
`processing unit (CPU) 330, random access memory (RAM)
`340, phase locked loop (PLL) or crystal oscillator (OSC) 350
`and power management block 120. The components are
`described below in further detail.
`
`Merely for conciseness, only the components relevant to
`the operation of an embodimentofthe present invention are
`shown contained in integrated circuit 100. However, inte-
`grated circuit 100 may contain several other components.
`Typically,
`integrated circuit contains other portions (not
`shown) which may be used to implementvarious user appli-
`cations(e.g., processing an analog signalor digital data), and
`such portions which implementthe user applications is con-
`veniently referred to as an application block.
`As maybereadily noticed from FIG. 3, each GRO/portion
`is at a corresponding area on the IC. The areas are non-
`contiguous, implying that different GROs/portions measure
`the corresponding place/area of the IC. In particular, GROs
`310-1, 310-2, 310-3 and 310-4 are respectively shown in top
`left, top right, bottom left and bottom right areas in the
`example scenario there.
`GROs 310-1 through 310-4 operate as measurement
`blocks, and may be placed in specific portions of the IC at
`which a characteristic (e.g., speed or propagation delay) of
`interest is sought to be measured. Each of GROs 310-1
`through 310-4 generates a respective signal on corresponding
`one of paths 312-1 through 312-4 representing the propaga-
`tion delay corresponding to the surrounding portion where
`the GRO is placed. In an embodiment, each GRO output
`signal represents a square wave, and accordingly the time
`period of the GRO output signal represents the propagation
`delay.
`In addition, GROs 310-1 through 310-4 are shownreceiv-
`ing GRO_ENsignalon respective paths 321-1 through 321-4.
`GROs310-1 through 310-4 are enabled/operational for one
`logical value of GRO_EN signal and nonoperational for
`another logical value of GRO_ENsignal.
`Monitor block 320 receives the signals from GROs 310-1
`through 310-4 on respective paths 312-1 through 312-4, and
`provides count (measured) values on path 323 representing,
`the propagation delays at different portions. In an embodi-
`ment, monitor block 320 contains a counter, which counts the
`numberof cycles of clock signal 325 during certain state (for
`example, period when the signal is at logical high level) of
`each of the signals 312-1 through 312-4 to generate corre-
`sponding count values.
`In an alternative embodiment, the counter counts the num-
`ber of cycles in the signal on paths 312-1 through 312-4
`during a fixed duration (for example, 1 milli second). The
`counted value again represents the propagation delay at the
`portion andis provided as the count value on path 323. Con-
`trol signals on path 332 enables the same counter to be used
`associated with all the GROs, thereby decreasing the circuit
`
`

`

`US 7,423,475 B2
`
`5
`complexity. An exampleuse of control signals on path 332 is
`described below with reference to the details ofmonitor block
`320 associated with FIG.6.
`
`CPU 330 performs various operations on the received
`count values on path 323 and generates a signal on path 112 to
`adjust the supply voltage accordingly. CPU 330 also provides
`control signals on path 332 to control various operations in
`monitor block 320. In an embodiment, CPU 330 generates the
`signal on path 112 based on an averageof all the count values.
`In an alternative embodiment,
`the largest count value
`among, the four values is used to generate the signal on path
`112 as described in sections below. The largest count value
`represents weak process corner since weak process corner has
`high propagation delay. As an illustration, if the average/
`largest count value represents weak process corner, CPU 330
`sends the signal to increase the supply voltage.
`CPU 330 receives information on path 343 whether the
`process corner is weak, nominalor strong for the correspond-
`ing average or largest count value (of the respective two
`embodiments noted above). In an embodiment, RAM 340
`contains a lookup table indicating whether the process corner
`is weak, strong or nominal corresponding to the (average/
`largest) count value and the present supply voltage level. An
`embodimentofthe lookuptable is described with reference to
`FIG. 10 in sections below. RAM 340 provides on path 343
`data indicating whether the process corner is weak, strong or
`nominal corresponding to the received count value on path
`323.
`
`It may be noted that once the count values representing the
`process corner are determined, CPU 330 CPU 330 programs
`power management block 120 to adjust the supply voltage.
`Such adjustment may be performed by using instructions
`consistent with an interface provided by power management
`block 120.
`
`Power management block 120 adjusts the supply voltage to
`integrated circuit 100 based on the signal received on path
`112. The mannerin which power managementblock 120 may
`be implemented according to several aspects of the present
`invention is described below with reference to FIG.4.
`
`10
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`6
`embodiment, current limiter 460 sends a signal on path 465
`representing constant current mode, in response to which
`powerstage 470 provides the desired currentto capacitor 455.
`Current limiter 460 generates another signal on path 465
`whenthe signal received on path 416 indicates that capacitor
`455 is charged to the desired voltage level, causing power
`stage 470 to operate in normal mode.
`Controller 410 receives reference voltage on path 431 and
`output voltage on path 451, and generates pulses on path 417.
`The duty cycle (ratio oftime durationof logic 1 to cycle time)
`of the pulses is computed based onthe difference of voltages
`received on paths 431 and 451, and code received on path 421.
`In general, the duration of logic 1 is increased to increase the
`voltage level (either in response to digital code indicating a
`need to increase the voltage or the voltage level received on
`path 451 in comparison to the reference voltage 431).
`Controller 410 also generates a signal on path 416 when the
`code received on path 421 requires a change ofthe voltage on
`capacitor 455. Controller 410 detects whether capacitor 455
`is charged to the desired voltage level and disables the signal
`on path 416 (if the capacitor is charged), which causes power
`managementblock 120 to be operated in normal mode.
`Voltage reference 430 generates a reference voltage on
`path 431, which represents the initial voltage level to be
`provided to various components in integrated circuit 100.
`Reference voltage 431 may be generated to be a constant
`voltage independent oftemperature, pressure, etc., variations.
`Register 440 stores a fixed code (adjustment value)
`received on path 444. In an embodiment, process corner of
`integrated circuit 100 is determined during testing of the die
`and adjustmentvalue 444to attain the desired voltage level is
`generated by a test equipment (not shown) based on the
`process corner. As aresult, the optimal desired voltage may be
`quicklyattained duringtheinitialization phase. In an embodi-
`ment, power management block 120 is integrated with the
`integrated circuit in the same die, and register 440 may be
`particularly useful in such embodiments.
`Multiplexer 420 receives fixed code on path 442 andvari-
`able code on path 112, which represents the desired voltage
`level (or changethereto) during the operation ofan integrated
`circuit. Multiplexer 420 selects one of the two codes received
`on paths 442 and 112 and provides the selected code on path
`421. The description is continued with respectto the details of
`GRO(gated ring oscillator) in one embodiment.
`
`5. Power Management Block
`FIG.4 is a block diagram illustrating the details of power
`management block 120 in an embodiment of the present
`invention. Power managementblock 120 is shown containing
`controller 410, multiplexer 420, voltage reference 430, reg-
`6. Gated Ring Oscillator
`ister 440, inductor 450, capacitor 455, current limiter 460 and
`powerstage 470. Each componentis described below.
`FIGS. 5A and 5B arecircuit diagrams, eachillustrating the
`
`Inductor 450 and capacitor 455 together formafilter, details of gated ring oscillator 310-1 in one embodiment.
`which generates a d.c. voltage on path 121 in responseto the
`Merely for illustration, the details of gated ring oscillator
`pulses received on path 475. During the initial power up,
`310-1 is described, however, gated ring oscillators 310-2,
`capacitor 455 charges from OVto the desired voltage level by
`310-3 and 310-4 may also be implemented similarly. Con-
`aconstant current received from powerstage 470. In addition,
`tinuing with reference to FIG. 5A,gated ring oscillator 310-1
`capacitor 455 charges to the desired voltage level by a current
`is shown containing inverters 550, 560 and 570, and ripple
`received from power stage 470 when code on path 421
`counter 580. Each componentis described below.
`changes representing the desired change in output voltage.
`Inverters 550, 560 and 570 (in an odd number) are con-
`Powerstage 470 converts the pulses received on path 417 in
`nected in a ring structure, which together generate a square
`to pulses with high power on path 475 in normal mode (con-
`wave on path 578. The time period of the square waverepre-
`stant voltage mode). Powerstage 470 provides constant cur-
`sents the propagation delay ofinverters 550, 560 and 570. The
`rent to capacitor 455 to charge to the desired voltage level in
`propagation delay in turn depends on the process cornerofthe
`a constant current mode based on the signal received on path
`portion surrounding to the inverters. Thus, the time period of
`417. Power stage 470 switches to constant voltage mode
`the square waverepresents the process corner surrounding the
`when the signal on path 417 represents constant voltage
`portion where GRO 310-1 is implemented in integrated cir-
`mode, which may be generated when capacitor 455 charges to
`cuit 100. Merely for conciseness, GRO 310-1 is shown con-
`the desired voltagelevel.
`taining only three inverters, however, GRO 310-1 may be
`Current limiter 460 controls the operation of power stage
`implemented with any odd numberofinverters to form the
`470 to provide the required high current to capacitor 455
`ring structure, as would be apparent to one skilled in the
`relevantarts.
`while capacitor 455 chargesto the desired voltage level. In an
`
`50
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`55
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`60
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`65
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`

`US 7,423,475 B2
`
`7
`Ripple counter 580 receives the square wave on path 578,
`and generates another square wave having a smaller fre-
`quency on path 588. Using the ripple counter generally
`increases the precision/resolution of measurement of the
`propagation delay (as described in sections below). In an
`embodiment, ripple counter 580 is implemented as a 9-bit
`counter, which results in the signal on path 588 having a time
`period of 512 times thatofthe signal on path 578. Using more
`bits in the ripple counter generally leads to better precision.
`From the above,it may be notedthat the time period of the
`square wave signal on path 588 represents the propagation
`delay of GRO 310-1. An alternative implementation of GRO
`310-1 is described below with reference to FIG. 5B.
`
`FIG.5B is a circuit diagram illustrating the details of GRO
`310-1 inan alternative embodiment. GRO 310-1 ofFIG. 5B is
`
`showncontaining NAND gates 510, 520 and 530, and ripple
`counter 540. NAND gates 510, 520 and 530, and ripple
`counter 540 together generate a square wave signal on path
`544 similar to the signal on path 588 of FIG. 5A.
`Ripple counter 540 operates similar to ripple counter 580
`and NANDgates 510, 520 and 530 operate similar to inverters
`550, 560 and 570 except that NAND gates 510, 520 and 530
`receive GRO_ENsignal on path 321-1. As described above
`with reference to FIG. 3, GRO_EN 321-1 is usedtostart/stop
`the operation of GRO.
`If GRO_EN 321-1 is at logic high, NANDgates 510, 520
`and 530 together generate a square wave signal on path 534.
`Ripple counter 540 generates on path 544 a square wave
`having a higher frequency from the square wave received on
`path 534. If GRO_EN 321-1 is at logic low, NANDgates 510,
`520 and 530 together stop generating the square wave signal,
`and provide a logic high value on path 534.
`Thus, it may be appreciated that GRO_EN signal 321-1
`starts the operation of GRO whenatlogic high and stops the
`operation when at logic low. The manner in which monitor
`block 320 uses the low frequency square wavesignals on path
`588/544 to generate a count value is described below with
`reference to FIGS. 6, 7, and 8.
`
`7. Monitor Block
`
`FIG. 6 is a block diagram illustrating the details of monitor
`block 320 in an embodiment of the present invention. As
`described above, broadly, monitor block 320 generates a
`count value representing the frequency of the a signal
`received from a corresponding GRO. Based on the count
`values, CPU 330 determines the process corner and the cor-
`responding change to be made in supply voltage. Monitor
`block 320 is shown containing multiplexers 610 and 640,
`frequency dividers 620 and 630, transition detector 650, con-
`trol register 660, counter 670 and capture register 680. Each
`componentis described below.
`Control register 660 is shown containing GRO_ENbit,
`COUNT_ENbit and select bits. However, control register
`660 may contain more numberofbits as required. Thebits of
`control register 660 are received on path 332 and are send by
`CPU 330. GRO_ENbit is used to enable each GRO 310-1
`through 310-4,
`transition detector 650 and counter 670.
`COUNT_ENbit is used to enable counter 670 and select bits
`are used to select one out of four GRO output signals 312-1
`through 312-4.
`Multiplexer (MUX) 610 selects a GRO output signal
`received on paths 312-1 through 312-4 based on select bits
`received on path 661. The select bits are set by CPU 330 as
`described above. The selected GRO outputsignalis provided
`on path 614. Dueto the use of multiplexor 610, several com-
`ponents(transition detector 650, control register 660, counter
`
`25
`
`40
`
`45
`
`8
`670, capture register 680, etc.) may be sharedto process the
`output signals received from all the GROs, thereby reducing
`the area requirements.
`Frequency dividers 620 and 630 divide the frequencyofthe
`selected GRO output signal received on path 614 and provide
`the lowerfrequency (high time period) GRO outputsignal on
`respective paths 624 and 634. The high time period GRO
`output signal may increase the resolution (precision) of the
`measurement of the count value. In an embodiment, fre-
`quency dividers 620 and 630 are implemented to divide by 2
`and 4 respectively.
`Multiplexer 640 selects one ofthe signals received on paths
`614, 624 and 634 basedonthe resolution select signal RES_
`SEL 641 contained in path 323 of FIG. 3. Multiplexer 640
`providesthe selected signal on path 645.
`Transition detector 650 detects the transitions (either fall-
`ing or rising) ofthe signal on path 645 and generates pulses on
`path 657 indicating the time points oftransitions. Transition
`detector 650 starts detecting transitions when GRO_EN
`received on path 665 is high. As described below, counter 670
`counts the numberof cycles of clock 352 between two suc-
`cessive transitions.
`
`Counter 670 starts counting the cycles/pulses in clock sig-
`nal clk 352 when both of GRO_EN and COUNT_ENare
`high, anda transition pulse is received from transition detec-
`tor 650 on path 657. Counter 670 stops counting when the
`next transition pulse is received on path 657. In an alternative
`embodiment, counter 670 receives the square wave signal on
`path 645 directly (without transition detector 650in the path),
`and counts the numbercyclesor pulsesin the signal received
`on path 645 during certain time period (for example, 1 milli-
`second). The time period to measure may be specified by
`enabling the COUNT_ENbit, and disabling the bit when the
`countis to stop. The count value is provided on path 678.
`Captureregister 680 stores the count value received on path
`678 at the start of falling edge transition detected on 657. CPU
`330 checks COUNT_ENbitin controlregister 660 and reads
`the count value from capture register 680 on path 323 when
`COUNT_ENbit is zero (