Trials@uspto.gov
`571-272-7822
`
`
`
`
`Paper No. 45
`Entered: January 8, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`TELA INNOVATIONS, INC.,
`Patent Owner.
`____________
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`____________
`
`Record of Oral Hearing
`Held: December 9, 2020
`____________
`
`
`
`
`Before JO-ANNE M. KOKOSKI, KRISTINA M. KALAN, and
`WESLEY B. DERRICK, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`571-272-7822
`
`
`
`
`Paper No. 45
`Entered: January 8, 2020
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`TELA INNOVATIONS, INC.,
`Patent Owner.
`____________
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`____________
`
`Record of Oral Hearing
`Held: December 9, 2020
`____________
`
`
`
`
`Before JO-ANNE M. KOKOSKI, KRISTINA M. KALAN, and
`WESLEY B. DERRICK, Administrative Patent Judges.
`
`
`
`
`
`
`
`
`
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`
`
`APPEARANCES:
`
`ON BEHALF OF THE PETITIONER:
`
`
`BAO NYUGEN, ESQ
`TODD FRIEDMAN, ESQ
`Kirkland & Ellis, LLP
`300 North LaSalle
`Chicago, IL 60654
`
`
`
`ON BEHALF OF THE PATENT OWNER:
`
`
`ANDREW P. ZAPPIA, ESQ.
`GUNNAR LEINBERG, ESQ.
`BRYAN SMITH, ESQ.
`Troutman Pepper
`875 Third Avenue
`New York, NY 10022
`
`
`
`
`
`The above-entitled matter came on for hearing on Wednesday,
`December 9, 2020, commencing at 1:00 p.m., EDT, by video/by telephone.
`
`
`
`
`
`
`
`
`
`
`
`2
`
`
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`
`P R O C E E D I N G S
`- - - - -
`JUDGE KOKOSKI: Good afternoon. Today we will hear
`
`arguments in IPR 2019-01520, 01521, 01522, 01636, 01637. I
`am Judge Kokoski and I am joined today by Judge Kalan and
`Judge Derrick. Let's start with appearances beginning with
`Petitioner.
`
`MR. NYUGEN: Your Honors, Bao Nyugen from Kirkland
`& Ellis. I will be speaking on behalf of Petitioner and with me
`on the video is Todd Friedman who is lead counsel.
`
`JUDGE KOKOSKI: Thank you. Patent Owner?
`
`MR. ZAPPIA: Andrew Zappia for Patent Owner and I have
`with me Gunnar Leinberg, lead counsel and Bryan Smith.
`
`JUDGE KOKOSKI: Thank you. Consistent with our
`Hearing Order, each party has 90 minutes to present their
`arguments and you can allocate your time between the cases as
`you wish. Petitioner will open the hearing with their 90 minutes
`and may reserve time for rebuttal. Petitioner, how much time
`would you like to reserve for your rebuttal?
`
`MR. NYUGEN: Your Honors, we will reserve 30 minutes
`for rebuttal.
`
`JUDGE KOKOSKI: Thirty minutes?
`
`MR. NYUGEN: Yes, yes Your Honor.
`
`JUDGE KOKOSKI: Okay. Okay. Patent Owner will then
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`have 90 minutes to present their case and may reserve time for
`surrebuttal. How much time would you like to reserve, Patent
`Owner?
`
`MR. ZAPPIA: Twenty minutes for surrebuttal, Your
`Honor.
`
`JUDGE KOKOSKI: Okay, thank you. In light of the
`amount of time granted to the parties for the arguments this case
`is a little longer than normal. I mean it's likely that we might
`need to take a short break somewhere around the halfway point
`or whenever we can do so with the least disruption to the
`proceedings but we'll see how the afternoon goes.
`
`Before we begin I would like to remind the parties that we
`each have a copy of the demonstratives that you provided.
`During your argument, please identify clearly and specifically
`the demonstrative reference by slide or screen number so that
`everyone can follow along and to assure clarity and accuracy of
`the court reporter's transcript. We also request that you keep
`your line muted when you are not speaking and also please keep
`in mind that the remote nature of this hearing may result in audio
`lag so please pause prior to speaking so as to avoid speaking
`over others. I'll also remind the parties that this hearing is open
`to the public and we do have an audio line open to the public
`today. Therefore, the parties should avoid disclosing any
`confidential information during their arguments. We will keep
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`track of the time and try to give you a reminder close to the end
`but we encourage the parties to keep track of your own time as
`well. With that, I think Petitioner you can begin when you're
`ready.
`
`MR. NYUGEN: Thank you, Your Honors. Your Honors,
`my name is Bao Nyugen from Kirkland & Ellis and as I said
`earlier I will be presenting on behalf of Petitioner Intel
`Corporation. I will start with the three IPR that are directed to
`the '523 patent and then I will address the two IPR that are
`directed to the '334 and '335 patents.
`
`On slide 3 is a summary of the challenged claims of the
`'523 patent. The three IPRs challenge the 24 claims of the '523
`patent but using a single common prior art ground which is Yano
`in view of Kitabayashi and Ikoma renders obvious all of the
`challenged claims and because of that single prior art ground the
`issues that are in dispute in this case actually allows the common
`across all (indiscernible) and the patent at the later briefing, for
`example the reply (phonetic) (indiscernible) as well.
`
`Your Honors, before getting into the disputed issues I
`would like to give a brief overview of the '523 patent and the
`prior art, and so on slide 4 there's a brief overview of the '523
`patent. The '523 patent, as the Patent Owner in fact describes in
`its Patent Owner reply that is cited, that's part black (phonetic)
`of the slide is about the layout, the regular layout in which
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`5
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`
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`structures are within the layout single dimensional. In other
`words, they are rectangular shape and they are oriented i n the
`same direction and that's what is shown, for example illustrated
`in figure 8B of the '523 patent as on the right side of the slide.
`Here the blue structures are structures of the first metal layer and
`you can see how they all rectangular shape and they all extend in
`a common direction. Now the Patent Owner explains in the
`Patent Owner's response regular layout doesn't impose more
`requirements such as common width or common bounds
`(phonetic) to the bounded (phonetic) shapes. You can see that
`the two top and bottom rectangular shapes for example are of
`different widths compared to the other rectangular shaped
`structures of the same layout and as I pointed out because Patent
`Owner will make an argument effectively having structures of
`different shapes -- rectangular shapes of different widths spaced
`(phonetic) in a regular layout and I think that's consistent with
`the '523 patent and we'll get back to that in more detail, we'll get
`to the issues I want to raise at this point.
`
`Beyond sort of the general concept of using rectangular
`shape unidirectional structures due to a regular layout of an
`integrated circuit, the '523 patent is completely circuit- agnostic.
`It doesn’t describe or discuss any functional circuit including
`circuits that are claimed in the patent such as the multiplexer is
`expressly claimed in the '523 claim 22, challenged claim 22. I
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`6
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`
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`want to point that out again because clearly often the Patent
`Owner argues that the prior art does not discuss functional
`circuits and that's actually not true. But the point is the '523
`patent itself does not describe any functional circuit.
`
`Let me now turn to slide 5 which here we have listed in full
`claim 1 of the '523 patent. That is the only independent claim
`that is challenged and all of the other claims that are challenged
`depend on claim 1. The most important point that I want to point
`out right now is that the claim of the '523 patent -- all the claims
`of the '523 patent and certainly claim 1, claims a region of a
`semiconductor chip. The claims of the term region appears in
`every claimed element of claim 1 for example. For example, if
`you look at the section of claim 1 that we have highlighted in red
`which relates to the gate electrode, i t recites that the gate
`electrode features that are formed within a region of the
`semiconductor chip, and then goes on with the requirement for
`that region that is claimed. And the same thing if you go to the
`middle column there we have highlighted in light blue the
`requirements of the claim recites the recitation that relates to the
`first-metal layer and the first-metal structures and again the term
`region is in that claim element. The claim does not claim
`anything outside the claimed region, nor do any of the dependent
`claims impose any requirements outside the claimed region.
`
`I make that point because as you will see, and we'll get to
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`7
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`
`
`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`the disputed issues, the Patent Owner in order to distinguish the
`prior art often times points to other (phonetic) documents
`relating to things that are outside of what Dr. Shanfield has
`established as being consistent with claimed region.
`
`Another point I want to make is that the claimed region is
`not a functional region. In other words, it doesn't correspond to
`any recognizable function. It's not about a region that
`corresponds that says a memory array, a memory cell, a
`processor module, nothing that is functionally recognizable. The
`reason is simply whatever is claimed, and it's an arbitrary reason
`and it is whatever is being claimed in the claim and that includes
`why it was called arbitrary quantitative requirements which are
`listed at the top there, for example th at the gate structure has to
`have at least seven gate gridlines, that the number of gate
`contacts in the region has merely six and the number of the metal
`gridlines with the first metal structure has zero distinct
`(phonetic). It doesn't by itself amount to any functional module
`or functional structure and I point that out because Dr. Farrell
`(phonetic) has argued repeatedly that Dr. Shanfield's selection of
`what in the Yano would teach you a claimed region correspond to
`the claim region. Farrell argues that selection is arbitrary, but
`the point is that the claimed region itself is arbitrary and it's
`noted with arbitrary quantitative requirements that the
`specification doesn't even talk about or suggest that they're
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`somehow of any significance.
`
`JUDGE KALAN: Counsel, I have a question about the
`preamble of claim 1 where a semiconductor chip is recited. Is
`that at odds with your arguments about the features being formed
`within a region when the claim as a whole is directed to the chip
`at large?
`
`MR. NYUGEN: No, your Honor. Certainly the claim is
`about a semiconductor chip. My point is every requirement, as
`you can see here, is directed to a claimed region. In other words,
`the gate electrodes, whether the gate electrodes whether there are
`seven gridlines or not recited in the context of the claimed
`region. For example, the claim requires six gate contacts. That's
`for the contact from the same region. The chip will have
`millions of the gate contacts, chip will have millions, hundreds
`of thousands of gate structures but the claim specifically claims
`seven and that's all about the small claimed region issue. If that
`answers your question, then we'll move on.
`
`JUDGE KALAN: Thank you.
`
`MR. NYUGEN: Okay. So now in terms of the prior art and
`only a brief overview because we will draw into the detail as we
`go through the disputed issues. So here's a brief overview of
`Yano and Yano is directed to regular layout. It's particularly
`focused on the gate layer because that's the layer that forms
`transistors and the transistors as Yano explains is where it's most
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`sensitive to fabrication (phonetic) deficiencies in view of things
`like that.
`
`As you can see in the figures 4 and 5 that are on top right
`of slide 6 that are annotated, as well as the figures on the face of
`the patent, of the Yano patent to the left. Every gate and dummy
`gate, the gates are highlighted in blue, in red, I'm sorry, in
`figures 4 and 5 and the dummy gates are highlighted by blue in
`the same figures 4 and 5. Every gate and dummy gate in figures
`4 and 5 are rectangular shape extending in the same direction as
`the vertical direction. Exactly the same way that Patent Owner
`has explained what it means to be a regular layout in the context
`of the '523 patent as I will explain. In fact they are also -- the
`gates and dummy gates are regularly spaced apart with the
`spacing S1 that is expressly shown or labelled in figure 4 and
`figure 5 and in fact in every figure of Yano.
`
`So Yano's not just a regular layout. Now unlike the '523
`patent that is completely circuit-agnostic and that doesn't go any
`deeper than just regular concept of regular layout. The Yano
`patent only goes deeper and it describes a general regular layout
`but at the level of building block circuits that hold standard
`cells. If ensures that the standard cells are regularly formed and
`they can be combined together and they can be spaced side-by-
`side each other and they can be in fact mapped onto each other,
`as Dr. Shanfield has done with figure 4+5 and we'll get back to
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`that again but you can see from the text that is below figure 4 +5
`that say just that. The present invention relates to standard cells
`used in a semiconductor integrated circuit. It relates to a
`standard cell library and a semiconductor integrated circuit using
`it, meaning using that standard cell library and explains that it is
`widespread to design a chip by combining these functional
`blocks, these functional circuits that are for standard cell and it
`explains that those cells have to be uniform, have to have the
`same height and they share the same wires or the same metal
`lines that carry power and ground (phonetic) in order for them to
`be easily laid out next to each other and be easily stuck on to
`each other, as Dr. Shanfield has done with figure 4+5, and just to
`be clear the height of the cell is what I highlighted this figure,
`top to bottom this figure, and the source wiring structures are the
`dark blue metal structures that run horizontal in those figures
`and perpendicular to the gates.
`
`I would like to turn now to slide 7 and this is again, this is
`quick overview of Kitabayashi. It is undisputed that Kitabayashi
`is directed to a regular layout with a particular focus on the
`metal wiring. Patent Owner does not dispute that at all. So
`simply we show here figure 15 and 17 of Kitabayashi. Here we
`show figures very clearly the two adjacent metal layers of the
`gate layer, one could be -- for example, the last figure 15 could
`be the metal-1 layer and the figure 17 to the right could be the
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`metal-2 layer and in each of the layers you can see that the
`wirings have all rectangular shape and they all extend in a
`common direction. For example in figure 15 all the structures
`are rectangular shape and they extend in a common horizontal
`direction, exactly the way the Patent Owner say what it means to
`be a regular layout and moreover just like Yano, Kitabayashi
`teaches the use of dummy structures to ensure layout regularity .
`What you see in the figures 15 and 17 the pink structures. We
`ran out of colors and pink was the color that we chose for
`dummy structures here. Pink, the dummy structures are there to
`ensure regularity. If you just take away the pink you can see
`there a lot of cases where you don't see any structures but with
`the pink dummy structures, just like the blue dummy gates of
`Yano on the slide before this ensures regularity, ensures that the
`metal structure that rectangular shape and that extend in a
`common direction are also regularly spaced.
`
`If I could now direct your attention to slide 8. This is a
`brief overview of the Ikoma reference. Ikoma is also directed to
`regular layout. If you look at figure 3A of Ikoma which is on the
`left, all the gates those are the red structures, are rectangular
`shape and the extend in a common direction, in this case the
`vertical direction. Exactly the same way as Patent Owner
`explains what it means to be a regular layout in the context of
`the '523 patent and what Ikoma focuses on the is the way to form
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`a gate contact to ensure that the gates actually stay rectangular
`even when they make contact with the gate contact.
`To just kind of put it simply, the gate on the gate contact I
`am just going to say (phonetic) here, is the gate contact would
`come down to meet the gates. In order to do that structure
`they're extremely small. There are a couple of ways to make
`sure that they will hit each other. One is that around the location
`where you would have the contact being made with the last gate,
`that's what is called forming a contact landing pad and there's a
`drawback to that because the gate is no longer rectangular shape.
`The other way to do that is to ensure that the gates and that's the
`way is was supposed to be in a rectangular shape and just have a
`loss (phonetic) of gate contact and no assigned (phonetic) gate
`contact to ensure that it's going to hit each other, that you want
`the gates contacts, they have to make contact. That is exactly
`what is taught in Ikoma. The only requirement is the gate is
`larger -- the gate contact is larger than the gate. It's overlapping
`both sizes of the edges of the gate as shown in figure 3B and it's
`claimed in the '523 patent and it's exactly consistent w ith the
`description in the '523 patent as it relates to gate contact and in
`fact that's the reason why, even though we're talking about the
`prior art here we have shown the gate contact structures of the
`'523 patent figure 7B right next to the Ikoma figure 3A on the
`slide.
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`
`So with that, slides 9 and 10 we will be now discussing the
`disputed issues and slides 9 and 10 at least have those issues,
`sort of a table of contents. I would call them as a roadmap, so
`that unless Your Honors want to take a different order I would
`go through this order and discuss these issues.
`So the first issue I want to address is slide 12, is about
`figure 4+5 and specifically I want to address Patent Owner's
`argument that figure 4+5 is a (indiscernible) and complicated
`figure. That's absolutely not the case. The figure 4+5 simply
`illustrates express teachings of Yano. As we've seen in the brief
`overview of Yano, I'll get into some more detail, Yano teaches
`that the cells 400 and 500 of figure 4+5 are cells of the same
`standard cell library that are meant to be combined together and
`meant to be laid out right next to each other. They're meant to
`be snapped on to each other and for example, the reason that
`Patent Owner teaches the cells are the same height, that the cells
`have to share the same power and ground lines is so that they can
`be snapped on to each other just like Dr. Shanfield shows in
`figure 4+5. That's not the only reason, although that in and of
`itself is sufficient to support what Dr. Shanfield has done
`respectively on the slide. Dr. Shanfield also explained that a
`person of ordinary skill in the art consistent with the teachings
`of Yano that the standard cells are used to form combined from
`larger circuits, that the person of skill in the art would be
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`motivated to specifically to pick cell 400 and 500 and lay them
`out the way he has done with figure 4+5.
`In order to implement very common and very important
`circuits, circuits that we have to see integrated circuit without
`those in them which are multiplexers which are flip- flop circuits.
`In fact, Yano figure 7 is a circuit schematic of a flip-flop circuit,
`such an important circuit that would benefit from the layout of
`figure 4+5 the way Dr. Shanfield has done. So in sum, figure
`4+5 is not at all hindsight-driven. It's not all a fabricated figure.
`It is grounded and the express teachings of Yano it is grounded
`in the knowledge of a person of skill in the art independent of
`'523 patent.
`
`So the last two bullets I summarized there is pointing out
`well, what's the Patent Owner's argument and what is Dr.
`Khatri's, which is Patent Owner's expert's argument? Again with
`that backdrop, we asked for that evidence. Dr. Khatri -- the
`Patent Owner by the way and you probably will see in their
`slides, now admits that standard cells are the same standard cell
`library are meant to be combined together. They cannot get
`around that point, that figure you will see in their slides. But
`what they are arguing still is that cell 400-500 of figure 4+5 are
`of different standard cells library. This is contrary to the
`express teachings of Yano that we see that says that it is building
`a semiconductor integrated circuit using it meaning a standard
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`cell library.
`But how do they get to that point? But, and how do they
`argue that they are of different standard cell libraries? Dr.
`Khatri admits that what he did was measure figure 4+ and figure
`5 using a ruler and then because the ruler's measurements come
`out to be different, his position is that the heights therefore are
`from standard cell libraries. Obviously, and it was clear and
`we'll see and we'll show you in one of the slides his testimony,
`deposition testimony on that point it was completely obvious
`to this patent that figure 4 and figure 5 cannot be to scale
`(phonetic) because one is in the portrait mode and the other one
`is landscape.
`JUDGE DERRICK: Counsel.
`MR. NYUGEN: Yes.
`JUDGE DERRICK: Can you direct us to some -- what's at
`record, some statement in Yano stating the cell 400 and cell 500
`are in fact in the same standard cell library as opposed to simply
`being in a -- that they can be included in a standard cell library.
`
`MR. NYUGEN: Yes, Your Honor. All the cells, as I will
`point to -- I guess we'll just point right away. So if you look at
`slide 13, as I said the present -- in slide 13 which is somewhat of
`a repeat of the slide where I think I had an overview of Yano --
`it says that the present invention relates to a standard cell library
`and a semiconductor integrated circuit using it. In other words
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`every cell that is being discussed in the present invention, which
`is the invention of Yano, all of those cells belong to the same
`standard cell library, be it cell 400, be it cell 500 of figure 4 and
`5 or be it cell 100 of figure 1, they are all in the same standard
`cell library. That's the point, Your Honor, that is clear from
`here. That's why I cite (phonetic) that statement.
`And another point I would say that makes it clear is that
`Yano in the second paragraph there on slide 13, i t's saying that
`those standard cells are of the same height, that they have the
`same source wiring structures and they're relying on uniform and
`you can clearly see that in figure 4 and 5 to the left, they are the
`same height. The source wiring structure in other words on top
`is the power line and you can see that the metal line can see they
`snap on and continue bearing power across all the cells. You can
`see that the bottom blue line is very ground wire, can see the
`snap-ons of the ground scaling (phonetic) across to all the cells.
`We can see that the cells are uniform, can see that the width of
`the gates are the same in figure 4 and 5 and more importantly,
`figure 4 as well as figure 5 has a spacing S1 between the gates.
`Every gate and dummy gate in each cell is regularly spaced, have
`uniform spacing as one can usually see. First of all, S1 is
`labelled in both figure 4 and figure 5 and you can see that they
`are identical when you look at them visually. That's one. So
`that's the support for what we're saying that cell 400, and there
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`are other statements as well, but that's our support for our
`position. I believe that's a strong position that the cell 400, cell
`500 are part of what Yano teaches as the present invention and
`present invention mapped (phonetic) from a single standard cell
`library. Every cell that are discussed in Yano belongs to that
`same standard cell library.
`JUDGE DERRICK: Well counsel, so there may be a
`difference between every cell being disclosed belonging to a
`standard cell library and belonging to a single standard cell
`library. Is there anything else indicating that every single cell
`in, disclosed in Yano, belong to the same one, such that can be
`interchanged or plugged into the same cell or into the same chip?
`MR. NYUGEN: I think that's the, Your Honor, if you're
`asking for is there an express statement in Yano that says cell
`400 and 500 are part of the same standard cell library, just those
`words --
`JUDGE DERRICK: Right.
`MR. NYUGEN: -- the answer is no.
`JUDGE DERRICK: Okay.
`MR. NYUGEN: But for a person of skill in the art reading
`Yano, you know, and when it says the present invention is about
`a standard cell library and this building a semiconductor
`integrated circuit using it meaning that standard cell library, that
`means a single standard cell.
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`
`Moreover, when you see that each of the figures is designed
`such that they have the same height, the same source wiring
`structure, the same spacing. They really follow the same exact
`rules. They are intended to be in the same standard cell library
`and they tend to be combined and spaced right next to each other
`and tended to be snapped on to each other.
`JUDGE DERRICK: I understand your position.
`MR. NYUGEN: Thank you, Your Honor. And so back I
`was just explaining and Your Honor was just talking about the
`sort of the layout reason, there's a physical reason, the layout
`reason why combining figure 4 and figure 5 the way Dr.
`Shanfield has done is completely consistent with the teachings of
`Yano and motivated by Yano, but as I have said before it is also
`motivated from a circuit point of view. Consistent also with the
`teachings of Yano that standard cells are used, combined
`together to form more complicated circuits, Yano, for example,
`has in figure 7 a flip-flop circuit. That's at the bottom right of
`slide 14 and the inverters in that -- and consistent to, flip-flop
`circuit is a very common circuit. Like I said we would be hard
`pressed to find integrated circuit without flip-flop circuits and
`within that the flip-flop has component circuits. Some of these
`components are inverters. Those are highlighted in blue.
`Inverters are, to quote Rabaey which is one of the textbooks that
`we sometimes cite is the nucleus of this design. This design,
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-01637 (Patent 10,141,335)
`
`seems like these were designed without inverters and it also has
`these flip-flop circuit in red, they are annotated in red. Those
`are transmission gates and those are extremely common circuit
`especially when used in context of selection circuit, such as
`multiplexers.
`Another very common circuit that has these two
`components, inverters and transmission gates, is the multiplexers
`and that's the figure right above the Yano figure 7 annotation and
`we can see that the transmission gates are highlighted in the
`dotted line in red and the inverters are highlighted in the dotted
`line in blue. Now t he inverters in the multiplexer that's shown in
`the transistor level showing there's a pair of transistors while in
`Yano they're shown in symbolic (phonetic) form, the triangle
`with the (indiscernible) at the end is recognizable or is
`recognized as being a symbol of the inverter.
`Why do we make that point and why did Dr. Shanfield
`point out that? Because if you look at the cell on figure 4+5.
`The left part of that figure which is cell 500 of figure 5, you
`have gates, these long gates. The gate structures in red are long
`and they cross the PMOS diffusion region that is tan color and
`then they cross the sort of the yellowish NMOS diffusion region.
`Each of those gates in the cell 500 of figure 5 is a paired gate
`and that's what we need for an inverter. That’s ideally suited for
`an inverter and in fact all of the cells of Yano, cell 500 is the
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`IPR2019-01520 (Patent 10,186,523)
`IPR2019-01521 (Patent 10,186,523)
`IPR2019-01522 (Patent 10,186,523)
`IPR2019-01636 (Patent 10,141,334)
`IPR2019-0163
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