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`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 1
`
`

`

`iv
`
`Contents
`
`Newnes
`An imprint of Elsevier Science
`Linacre House, Jordan Hill, Oxford OX2 8DP
`200 Wheeler Road, Burlington MA 01803
`
`First published 1997
`Reprinted 2000, 2001
`Second edition 2003
`
`Copyright © 2003, Steve Heath. All rights reserved
`
`The right of Steve Heath to be identified as the author of this work
`has been asserted in accordance with the Copyright, Designs and
`Patents Act 1988
`
`No part of this publication may be reproduced in any material form (including
`photocopying or storing in any medium by electronic means and whether or not
`transiently or incidentally to some other use of this publication) without the
`written permission of the copyright holder except in accordance with the
`provisions of the Copyright, Designs and Patents Act 1988 or under the terms
`of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham
`Court Road, London, England W1T 4LP. Applications for the copyright
`holder’s written permission to reproduce any part of this publication should be
`addressed to the publisher
`
`TRADEMARKS/REGISTERED TRADEMARKS
`Computer hardware and software brand names mentioned in this book are
`protected by their respective trademarks and are acknowledged
`
`British Library Cataloguing in Publication Data
`A catalogue record for this book is available from the British Library
`
`Library of Congress Cataloguing in Publication Data
`A catalogue record for this book is available from the Library of Congress
`
`ISBN 0 7506 5546 1
`
`Typeset by Steve Heath
`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 2
`
`

`

`Embedded processors
`
`17
`
`This is used to provide local data storage for programs and to store
`information for the processor such as return addresses for subrou-
`tine jumps and interrupts.
`The stack pointer provides additional storage for the pro-
`grammer: it is used to store data like return addresses for subrou-
`tine calls and provides additional variable storage using a PUSH/
`POP mechanism. Data is PUSHed onto the stack to store it, and
`POPed off to retrieve it. Providing the programmer can track
`where the data resides in these stack frames, it offers a good
`replacement for the missing registers.
`8 bit data restrictions
`An 8 bit data value can provide an unsigned resolution of
`only 256 bits, which makes it unsuitable for applications where a
`higher resolution is needed. In these cases, such as financial,
`arithmetic, high precision servo control systems, the obvious
`solution is to increase the data size to 16 bits. This would give a
`resolution of 65536 — an obvious improvement. This may be
`acceptable for a control system but is still not good enough for a
`data processing program, where a 32 bit data value may have to be
`defined to provide sufficient integer range. While there is no
`difficulty with storing 8, 16, 32 or even 64 bits in external memory,
`even though this requires multiple bus accesses, it does prevent
`the direct manipulation of data through the instruction set.
`However, due to the register model, data larger than 8 bits
`cannot use the standard arithmetic instructions applicable to 8 bit
`data stored in the accumulator. This means that even a simple 16
`bit addition or multiplication has to be carried out as a series of
`instructions using the 8 bit model. This reduces the overall effi-
`ciency of the architecture.
`The code example is a routine for performing a simple 16 bit
`multiplication. It takes two unsigned 16 bit numbers and produces
`a 16 bit product. If the product is larger than 16 bits, only the least
`significant 16 bits are retained. The first eight or so instructions
`simply create a temporary storage area on the stack for the
`multiplicand, multiplier, return address and loop counter. Com-
`pared to internal register storage, storing data in stack frames is
`not as efficient due the increased external memory access.
`Accessing external data consumes machine cycles which
`could be used to process data. Without suitable registers and the
`16 bit wide accumulator, all this information must be stored
`externally on the stack. The algorithm used simply performs a
`succession of arithmetic shifts on each half of the multiplicand
`stored in the A and B accumulators. Once this is complete, the 16
`bit result is split between the two accumulators and the temporary
`storage cleared off the stack. The operation takes at least 29
`instructions to perform with the actual execution time totally
`dependant on the values being multiplied together. For compari-
`son, most 16/32 bit processors such as the MC68000 and 80x86
`families can perform the same operation with a single instruction!
`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 3
`
`

`

`Embedded processors
`
`21
`
`processor and was used in many of the early home computers such
`as the Amstrad CPC series. It was also used in many embedded
`designs partly because of its improved performance and also for
`its built-in refresh circuitry for DRAMs. This circuitry greatly
`simplified the external glue logic that was needed with DRAMs.
`The Z80 was originally packaged in a 40 pin DIP package
`and ran at 2.5 and 4 MHz. Since then other packages and speeds
`have become available including low power CMOS versions —
`the original was made in NMOS and dissipated about 1 watt. Zilog
`now use the processor as a core within its range of Z800
`microcontrollers with various configurations of on-chip RAM and
`EPROM.
`Z80 programming model
`The Z80 programming model essential consists of a set of 8
`bit registers which can be paired together to create 16 bit versions
`for use as data storage or address pointers. There are two register
`sets within the model: the main and alternate. Only one set can be
`used at any one time and the switch and data transfer is performed
`by the EXX instruction. The registers in the alternate set are
`designated by a ´ suffix.
`
`Main
`register
`set
`
`Alternate
`register
`set
`
`A
`B
`D
`H
`
`A’
`B’
`D’
`H’
`
`F
`C
`E
`L
`
`F’
`C’
`E’
`L’
`
`Program counter
`PC
`Index register IX
`Index register IY
`Stack pointer SP
`IV
`MR
`
`BC
`DE
`HL
`
`BC’
`DE’
`HL’
`
`The Z80 programming model
`
`The model has an 8 bit accumulator A and a flags register
`known as F. This contains the status information such as carry,
`zero, sign and overflow. This register is also known as PSW
`(program status word) in some documentation. Registers B, C, D,
`E, H and L are 8 bit general-purpose registers that can be paired to
`create 16 registers known as BC, DE and HL. The remaining
`registers are the program counter PC, two index registers IX and
`IY and a stack pointer SP. All these four registers are 16 bits in size
`and can access the whole 64 kbytes of external memory that the
`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 4
`
`

`

`24
`
`Embedded systems design
`
`Port A
`
`Port B
`
`Port C
`
`Port D
`
`SCI
`
`SPI
`
`Internal bus
`
`4144 bytes
`EPROM
`
`176 bytes
`RAM
`
`240 bytes Boot
`ROM
`
`HC05 processor
`core
`
`Clock
`
`Watch
`dog
`
`16 bit timer
`
`Baud rate
`generator
`
`Example microcontroller (Motorola MC68HC705C4A)
`
`12
`
`11 10 9
`
`0
`
`0
`
`0
`
`0
`
`12
`
`11 10 9
`
`8
`
`0
`
`8
`
`7
`
`7
`
`7
`
`1
`
`7
`
`7
`
`1
`
`6
`
`6
`
`6
`
`1
`
`6
`
`6
`
`1
`
`5
`
`5
`
`5
`
`4
`
`4
`
`4
`
`3
`
`3
`
`3
`
`2
`
`2
`
`2
`
`1
`
`1
`
`1
`
`0
`
`0
`
`0
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`Accumulator (A)
`
`Index register (X)
`
`Stack pointer (SP)
`
`Program counter (PC)
`
`5
`
`4
`
`3
`
`2
`
`1
`
`0
`
`1 H I N Z C
`
`Condition code
`register (CCR)
`
`Half-carry flag
`
`Interrupt mask
`
`Negative flag
`
`Zero flag
`
`Carry/borrow flag
`
`68HC05 programming model
`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 5
`
`

`

`44
`
`Embedded systems design
`
`To prevent an interrupt request generating multiple ac-
`knowledgements, the internal interrupt mask is raised to the
`interrupt level, effectively masking any further requests. Only if a
`higher level interrupt occurs will the processor nest its interrupt
`service routines. The interrupt service routine must clear the
`interrupt source and thus remove the request before returning to
`normal execution. If another interrupt is pending from a different
`source, it will be recognised and cause another acknowledgement
`to occur.
`
`Error recovery and control signals
`There are three signals associated with error control and
`recovery. The bus error BERR*, HALT* and RESET* signals can
`provide information or be used as inputs to start recovery proce-
`dures in case of system problems.
`The BERR* signal is the counterpart of DTACK*. It is used
`during a bus cycle to indicate an error condition that may arise
`through parity errors or accessing non-existent memory. If BERR*
`is asserted on its own, the processor halts normal processing and
`goes to a special bus error software handler. If HALT* is asserted
`at the same time, it is possible to rerun the bus cycle. BERR* is
`removed followed by HALT* one clock later, after which the
`previous cycle is rerun automatically. This is useful to screen out
`transient errors. Many designs use external hardware to force a
`rerun automatically but will cause a full bus error if an error occurs
`during the rerun.
`Without such a signal, the only recourse is to complete the
`transfer, generate an immediate non-maskable interrupt and let a
`software handler attempt to sort out the mess! Often the only way
`out is to reset the system or shut it down. This makes the system
`extremely intolerant of signal noise and other such transient
`errors.
`The RESET* and HALT* signals are driven low at power-up
`to force the MC68000 into its power-up sequence. The operation
`takes about 100 ms, after which the signals are negated and the
`processor accesses the RESET vector at location 0 in memory to
`fetch its stack pointer and program counter from the two long
`words stored there.
`
`Motorola MC68020
`The MC68020 was launched in April 1984 as the ‘32 bit
`performance standard’ and in those days its performance was
`simply staggering — 8 million instructions per second peak with
`2–3 million sustained when running at 16 MHz clock speed. It was
`a true 32 bit processor with 32 bit wide external data and address
`buses as shown. It supported all the features and functions of the
`MC68000 and MC68010, and it executed M68000 USER binary
`code without modification (but faster!).
`
`Patent Owner, Bot M8 LLC - Ex. 2027, p. 6
`
`