(12) United States Patent
`Takeda et al.
`
`USOO6394905B1
`(10) Patent No.:
`US 6,394,905 B1
`(45) Date of Patent:
`*May 28, 2002
`
`(54) SYSTEMS AND METHODS FOR PROVIDING
`SECURITY IN A WIDEO GAME SYSTEM
`N
`(75) Inventors: Genyo Takeda, Kyoto; Shuhei Kato,
`Otsu; Satoshi Nishiumi, Kyoto, all of
`(JP) s
`s
`s
`
`(73) Assignee: Nintendo Co., Ltd., Kyoto (JP)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`This patent is Subject to a terminal dis-
`claimer.
`
`(21) Appl. No.: 09/660,586
`(22) Filed:
`Sep. 12, 2000
`
`Related U.S. Application Data
`
`(63) Continuation of application No. 09/379,109, filed on Aug.
`23, 1999, which is a continuation-in-part of application No.
`08/850,676, filed on May 2, 1997, now Pat No. 6,071,191,
`Sh,signing, arriage.N.'s562,
`7
`(51) Int. Cl.' .................................................. G06F 1700
`(52)
`... 463/29: 463/36; 463/43
`(58) Field of Search .............................. 463/29, 36,43,
`463/44, 45, 46, 47
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,755,641 A 8/1973 Rackman
`3,772,662 A 11/1973 Blair
`(List continued on next page.)
`FOREIGN PATENT DOCUMENTS
`
`DE
`EP
`
`40 18052
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`O114522
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`
`
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`List
`tinued
`t
`(List continued on next page.)
`Primary Examiner John Paradiso
`(74) Attorney, Agent, or Firm Nixon & Vanderhye P.C.
`(57)
`ABSTRACT
`A video game System includes a game cartridge which is
`pluggably attached to a main console having a main
`processor, a 3D graphics generating coprocessor, expand
`able main memory and player controllers. A multifunctional
`peripheral processing Subsystem external to the game micro
`processor and coprocessor is described which executes
`commands for handling player controller input/output to
`thereby lessen the processing burden on the graphics pro
`cessing Subsystem. The player controller processing Sub
`System is used for both controlling player controller input/
`output processing and for performing game authenticating
`Security checks continuously during game play. The periph
`eral interface includes a micro-processor for controlling
`various peripheral interface functions, a read/write random
`acceSS memory, a boot ROM, a coprocessor command
`channel interface, a player controller channel interface, etc.,
`which components interact to efficiently process player
`controller commands while also performing other important
`functions without requiring Significant main processor pro
`cessing time. A peripheral interface macro may be executed
`to Start a read or write transaction with each peripheral
`device and thereafter transfer the transaction results Stored in
`the random access memory to the game microprocessor
`main memory. The peripheral interface performs Security in
`addition to input/output functions. The peripheral interface
`interacts with a Security microprocessor chip within an
`external Storage unit. The Video game System authenticates
`the Security microprocessor chip, and also authenticates the
`Video game program Stored on a storage medium within the
`external Storage unit.
`
`13 Claims, 34 Drawing Sheets
`
`IPR2020-01218
`Sony EX1005 Page 1
`
`

`

`US 6,394.905 B1
`Page 2
`
`U.S. PATENT DOCUMENTS
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`
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`5,230,039 A 7/1993 Grossman et al.
`5.245,320 A 9/1993 Bouton
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`D357,712 S
`4/1995 Wu
`5,426,762 A * 6/1995 Nakagawa .................. 395/425
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`D363,092 S
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`D375,326 S
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`5,593,350 A
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`1/1998 Tai
`RE35,839 E.
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`6,022,274 A
`2/2000 Takeda et al. ................ 463/29
`6,071,191. A * 6/2000 Takeda et al. ....
`... 463/29
`6,190,257 B1
`2/2001 Takeda et al. ................ 463/29
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`EP
`EP
`EP
`EP
`
`6/1986
`O2O6704 A2
`5/1988
`O 268 419
`O449530 A2 3/1991
`431 732
`6/1991
`O 47O 615
`2/1992
`
`IPR2020-01218
`Sony EX1005 Page 2
`
`

`

`US 6,394,905 B1
`
`Page 3
`
`EP
`EP
`EP
`EP
`EP
`EP
`EP
`EP
`GB
`GB
`GB
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`W0
`WO
`W0
`WO
`WO
`
`0 553 532
`0 724 220
`0 632 407 A1
`0 633 533 A2
`0 649 118 A2
`0 676 719 A2
`0 676 726 A2
`0 685 246
`2033763
`2 244 546
`2 263 802
`50—22475
`53—17849
`57—2084
`57—18236
`57—136217
`59—40258
`59—121500
`61—16641
`61—198286
`61—185138
`62—269221
`2—31256
`2—41342
`2—68404
`3—16620
`2—68404
`3—248215
`4—26432
`4—20134
`4—42029
`4—106594
`4—104893
`4—291468
`5—100759
`5—19925
`5—199925
`5—177057
`5—241502
`6—23148
`6—54962
`6—68238
`6—110602
`6—114683
`6—114686
`6—190145
`6—190147
`6—205010
`6—285259
`6—290277
`6—315095
`7—104930
`7—116343
`7—178242
`7—222865
`7—288006
`7—317230
`7—317230
`8—45392
`62—269221
`WO 92/09347
`WO94/10685
`WO 94/12999
`WO94/27205
`WO97/17651
`
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`7/1994
`1/1995
`1/1995
`4/1995
`10/1995
`10/1995
`12/1995
`5/1980
`12/1991
`8/1993
`3/1975
`6/1978
`1/1982
`1/1982
`8/1982
`3/1984
`7/1984
`1/1986
`9/1986
`11/1986
`11/1987
`2/1990
`3/1990
`5/1990
`1/1991
`5/1991
`11/1991
`1/1992
`2/1992
`2/1992
`8/1992
`9/1992
`10/1992
`4/1993
`5/1993
`5/1993
`7/1993
`9/1993
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`
`OTHER PUBLICATIONS
`
`Open GL Reference Manual, “The Official Reference Don-
`cument for OpenGL, Release 1,” OpenGL Architecture
`Review Board, Copyright 1992 by Silicon Graphics, Inc.
`
`MIPS Microprocessor R4000 User’s Manual, First Edition,
`by Joe Heinrich, Copyright 1993 by MIPS Technologies,
`Inc.
`
`MIPS Microprocessor R4000 User’s Manual, Second Edi-
`tion, by Joe Heinrich, Copyright 1994 by MIPS Technolo-
`gies, Inc.
`MIPS RISC Architecture, “Introducing the R4000 Technol-
`ogy,” by Gerry Kane and Joe Heinrich, Copyright 1992 by
`MIPS Technologies. Inc.
`MIPS Open RISC Technology, “R4400 Microprocessor
`Product Information,” by Satya Simha. MIPS Technologies,
`Inc., Sep. 27, 1993.
`INDY—TMG—(09/93). Copyright
`INDY Product Guide,
`1993 by Silicon Graphics, Inc.
`Open GL It’s Everywhere, Information Sheet. OPGL—BRO
`(07/93), Copyright 1993 by Silicon Graphics. Inc.
`Reality Engine/Reality Engine Graphics Subsystems, Data
`Sheet. Copyright 1993 by Silicon Graphics. Inc.
`INDY Technical Report, INDY—TR (06/93) Copyright 1993
`by Silicon Graphics, Inc.
`Reality Engine In Visual Simulation Technical Overview,
`RE—VisSim—TR(8/92), Copyright 1992 by Silicon Graphics.
`Inc.
`
`Rambus Architectural Overview, DL0001—02, Copyright
`1992, 1993 by Rambus Inc.
`SH7600 Series Super H Risc Engine. Overview, Hitachi
`manual. Oct. 17, 1994.
`This is What It’s Like to Give Your Next ProductA 32—Bit
`RISC Controller, Hitachi America, Ltd. brochure, 1994.
`SEGA Genesis Instruction Manual, SEGA, Hayward, Cali-
`fornis, #3701—926—0—01 (1994).
`SEGA Genesis 32X Instruction Manual, SEGA, Redwood
`City California, #672—2116 (1994).
`Knuckles Chaotix Instruction Manual, SEGA, Redwood
`City, California, #84503 (1995).
`3D Ballz Instruction Booklet, Accclade, San Jose, Califor-
`nia, #3050—00231 ReV. A.
`SONIC 2 the Hedgehog Instruction Manual, SEGA, Hay-
`ward, California , #672—0944 3701—925—0 —01 (1992).
`PR Newswire, Sony Enters the CD—ROM—Based Video
`Game, New York, Ny, May 31, 1991.
`Sony PlayStation Instruction Manual, and informational
`materials. Sony Computer Entertainment Inc. 1995.
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`disk; 2) hand controller; 3) internal circuit boards (top View);
`4) internal circuit boards (top View); 5) compact disk reader
`(bottom View); and internal main circuit board (bottom
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`trum HoloByte, Alameda, California, #3031BM 208858.
`Nintendo Power, vol. 31, pp. 74—76, PilotWings article.
`Nintendo Power, vol. 38, pp. 25, PilotWings article.
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`ment System, SNS—PW—USA, copyright 1991.
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`Nintendo Player’s Guide, pp. 82—83 and 160, copyright
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`
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`
`PR Newswire, Sony enters the CD—ROM—Based Video
`Game, New York, Ny, May 31, 1991.
`
`|PR2020-01218
`
`Sony EX1005 Page 3
`
`IPR2020-01218
`Sony EX1005 Page 3
`
`

`

`US 6,394.905 B1
`Page 4
`
`“Hardware Reset With Microcode Warning Period”, IBM
`Technical Disclosure Bulletin, vol. 33, No. 11, Apr. 1991,
`pp. 105-106.
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`
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`Program Protection,” E.J. Lengyel et al.
`* cited by examiner
`
`IPR2020-01218
`Sony EX1005 Page 4
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 1 of 34
`
`US 6,394.905 B1
`
`
`
`IPR2020-01218
`Sony EX1005 Page 5
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 2 of 34
`
`US 6,394.905 B1
`
`
`
`
`
`
`
`
`
`IPR2020-01218
`Sony EX1005 Page 6
`
`

`

`U
`
`May 28, 2002
`
`Sheet 3 0f 34
`
`US 6,394,905 B1
`
`
`
`22A.mmn52:
`
`2.
`
`
`
`29:25Emma
`
`m~25.que:22”m“.nE:38E:33Pu.E:I.a.S.a:s.
`
`-.22.
`
`.55..o:
`
`Fllli
`
`«03qu:2=22
`
`2:
`
`5”.Eu
`
`2.>5
`mm:A
`
`hmé
`
`mommmuoEOmEE
`
`
`
`35:52..5EEEE
`
`agave—35:2
`
`
`
`2m;mm?
`
`|PR2020-01218
`
`Sony EX1005 Page 7
`
`IPR2020-01218
`Sony EX1005 Page 7
`
`
`
`
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 4 of 34
`
`US 6,394.905 B1
`
`Reset SW
`
`PUSH
`
`r
`
`NT2
`
`PUSH
`
`> 0.5s
`
`- -
`
`0.5s
`
`2.8V
`
`POWER
`
`Res C
`
`CldCap
`
`CldRes
`
`2.8V
`
`X 5ns
`
`Fig. 3B
`
`IPR2020-01218
`Sony EX1005 Page 8
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 5 of 34
`
`US 6,394.905 B1
`
`00g
`
`RDB8-RDB
`--WD)
`
`BuscIR witH
`st H in
`TXCLKSIN
`
`RDB8-RDB
`
`300b
`
`
`
`RORAM2
`
`BSCR
`BUSENABLE
`
`
`
`Fig. 4(A) PoWER or RESEicircuits
`--WDD
`+VDD +VD0C
`139
`
`RESE
`
`:
`
`,
`----------
`
`06
`
`INT
`
`tests
`
`CART
`
`
`
`RESE
`
`RDB8-RDBOW
`
`PCHCMD
`PCHRSP
`
`BUSCR
`-USENABLE
`
`C.
`
`COLORESET I
`
`
`
`
`
`BE
`
`RXCK -
`XCK
`EXPANSION
`
`SN
`
`- - - -
`
`was mm we an are a- - - - -
`
`
`
`
`
`37
`
`----------
`OSCATOR FSO
`OSCN
`FSO/5
`FSC
`FSEL
`
`OSCOUT
`
`YAHS
`MASTERCOCK
`
`SYSAD3
`SYSAD
`
`ALEH
`ALE
`
`ADCLK
`AUDLRCLK
`AUDATA
`
`SYSCM)4.
`SYSCMDO
`
`s
`
`AC
`
`s
`SRGB
`
`200
`
`SYNC
`
`WCLK
`COPROCESSOR
`YAH
`---
`
`IPR2020-01218
`Sony EX1005 Page 9
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 6 of 34
`
`US 6,394.905 B1
`
`PERPHERAL
`INTERFACE
`
`38
`
`PCHCLK
`PCHCMD
`PCHRSP
`
`NT2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`04a
`
`VIDEO DIA
`CONVERTER
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`ADO MXER
`AMP
`CHN
`CH2N
`chlou,
`(H2OUT
`
`VIDEO
`ENCODER
`
`TO/FROM
`SERIAL INPUT/OUTPUT
`CONNECTOR
`
`Fig. 4B)
`
`VIDEO GAME
`CONSOE 52
`
`1
`
`CARTRIDGE/EXPANSION
`CONNECTORS
`
`54
`
`49
`
`AUDIO/WDEO
`OUTPUT
`CONNECTOR
`
`IPR2020-01218
`Sony EX1005 Page 10
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 7 of 34
`
`US 6,394.905 B1
`
`Fig. 5A
`
`RCP OUTPUTS PChCnd
`
`RCP samples PChRsp
`
`PChClk
`
`PChCmd
`
`RCP
`
`PChRsp
`(Read Data And ACK)
`
`RCP
`
`PChClk
`
`s
`
`P OUTPUTS
`
`i.
`
`Plf samples
`
`o
`
`H
`
`tl
`
`(Command And Write Data)
`
`(Read Duta And ACKk)
`
`aae aas a
`
`IPR2020-01218
`Sony EX1005 Page 11
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 8 of 34
`
`US 6,394.905 B1
`
`1. Read 4B
`
`2. Write 4B
`
`3. Plf Macro
`
`4. Write 648
`Buffer
`
`Phc Llullllllllll/U / Lllllll
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`ChCmd
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`STAR
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`START
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`-i-, -ian -
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`ACK
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`At least Clock
`
`IPR2020-01218
`Sony EX1005 Page 12
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 9 of 34
`
`US 6,394.905 B1
`
`Fig.6A
`
`
`
`IPR2020-01218
`Sony EX1005 Page 13
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 10 of 34
`
`US 6,394.905 B1
`
`
`
`
`
`Fig. 6F
`
`IPR2020-01218
`Sony EX1005 Page 14
`
`

`

`U.S. Patent
`US. Patent
`
`May 28, 2002
`
`Sheet 11 0f 34
`
`US 6,394.905 B1
`US 6,394,905 B1
`
`
`
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`
`mm.—mufizmhz—Emu—EEK
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`|PR2020-01218
`
`Sony EX1005 Page 15
`
`IPR2020-01218
`Sony EX1005 Page 15
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 12 of 34
`
`US 6,394.905 B1
`
`8 *61)
`
`09%
`
`
`
`
`
`IPR2020-01218
`Sony EX1005 Page 16
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 13 of 34
`
`US 6,394.905 B1
`
`Fig. 9A
`
`BUS
`287
`
`290
`
`32
`
`
`
`34
`
`O MODULATOR
`
`FROM DEMODULATOR
`
`CONTROL
`SIGNAL
`
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`
`30
`
`CONTROLLER
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`
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`C.R
`
`s
`298 t
`
`99
`
`PORT 66
`
`IPR2020-01218
`Sony EX1005 Page 17
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 14 of 34
`
`US 6,394.905 B1
`
`
`
`se
`
`-
`
`IPR2020-01218
`Sony EX1005 Page 18
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 15 of 34
`
`US 6,394.905 B1
`
`3S
`
`37
`
`39
`
`32
`
`323
`
`
`
`
`
`
`
`CHANNE, SET
`
`SEND-COUNTER SET
`
`SEND.COUNTER
`s: O.
`
`NO
`
`YES
`
`SET PORT TO
`RECEIVE-MODE
`
`RECEIVE.COUNTER SET
`
`
`
`3S
`
`RECEIVE-COUNTER
`= 0
`
`
`
`37
`
`
`
`379
`
`SE PORT TO
`SEND-MODE
`
`RETURN
`
`Fig. 10A
`
`33
`
`SEND A BYTEDATA
`
`333
`
`DECREMENT
`SEND-COUNTER
`
`RECEIVE A BYTE-DATA
`
`DECREMENT
`RECEIVE-COUNTER
`
`
`
`IPR2020-01218
`Sony EX1005 Page 19
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 16 of 34
`
`US 6,394.905 B1
`
`- 33
`
`SEND A BYTE-DATA
`
`
`
`POR-READY
`FLAG ON
`
`339
`
`SEND A BYTE-DATA
`FROMMEMORY
`TO PORT
`
`
`
`
`
`
`
`
`
`
`
`RECEIVE ABYE-DATA
`
`RETURN
`
`PORT-READY
`FLAG ON
`
`SEND A BYTE-DATA
`FROM PORT TO
`MEMORY
`
`Fig. TOC
`
`RETURN
`
`IPR2020-01218
`Sony EX1005 Page 20
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 17 of 34
`
`US 6,394.905 B1
`
`MEMORY CARD
`
`JOYP ORT
`
`G N
`
`
`
`BUTTON LAYOUT
`
`56
`
`IPR2020-01218
`Sony EX1005 Page 21
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 18 of 34
`
`US 6,394.905 B1
`
`
`
`
`
`
`
`
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`§ 136 || 18
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`IPR2020-01218
`Sony EX1005 Page 22
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 19 of 34
`
`US 6,394.905 B1
`
`Ø Ø ZZZZZZZZ Ø
`
`
`
`Hy!
`
`IPR2020-01218
`Sony EX1005 Page 23
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 20 of 34
`
`US 6,394.905 B1
`
`
`
`ZZZ
`
`
`„^ AgqNWIS NMOG NEMOJ/|
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`|
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`
`
`WWW9WIO 9NIWII D
`
`IPR2020-01218
`Sony EX1005 Page 24
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 21 of 34
`
`US 6,394.905 B1
`
`Fig. 15 EXAMPLE SECURITY CHIP
`MANUFACTURING PROCESS
`
`VIDEO GAME PROGRAM
`
`502
`
`Z% 2
`
`500
`
`
`
`IPR2020-01218
`Sony EX1005 Page 25
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 22 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16A
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDUM
`
`VIDEO GAME PROGRAM
`
`PERPHERAL INTERFACE
`506'
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 26
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 23 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16B
`
`54
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDIUM
`
`PERPHERAL INTERFACE
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 27
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 24 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16C
`
`54
`
`EXTERNAL STORAGE UNIT
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 28
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 25 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16D
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDIUM
`
`VIDEO GAME PROGRAM
`
`2
`
`PERPHERAL INTERFACE
`
`A-KEY
`
`C-?e
`
`504"
`
`up-
`
`2
`
`506'
`
`-> A-CODE
`
`A CODE
`
`510
`
`C
`
`MAIN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 29
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 26 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16E
`
`54
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDUM
`
`VIDEO GAME PROGRAM
`
`2
`
`
`
`PERPHERAL INTERFACE
`
`Acode
`
`Acode."
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 30
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 27 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 16F
`EXTERNAL STORAGE UNIT
`
`54
`
`STORAGE MEDUM
`
`PERPHERAL INTERFACE
`
`GOOR RESET
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 31
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 28 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 17
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDIUM 502
`
`PERPHERAL INTERFACE
`
`VIDEO GAME PROGRAM
`
`(RESET IF
`NOTAUTHENTIC)
`
`VIDEO GAME
`PROGRAM
`AUTHENTICT
`
`MAN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 32
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 29 of 34
`
`US 6,394.905 B1
`
`
`
`Fig. 18
`
`EXTERNAL STORAGE UNIT
`
`STORAGE MEDIUM 502
`
`VIDEO GAME PROGRAM
`
`2
`
`PERPHERAL INTERFACE
`
`(RESET IF
`NOTAUTHENTIC)
`
`VIDEO GAME PROGRAM
`
`EXECUTE 2
`
`MAIN PROCESSOR
`
`MAN UNIT
`
`IPR2020-01218
`Sony EX1005 Page 33
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 30 of 34
`
`US 6,394.905 B1
`
`GAME CARTRIDGE
`
`Fig. 19
`MAN CPU
`
`PF MEMORY
`
`CPU Gamero see chieSEC. CHP
`
`
`
`
`
`LOAD PL3 FROM GAME-ROM
`TO CPU MEMORY
`
`
`
`- P.
`-
`
`COMPUTE PL3 BY A-KEY TO
`GET A-CODE ABOUT PL3
`
`712
`
`PL2
`
`; GAME
`PROGRAM
`
`
`
`PL3 AUTHENTICATE GAME PROGRAM
`
`22 GAME
`PROGRAM
`
`JUMP TO GAME PROGRAM
`NCPU MEMORY
`
`724
`
`
`
`
`
`START GAME PROGRAMAND
`START COMMUNICATION BETWEEN
`PFAND SEC, CHIP
`
`726
`
`COMMUNICATION BETWEEN
`PFAND SEC. CHP
`
`IPR2020-01218
`Sony EX1005 Page 34
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 31 of 34
`
`US 6,394.905 B1
`
`
`
`
`
`
`
`POWer. On
`
`802
`
`804
`
`Receive CASSETTE/BULK-Code
`from SEC, CHIP
`
`Send CASSETTE/BULK-COce
`to CPU
`
`806
`
`808
`
`Receive A-COce from SEC. CHIP
`
`810
`
`8 12
`
`Receive A-Key from SEC. CHIP,
`Send A-Key to CPU
`
`Receive A-Code from CPU
`
`
`
`
`
`NO
`
`
`
`Compare A-Codes
`from SEC. CHIP
`and CPU
`
`814
`
`OK
`
`816
`
`Send GO(1) to CPU
`
`
`
`
`
`
`
`Receive Go(1)
`from CPU
`
`NO
`
`YES
`
`82O
`
`Send Go(2) to SEC. CHIP
`
`TO FIG.20B
`
`-(A)-
`
`Fig. 20A
`
`TO FIG.20B.
`(C)
`TOFg20C:
`(D->
`
`IPR2020-01218
`Sony EX1005 Page 35
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 32 of 34
`
`US 6,394.905 B1
`
`FROM
`FG.
`(A) 20A
`
`Fig. 20B
`
`
`
`-822
`Timer Request
`ON?
`
`NO
`
`Yes
`
`824
`
`Send gies tO
`
`
`
`
`
`eceive GO(3) from CIC
`
`No
`
`Yes
`
`
`
`830
`Yes
`Send Test-calc Request
`to SEC, CHIP
`
`834
`Send received input data
`from CPU to SEC.CHIP
`
`838
`Receive result data from
`SEC.CHP
`
`840
`
`Send result data
`to CPU
`
`IPR2020-01218
`Sony EX1005 Page 36
`
`

`

`U.S. Patent
`
`May 28, 2002
`
`Sheet 33 of 34
`
`US 6,394.905 B1
`
`FROM FIG.20B
`
`Fig. 200
`
`Send SEC
`Communication
`Command
`
`
`
`842
`
`84
`4
`
`Calculate C-COce
`
`84
`6
`
`Send C-COcle to
`SEC Chip
`
`
`
`
`
`84
`8
`
`Receive C-COde
`from SEC Chip
`
`
`
`
`
`Compare C-Code
`
`Infinite Loop,
`NME to CPU
`
`FROM FG, 20A
`
`
`
`
`
`FROM FIG.20A
`-(D)
`
`IPR2020-01218
`Sony EX1005 Page 37
`
`

`

`US. Patent
`
`May 28, 2002
`
`Sheet 34 0f 34
`
`US 6,394,905 B1
`
`co=§§EEoo
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`
`Sony EX1005 Page 38
`
`IPR2020-01218
`Sony EX1005 Page 38
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`

`

`1
`SYSTEMS AND METHODS FOR PROVIDING
`SECURITY IN A WIDEO GAME SYSTEM
`
`US 6,394.905 B1
`
`15
`
`2
`received over one line, clock signals over another line and
`responses are transmitted to the coprocessor over a third
`Serial line. The peripheral interface includes a microproces
`Sor for controlling various peripheral interface functions, a
`read/write random access memory, a boot ROM, a copro
`ceSSor command channel interface, a player controller chan
`nel interface, etc., which components interact to efficiently
`process player controller commands while also performing
`other important functions without requiring Significant main
`processor processing time.
`The coprocessor command channel interface responds to
`coprocessor clock and command control Signals to permit
`access to the random access memory and to the boot ROM
`and generates control Signals to interrupt the peripheral
`interface microprocessor. A peripheral interface macro may
`be executed to start a read or write transaction with each
`peripheral device and thereafter transfer the transaction
`results Stored in the random access memory to the game
`microprocessor main memory.
`In accordance with another aspect of the present
`invention, a portable Storage device is used in the form of a
`game cartridge in the exemplary embodiment having a low
`pinout due in part to the use of a multiplexed address/data
`buS. Memory access related timing Signals are transmitted to
`the cartridge which may be programmably varied depending
`upon detected address domain which is used to establish the
`type of Storage device being used by the Video game System.
`BRIEF DESCRIPTION OF THE DRAWINGS
`These and other features and advantages of the present
`invention will be better and more completely understood by
`referring to the following detailed description of a presently
`preferred exemplary embodiment in connection with the
`drawings, of which:
`FIG. 1 is a perspective view of an exemplary embodiment
`of a Video game System in accordance with the present
`invention;
`FIG. 2 is a block diagram of a Video game console and
`game cartridge shown in FIG. 1,
`FIG. 3A is a block diagram of reset related circuitry
`embodied in the video game console shown in FIG. 2;
`FIG. 3B depicts timing Signals generated by the circuitry
`of FIG. 3A;
`FIGS. 4A and 4B is an exemplary, more detailed, imple
`mentation of the vide game console as shown in the FIG. 2
`block diagram;
`FIG. 5A shows exemplary Signals appearing on the com
`munication channel between the coprocessor in the periph
`eral interface Subsystem;
`FIG. 5B depicts exemplary timing signals for illustrative
`commands communicated on this communication channel;
`to FIGS. 6A-F show exemplary 3D screen effects achiev
`able using the System described herein.
`FIG. 7 is a block diagram of the peripheral interface
`shown in FIG. 2;
`FIG. 8 depicts in further detail the PIF channel interface
`shown in FIG. 7;
`FIG. 9A is a block diagram showing in farther detail the
`joystick channel controller in one of the ports depicted in the
`block diagram of FIG. 7;
`FIG. 9B is an illustrative representation of data from a
`player controller communicated to the peripheral interface
`138;
`FIGS. 10A through 10C are flowcharts depicting the
`Sending and receiving modes of operation for the player
`controller channel shown in FIG. 7;
`
`25
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`This is a continuation of application Ser. No. 09/379,109
`filed Aug. 23, 1999, which is a continuation in part of
`application Ser. No. 08/850,676 filed May 2, 1997 (now U.S.
`Pat. No. 6,071,191), which is a continuation-in-part of
`application Ser. No. 08/562,288 filed Nov. 22, 1995 (now
`U.S. Pat. No. 6,022,274).
`FIELD OF THE INVENTION
`The present invention relates to a high performance low
`cost Video game System. More particularly, the invention
`relates to a Video game System having a multifunctional
`player controller processing Subsystem with Security
`features, and a flexibly expandable video game external
`memory with a low pin out.
`BACKGROUND AND SUMMARY OF THE
`INVENTION
`Microprocessor-based home Video game Systems. Such as
`the Nintendo Entertainment System and the Super Nintendo
`Entertainment System have been highly Successful in part
`because they can interactively produce exciting videograph
`ics involving numerous animated moving objects.
`The Video game System described herein and in further
`detail in a concurrently filed patent application, which has
`been incorporated herein by reference and names Van Hook
`et all as inventors, permits game play involving three
`dimensional images having a depth and realism far exceed
`ing these and other heretofore known video game Systems.
`In the past, computer Systems required to produce Such
`images interactively costs tens of thousands of dollars.
`In order to provide Such a high performance Video game
`System at a cost affordable to the average consumer, many
`features in the Video game System were uniquely optimized.
`In So doing, many unique features were incorporated into the
`40
`System described herein using novel, multifunctional com
`ponents having a low pinout, but which provide for highly
`flexible future expansion.
`The processor and/or picture processing unit of Video
`game Systems. Such as the Nintendo Entertainment System
`and the Super Nintendo Entertainment System exercise
`direct control over processing of Signals from player input/
`game control devices, i.e., player controllers. These prior art
`Systems do not include a player controller processing Sub
`System which coacts with the game microprocessor and
`picture processing unit to proceSS commands for handling
`player controller related input/output.
`The present invention is directed in part to a multifunc
`tional peripheral processing Subsystem external to the game
`microprocessor and disclosed coprocessor which executes
`commands for handling player controller input/output to
`thereby lessen the processing burden on the graphics pro
`cessing Subsystem. the peripheral processing Subsystem is
`used for both controlling player controller input/output
`processing and for performing game authenticating Security
`checks continuously during game play. The peripheral pro
`cessing Subsystem is also used during the game cartridge/
`Video game System console initial communication protocol
`using instructions stored in its boot ROM to enable initial
`game play.
`The peripheral interface is coupled to the coprocessor by
`a three bit wide serial bus over which commands are
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`IPR2020-01218
`Sony EX1005 Page 39
`
`

`

`US 6,394.905 B1
`
`3
`FIG. 11 shows an exemplary player controller with a
`memory card;
`FIG. 12 is a block diagram of an exemplary cartridge
`memory device and associated accessing circuitry;
`FIGS. 13 and 14 are exemplary timing control and data
`Signals associated with the memory System depicted in FIG.
`12;
`FIG. 15 shows an example process for manufacturing
`external Storage units embodying Security features,
`FIGS. 16A-16F show an example embodiment of an
`overall video game Security arrangement that tests whether
`a Video game program and Storage unit Security chip match;
`FIG. 17 shows an additional video game Security arrange
`ment embodiment;
`FIG. 18 shows a still additional video game security
`arrangement embodiment;
`FIG. 19 is a simplified flowchart of a further embodiment
`of example Security Steps performed by a Video game main
`proceSSOr,
`FIGS. 20A-20C are a simplified flowchart of a further
`embodiment of example Security Steps performed by a video
`game peripheral interface; and
`FIG. 21 is a simplified flowchart of a further embodiment
`of example Security Steps performed by a video game
`Security chip.
`
`DETAILED DESCRIPTION OF EXEMPLARY
`EMBODIMENT
`FIG. 1 shows an exemplary embodiment of a Video game
`system 50 in accordance with the present invention. Illus
`trative video game System 50 includes a main console 52, a
`Video game Storage device 54, and handheld controllers
`56a,b (or other user input devices). Main console 52 is
`connected to a conventional home color television set 58.
`Television set 58 displays 3D video game images on its
`television Screen 60 and reproduces Stereo Sound through its
`SpeakerS 62a, b.
`In the illustrative embodiment, the Video game Storage
`device 54 is in the form of a replaceable memory cartridge
`insertable into a slot 64 on a top surface 66 of console 52.
`A wide variety of alternative program Storage media are
`contemplated by the present invention such as CD ROM,
`floppy disk, etc. In this exemplary embodiment, Video game
`Storage device 54 comprises a plastic housing 68 encasing a
`printed circuit board 70. Printed circuit board 70 has an edge
`72 defining a number of electrical contacts 74. When the
`Video game Storage device 68 is inserted into main console
`slot 64, the cartridge electrical contacts 74 mate with cor
`responding "edge connector' electrical contacts within the
`main console. This action electrically connects the Storage
`device printed circuit board 72 to the electronics within main
`console 52. In this example, at least a “read only memory”
`chip 76 is disposed on printed circuitboard 70 within storage
`device housing 68. This “read only memory' chip 76 stores
`instructions and other information pertaining to a particular
`Video game. The read only memory chip 76 for one game
`cartridge Storage device 54 may, for example, contain
`instructions and other information for an adventure game
`while another Storage device 54 may contain instructions
`and information to play a car race game