I 1111111111111111 11111 1111111111 1111111111 111111111111111 IIIIII IIII IIII IIII
`US008487659B2
`
`c12) United States Patent
`Kapusta
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 8,487,659 B2
`Jul. 16, 2013
`
`(54) COMPARATOR WITH ADAPTIVE TIMING
`
`(75)
`
`Inventor: Ronald Kapusta, Bedford, MA (US)
`
`(73) Assignee: Analog Devices, Inc., Norwood, MA
`(US)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 151 days.
`
`(21) Appl. No.: 13/092,465
`
`(22) Filed:
`
`Apr. 22, 2011
`
`(65)
`
`Prior Publication Data
`
`US 2012/0268185 Al
`
`Oct. 25, 2012
`
`(51)
`
`(2006.01)
`
`Int. Cl.
`G0JR 25100
`(52) U.S. Cl.
`USPC ....... 327/3; 327/12; 327/43; 327/57; 327/261
`( 58) Field of Classification Search
`USPC ............... 327/3, 9, 12, 33, 37, 43, 45, 51, 52,
`327/57
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,027,116 A
`6/ 1991 Armstrong et al.
`5,247,241 A
`9/1993 Ueda
`6,400,302 Bl
`6/2002 Amazeen et al.
`7,095,345 B2
`8/2006 Nguyen et al.
`7,167,121 B2
`1/2007 Carreau et al.
`7,342,463 B2
`3/2008 Brokaw et al.
`7,400,118 Bl
`7/2008 Zhang et al.
`7,425,857 B2 *
`9/2008 Confalonieri et al. ........ 327/264
`
`7,701,256 B2
`7,834,793 B2
`8,044,654 B2
`8,063,675 B2 *
`8,248,108 B2 *
`2008/0100490 Al
`2008/0284406 Al
`2009/0102780 Al
`2009/0273739 Al
`
`4/2010 Hurrell et al.
`11/2010 Carreau et al.
`10/2011 Kapusta, Jr.
`11/2011 Igarashietal ................ 327/143
`8/2012 Santoro et al. .................. 327/63
`5/2008 Chatal et al.
`11/2008 Kapusta
`4/2009 Brown
`11/2009 Brown
`
`OTHER PUBLICATIONS
`
`Analog Devices Inc., "14-Bit, 2500 MSPS, RF Digital-to-Analog
`Converter", AD9739 Datasheet, Rev. 0, 56 pages, Jan. 2009.
`Chen et al., "A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-
`µm CMOS," IEEE Journal ofSolid-State Circuits, vol. 41, No. 12,pp.
`2669-2680, Dec. 2006.
`Ginsburg et al., "Dual Time-Interleaved Successive Approximation
`Register ADCs for an Ultra-Wideband Receiver," IEEE Journal of
`Solid-State Circuits, vol. 42, No. 2, pp. 247-257, Feb. 2007.
`Verma et al., "An Ultra Low Energy 12-bit Rate-Resolution Scalable
`SAR ADC for Wireless Sensor Nodes," IEEE Journal of Solid-State
`Circuits, vol. 42, No. 6, pp. 1196-1205, Jun. 2007.
`
`* cited by examiner
`
`Primary Examiner - An Luu
`(74) Attorney, Agent, or Firm - Kenyon & Kenyon LLP
`
`ABSTRACT
`(57)
`An adaptive delay device that provides a delay to a signal
`based on circuit conditions such as temperature, supply volt(cid:173)
`age values and/or fabrication processes. The adaptive delay
`device may respond to circuit conditions by charging a
`capacitive device to a threshold voltage. A comparator may
`incorporate the adaptive delay device to provide adaptive
`timing for the comparator functions thereby attaining
`improved noise performance and/or reduce power consump(cid:173)
`tion.
`
`11 Claims, 7 Drawing Sheets
`
`IN
`
`PREAMPLIFIER
`a.tQ
`
`-
`
`LATCH
`320
`
`- OUT
`
`RESET
`
`ADAPTIVE
`DELAY
`~
`
`RESET_DEL
`
`HS
`
`1, mt
`
`RESET~
`
`I
`
`RESET_DEL
`
`LS
`
`LS
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 1
`
`

`

`\0 = N
`
`UI
`O'I
`-....l
`00
`~
`00
`
`d r.,;_
`
`(PRIOR ART)
`
`FIG. 1
`100
`
`DELAY 125
`
`DEL_RESET
`
`0 ....
`....
`.....
`rJJ =(cid:173)
`
`('D
`('D
`
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`
`OUT
`
`127
`
`LATCH
`
`_, I PREAMPLIFIER i---------..i
`
`123
`
`RESET
`
`output)
`
`from SHA and DAG
`between analog input
`
`(signal difference
`
`IN
`
`~
`
`0 ....
`
`:-'
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`....
`2'
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`N
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`~ = ~
`
`~
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`
`120
`
`COMPARATOR
`
`:-
`
`105
`SHA
`
`:-
`
`INPUT
`ANALOG
`
`~
`~
`
`~
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 2
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 2 of 7
`
`US 8,487,659 B2
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 3
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 3 of 7
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`US 8,487,659 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 4
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 4 of 7
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`US 8,487,659 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 5
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 5 of 7
`
`US 8,487,659 B2
`
`i ,.,, Change
`
`Delay
`
`:
`
`RESET
`
`RESET DEL
`
`HS
`
`------------ ---l-
`0.7V
`
`Capacitor Vth
`Voltage
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`Capacitor
`Voltage
`
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`to
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`t3
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`FIG. 5
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 6
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 6 of 7
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`US 8,487,659 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 7
`
`

`

`U.S. Patent
`
`Jul. 16, 2013
`
`Sheet 7 of 7
`
`US 8,487,659 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 8
`
`

`

`US 8,487,659 B2
`
`1
`COMPARATOR WITH ADAPTIVE TIMING
`
`FIELD OF INVENTION
`
`The present invention relates to signal processors, and 5
`more particularly to a device for tracking operation of adja-
`cent circuitry in response to process, voltage and temperature
`(PVT) variations experienced by the adjacent circuitry.
`
`2
`increase, the delay between amplifying the input signal and
`releasing the latch adaptively changed to allow the preampli-
`fier or latch more time to operate on the input signal to fill the
`sampling period. This provides the advantage ofbetter signal-
`to-noise ratios and/or lower power.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`BACKGROUND
`
`Successive approximation register (SAR) analog-to-digi-
`tal converters (ADC) perform analog to digital conversions.
`The SAR ADC includes a number of different components
`including comparators.
`FIG. 1 illustrates a conventional comparator configuration
`within a SAR ADC. A conventional SAR ADC 100 includes
`an analog input, a sample and hold amplifier 105, a digital(cid:173)
`to-analog converter (DAC) 110, a comparator 120, and logic
`130. The comparator 120 includes a pre-amplifier 123, a 20
`delay device 125 and latch 127. The pre-amplifier 123 ampli(cid:173)
`fies the input signals and outputs the amplified input signal to
`the latch, improving the input referred noise and linearity of
`the comparator. In order to allow the preamplifier 123 time to
`amplify the input signal, a control signal RESET is delayed 25
`before going to the latch, so that the latch is held in a known
`reset state while the preamplifier is amplifying. Once the
`delayed reset signal is released, the latch will regenerate and
`the comparator makes it decision. The delay of the delay
`device 125 is fixed by inserting an inverter or series of invert- 30
`ers in the circuit path. A delayed output signal DEL_RESET
`from the delay device 125 is provided to the latch 127. FIG. 2
`illustrates an exemplary timing diagram of a conventional
`comparator, such as comparator 120.
`Typically, as shown, by the preamplifier output 230, the 35
`preamplifier 123 operates for some period of time (tl to t2)
`before the latch 127 is released. The maximum speed of a
`SAR ADC 100 is dependent upon the operating speed of the
`digital logic and switches such as those that form the com(cid:173)
`parator 120. The operating speed of the digital logic and 40
`switches, e.g., inverters and latches, vary in response to vari(cid:173)
`ous circuit conditions such as variations in the supply voltage,
`variations in temperature, or fabrication process variations
`across different manufacturing lots of integrated chips.
`Examples of fabrication process parameters may be device 45
`characteristics, such as threshold voltage and oxide thickness.
`When the delay through the delay elements 125 becomes
`shorter because of the faster operating conditions, such as
`rises in circuit temperature, supply voltage increases, process
`effects, or other conditions, the signal DEL_RESET 220 may 50
`be output sooner. Consequently, the preamplifier 123 has less
`time to amplify before the latch 127 is released, as shown by
`240. However, the increased comparator 120 operating speed
`due to the change in parameters is generally lost because the
`sample rate of the ADC is typically held constant. In other 55
`words, the preamplifier 123 and latch 127 within the com(cid:173)
`parator 120 may finish operating sooner on a given input, but
`ultimate output of the latch signal still has to wait until the end
`of the sampling period because the ADC is still clocked at the
`sampling rate, which remains unchanged.
`The inventor has recognized the benefit of a device that
`operates opposite to the effects of PVT variations. An exem(cid:173)
`plary implementation of an application of the device is for a
`comparator in a SAR ADC that adaptively adjusts its timing
`to take advantage of changes in conditions and circuit param- 65
`eters to provide better performance. For example, it would be
`beneficial if, as the digital logic and switching speeds
`
`FIG. 1 illustrates a conventional comparator configuration
`10 within a SAR ADC.
`FIG. 2 illustrates an exemplary timing diagram of the con(cid:173)
`ventional comparator of FIG. 1.
`FIG. 3 illustrates an exemplary implementation of a com(cid:173)
`parator with an adaptive delay according to an embodiment of
`15 the present invention.
`FIG. 4 illustrates an exemplary configuration of an adap(cid:173)
`tive delay device according to an embodiment of the present
`invention.
`FIG. 5 illustrates an exemplary timing chart of an adaptive
`delay according to an embodiment of the present invention.
`FIG. 6 illustrates an exemplary timing diagram of the
`operation of an adaptive delay device according to an embodi(cid:173)
`ment of the present invention.
`FIG. 7 illustrates an analog-to-digital converter according
`to an embodiment of the present invention.
`
`DETAILED DESCRIPTION
`
`Embodiments of the present invention may provide a delay
`device that may dynamically adapt its delay based on PVT
`variations in the circuit environment in a manner that coun(cid:173)
`teracts traditional PVT effects. Thus, if PVT effects ordi(cid:173)
`narily cause other transistors within a circuit to switch at a
`faster rate (for example, driving voltages increase or tempera-
`ture decreases), the delay device increases its delay to operate
`at a slower rate. The delay device may be used as a control
`element to gate operations of other components within a
`circuit system, which can stabilize the system's throughput
`even when large PVT variations occur.
`In another embodiment, the delay element may include an
`inverter, a capacitor and an output transistor. The inverter may
`invert a control signal that is input to the delay element. The
`capacitor may be coupled to the inverter's output and may
`begin charging when the inverter's output transitions to a high
`voltage level. The output transistor may have a gate coupled
`to the capacitor and its source coupled to a high supply volt-
`age. The output transistor may pull an output of the delay
`element high when the gate voltage is lower than the high
`supply voltage ( e.g., V DD) by an amount that exceeds the
`threshold voltage ( e.g., V,h). When the capacitor charges to an
`amount (e.g., VC) that is within the threshold (IV DD-
`VC] I <V,h), the output transistor may cease to conduct and the
`output voltage may drop to ground.
`In another embodiment, a comparator may include an
`adaptive delay device. A comparator may include an input for
`an input signal, a control signal input, an output, a preampli(cid:173)
`fier, an adaptive delay device and a latch, both the preampli(cid:173)
`fier and the latch may be responsive to a control signal. The
`control signal may allow the preamplifier to amplify the input
`60 signal, and provide it to the latch. The adaptive delay device
`may respond to circuit conditions in the comparator, and in
`response, may adaptively delay the control signal applied to
`the preamplifier from being applied to the latch. After the
`delay time period, the control signal may be output to the
`latch. The latch may resolve the amplified input signal upon
`receipt of the delayed control signal, and output a digital
`representation of the input signal.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 9
`
`

`

`US 8,487,659 B2
`
`3
`FIG. 3 illustrates a comparator with an adaptive delay
`according to an embodiment of the present invention. The
`exemplary comparator 300 may include a preamplifier 310, a
`latch 320 and an adaptive delay element 330, all of which may
`be fabricated in a common integrated circuit, and may operate 5
`from a common supply voltage, e.g., VDD (not shown). Thus,
`PVT conditions should apply to all circuit elements within the
`comparator 300 nearly identically.
`The preamplifier 310 may have inputs for an input signal
`(IN) and a control signal (RESET) and an output for output- 10
`ting an amplified representation of the input signal. The latch
`320 may have an input coupled to an output of the preampli(cid:173)
`fier and an input for receiving a delayed control signal (RE(cid:173)
`SET _DEL) from the adaptive delay element 330 and an out(cid:173)
`put for outputting a voltage (OUT) representative of the 15
`digital value of the input signal IN.
`The adaptive delay element 330 may have an input for
`receiving the control signal RESET, and an output for output(cid:173)
`ting the delayed control signal RESET_DEL. The adaptive
`delay element 330 may have a circuit structure that inverts 20
`effects of PVT that may occur in the preamplifier 310 and the
`latch 3 20. Thus, if switches of the preamplifier 310, latch 3 20
`and delay element 330 may operate faster in response to
`decreased temperature and/or increased supply voltage
`VDD), the circuit structure of the adaptive delay element 330 25
`may add delay to its operations in a manner that counteracts
`the PVT effects. The circuit architecture of the delay element
`330, therefore, may stabilize throughput of the comparator
`300 even in the presence of PVT effects.
`The adaptive delay element 330 may include an inverter 30
`331, a capacitor 333, a transistor 335 and an impedance
`element 337. The inverter 331 may receive the control signal
`RESET and be powered by a high supply voltage HS. The
`output of the inverter 331 may be connected to capacitor 333
`and to a gate terminal of transistor 335. The capacitor 333 35
`may also be connected to a low supply voltage LS, which may
`be ground. The source terminal of the transistor 335 may be
`connected to the high supply voltage HS, and the drain ter(cid:173)
`minal of the transistor 335 may be connected to the imped(cid:173)
`ance element 337. The impedance element 337 may also be 40
`connected to the low supply voltage LS. The output of the
`adaptive delay element 330 may be at the node between
`transistor 335 and impedance element 337. In operation,
`when a high RESET signal is applied to the inverter 331, the
`inverter 331 outputs a low signal causing the capacitor 333 to 45
`discharge. With the capacitor 333 discharged, transistor 335
`has a significant voltage between its gate and source, and will
`strongly conduct, pulling the output RESET_DEL high.
`When RESET goes low, the inverter 331 outputs a high signal
`causing capacitor 333 to charge. The voltage across capacitor 50
`333 may eventually rise to within a threshold voltage of the
`high supply HS, causing transistor 335 to shut off. The output
`voltage RESET_DEL is then pulled low through impedance
`element 337, and will be output.
`FIG. 4 is a circuit diagram of an adaptive delay element 400 55
`according to an embodiment of the present invention. The
`adaptive delay element 400 may include an inverter 405 hav(cid:173)
`ing an input for the control signal RESET, and an output
`RESET_DEL for outputting a delayed control signal, transis(cid:173)
`tors 411 and 420, a capacitor 425, and a pair of impedance 60
`elements 431 and 430. The impedance elements 431 and 430
`may be a resistor, transistor or some other device that may
`function as a current source.
`The inverter 405 may include transistors 411 and 410 that
`may have their respective gate terminals connected to the 65
`adaptive delay element 400 input (RESET). A source termi(cid:173)
`nal of transistor 411 may be connected to a terminal ofa first
`
`4
`impedance element 431. A drain terminal of transistor 411
`may be connected to a drain terminal of transistor 410. A
`source terminal of transistor 410 may be connected to ground
`(or VSS). Another terminal of first impedance element 431
`may be connected to VDD. The commonly connected drains
`of transistors 411 and 410 may be connected to an interme(cid:173)
`diate node (Node A). The intermediate node (Node A) may
`also be connected to a gate terminal of transistor 420 and a
`terminal of capacitor 425. Also connected to VDD may be a
`source terminal of transistor 420. The gate (or control input)
`terminal of transistor 420 may be connected to the interme(cid:173)
`diate node (Node A). The drain terminal oftransistor420 may
`be connected to the output of the adaptive delay element 400
`and to a terminal of the second impedance element 430.
`The second impedance element 430 may be connected
`between the drain terminal of the transistor 420 and ground
`( or VSS). Capacitor 425 may be connected between Node A
`and ground ( or VSS). The capacitor 425 may also be a tran(cid:173)
`sistor configured as a capacitance device, or a device other
`than a capacitor that provides suitable capacitance. The out(cid:173)
`put of the adaptive delay element 400 may be connected
`between the drain of transistor 420 and the second impedance
`element 430.
`When operating, the adaptive delay element 400 may
`respond to conditions of other circuit components in the SAR
`ADC, for example, the supply voltage control and decision
`logic 130 of FIG. 1. The circuit components of the adaptive
`delay element 400 may be fabricated in the same processes as
`the other SAR ADC components. As a result, the adaptive
`delay element 400 may respond to a particular circuit condi(cid:173)
`tion in a similar manner as the other components in the SAR
`ADC due to the similar fabrication process. Or, the adaptive
`delay element 400 may be supplied with a common voltage
`source. In other words, the response to the circuit conditions
`by the adaptive delay element 400 will be substantially simi(cid:173)
`lar to the response of the other components of the SAR ADC
`to the same circuit conditions.
`The first impedance element 431 may provide a constant
`source of current at a substantially fixed magnitude regardless
`of the voltage VDD. In addition, one of either transistor 410
`and 411 may always be on. The signal timing of the adaptive
`delay element 400 will be explained with reference to the
`timing diagram in FIG. 5. In a first example (ex. 1), when
`signal RESET is high, transistor 411 may be off and transistor
`410 may be on. As a result, the gate voltage applied to delay
`transistor 420 may be low, which causes transistor 420 to
`conduct, and RESET_DEL may also be high. So initially,
`both signals RESET and RESET _DEL may be high as shown
`attimet0 in FIG. 5. When the signal RESET goes low (at time
`t1 in FIG. 5), transistor 410 may tum off and transistor 411
`may tum on, current from impedance element 431 may begin
`charging capacitor 425. The voltage on the capacitor 425 may
`rise in the form of a ramp function at a fixed slope. The current
`provided by the impedance element 431 may not respond to
`changes in VDD.
`As capacitor 425 charges, the gate voltage of transistor 420
`(i.e., node A voltage) provided by capacitor 425 may remain
`below the transistor 420 threshold voltage, and the transistor
`420 may continue to conduct. As a result, signal RESET_
`DEL may be held high. Eventually, when the gate voltage of
`transistor 420 rises to within a threshold ofVDD ( e.g., within
`the gate-source voltage V Gs of transistor 420 shown as 0.7
`volts), transistor 420 will shut off, and the signal RESET_
`DEL may be pulled low ( as shown at time t2 in FIG. 5) by the
`second impedance element 431 as the capacitor 425 dis(cid:173)
`charges. The signal RESET_DEL remains low until the
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 10
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`US 8,487,659 B2
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`5
`RESET signal goes high, and again both RESET and
`RESET_DEL are high (at time t3 of FIG. 5). The cycle may
`repeat based on the RESET signal.
`In the first example, the gate-source voltage of delay tran(cid:173)
`sistor 420 is shown as 0.7 volts. In other words, once the
`difference between the supply voltage HS and the gate volt(cid:173)
`age provided by capacitor 425 is less than 0. 7 volts, the delay
`transistor 420 may begin to no longer conduct. In a second
`example ( ex. 2), due to fabrication process variations, the gate
`source voltage V Gs of transistor 420 is 0.6 volts, which means
`transistor 420 has a smaller threshold voltage. The operation
`of the overall circuit is similar. Both the RESET signal and the
`RESET_DEL are initially high as shown at time tO. Both
`signals remain high for a time, until time t1 of FIG. 5, and then
`the RESET signal goes low, and the capacitor 425 begins to
`charge. Because of the fabrication process change, the capaci-
`tor voltage must rise higher, which takes a longer time. As a
`result, instead ofRESET_DEL falling to low at time t2 as in
`ex. 1, its delay changes, and it falls later at time t4. Examples
`1 and 2 illustrates that, in order to shut off transistor 420, the
`capacitor 425 must charge to a voltage that is responsive to
`conditions that affect circuit components. Accordingly, the
`time periods tl-t2 (t4) may adapt due to the effects of PVT
`variations.
`In another example of the affects of PVT, when VDD is
`low, the capacitor 425 does not have to charge to as high of a
`voltage to reach the threshold voltage because the threshold
`voltage is lower due to the lower VDD. As a result, the delay
`is less since current provided by impedance element 431 is
`unaffected by variations in VDD and the threshold voltage is
`lower.
`The output signal RESET_DEL may signal the latch to
`release its value for the input signal. An adaptive delay device 35
`as described with respect to FIG. 4 may be implemented
`adjacent to other circuit components that may be affected by
`PVT effects, and the adaptive delay device may react
`inversely to oppose the PVT effects on the other, adjacent
`circuit components. An adaptive delay device as shown in 40
`FIG. 4 may provide improved conversion noise performance
`by providing, for example, a preamplifier with additional time
`to amplify an analog input signal.
`As explained above, certain circuitry operates more slowly
`or quickly as temperatures around or in the circuit compo- 45
`nents rise or fall. The changes in temperature may be
`accounted for by using a current source for charging capacitor
`425 that provides a current that is proportional to temperature.
`Circuits, such as proportional-to-absolute
`temperature
`(PTAT) and complimentary-to-absolute temperature (CTAT) 50
`circuits that output a current or voltage signal in response to
`temperature variations are known. By leveraging this known
`technology, a circuit can be provided that not only responds to
`process fabrication differences, and supply voltage variation,
`but also to changes in temperature.
`FIG. 6 illustrates an adaptive delay with an exemplary
`implementation of PTAT current source according to an
`embodiment of the present invention. Such an implementa(cid:173)
`tion may provide better power efficiency, and improved noise
`performance.
`The configuration of transistors 640, 641, 642, capacitive
`element 647, impedance element 643 and PTAT current
`source 630 may be similar to the configuration of inverter
`405, transistor 420, capacitive element 425 and impedance
`element 430 in FIG. 4. The PTAT current source 630 may 65
`replace impedance element 431 of FIG. 4. The PTAT current
`source 630 may include transistors 616, 627, 628, and 644
`
`6
`(which may be PMOS transistors), transistor 615 (which may
`be an NMOS transistor), resistance element 611, and an
`impedance element 631.
`In the PTAT current source 63 0, the transistor 644 that may
`5 have a source terminal connected to VDD, a drain terminal
`connected to a source terminal transistor 641, and a gate
`terminal may be connected to a gate terminal of PMOS tran(cid:173)
`sistor 616. While transistors 616, 627 and 628, transistor 615,
`resistance element 611 and impedance element 631 may be
`10 configured to form an amplifier with a negative feedback
`loop. The PMOS transistors 628 and 627 may be configured
`as a current mirror. The impedance element 631 may be used
`to provide a bias current.
`Source terminals of transistors 628 and 627 may be con-
`15 nected to VDD, and the gate terminals of transistors 628 and
`627 may be commonly connected. The drain of transistor 628
`may be connected to the commonly connected gates of tran(cid:173)
`sistors 628 and 627, and the drain of transistor 627 may be
`connected to a terminal of impedance element 631 Another
`20 terminal of impedance element 631 may be connected to
`ground ( or VSS). A drain terminal of the transistor 615 may
`be connected to the drain of transistor 628, and a source
`terminal may be connected to ground ( or VSS), and a gate
`terminal may be connected to a node at a terminal of resis-
`25 tance element 611. A source terminal of the transistor 616
`may be connected to VDD. A drain terminal of transistor 616
`may be connected to a node in common with the gate terminal
`of transistor 615 at a terminal of resistance element 611. A
`gate terminal of transistor 616 may be connected to a node at
`30 a drain terminal of transistor 627, and to the gate terminal of
`transistor 644.
`Resistance element 611 may have another terminal con(cid:173)
`nected to ground ( or VSS). Resistance element 611 is illus(cid:173)
`trated as a resistor but may be implemented using a transistor,
`or other device.
`During operation, the current through transistor 616 may
`be equal to the current Ir through resistance element 611. In
`other words, Ir,.,(VGS of transistor 615)/R value of 611 since
`the voltage at node B above resistance element 611 is con(cid:173)
`nected to gate of transistor 615.
`Transistors 628 and 627 may form a current mirror that
`may provide a current mirrored from a drain terminal of
`transistor 615 to impedance element 631. The transistor 615
`may be sized so it has a gate-source voltage VGS that is
`proportional to temperature. In other words, as temperature
`rises, the VGS of transistor 615 rises, and as temperature
`decreases, the VGS of transistor 615 decreases. This tempera(cid:173)
`ture reaction property of transistor 615 may be accomplished
`through sizing the gate length and width. For example, the
`gate length can be made long and the gate width can be made
`small with respect to the gate length. However, the ratio will
`vary from fabrication process to fabrication process.
`Transistor 615 may sized to be a transistor that operates
`with a large overdrive voltage, in which case the transistor
`55 615 gate voltage may be very much greater than the transistor
`615 threshold voltage (i.e., VGS>>VT).
`Transistors 616 and 644 may have currents that are a ratio
`of one another based on the sizing of each transistor since the
`gate voltage applied to each is the same. Accordingly, tran-
`60 sistor 644 may pass a current that is a ratio ( e.g., 1: 1, 2: 1,
`0.75: 1 and similar ratios) of the current through transistor
`616. The PTAT current source 630 generates a current that
`varies proportionally to temperature. The current may be
`delivered via transistor 644. As circuit temperature decreases,
`the current may decrease, while conversely the delay of the
`falling RESET signal may be further delayed from being
`asserted because transistor 644 allows limited current to pass,
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 11
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`US 8,487,659 B2
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`5
`
`7
`in which case, charging of capacitive element 647 takes
`longer. In addition, the adaptive delay 600 may also compen(cid:173)
`sate for variations in supply voltages and fabrication process
`changes as described above with reference of FIG. 4, for
`example.
`Of course, a PTAT current source 630 may be implemented
`in a variety of configurations including, for example, using
`area-ratioed bipolar transistors with emitter degeneration that
`are common in traditional bandgap circuits or other configu(cid:173)
`rations as known by those of ordinary skill in the art. The 10
`PTAT current generator 630 shown in FIG. 6 is only an
`example.
`In addition to the above described implementations for an
`exemplary adaptive delay, other implementations of the adap(cid:173)
`tive delay have been envisioned by the inventor. FIG. 7 illus- 15
`trates an additional exemplary implementation.
`The illustrated ADC 700 may include a comparator 730,
`and an adaptive delay 731. The comparator 730 may receive
`inputs from two inputs, and a delay control signal. For
`example, the two inputs (Input #1 and Input #2) may form a
`differential input, with which the comparator will make a
`decision as to whether the differential input is positive or
`negative. Alternatively, the two inputs might include one ana(cid:173)
`log input (e.g. Input #1) and one reference input (e.g. Input
`#2), in which case the comparator may make a decision as to
`whether the analog input is greater than or less than the
`reference input. The adaptive delay 731 may receive a control
`signal that is intended to cause the comparator to resolve the
`analog input and output a digital representative voltage. The
`adaptive delay 731 may respond to changes in surrounding
`circuit component conditions ( e.g., temperature, fabrication 30
`process variations or supply voltage variations), and adapt the
`delay to allow for better noise response of the comparator
`and/or better power performance.
`Several features and aspects of the present invention have
`been illustrated and described in detail with reference to 35
`particular embodiments by way of example only, and not by
`way of limitation. It will be appreciated that modifications
`and variations of the present invention are covered by the
`above teachings and within the purview of the appended
`claims without departing from the spirit and intended scope
`of the invention. For example, NMOS devices may be inter(cid:173)
`changed with PMOS devices, and vice versa. Applied volt(cid:173)
`ages may also be changed accordingly.
`
`40
`
`20
`
`8
`3. The comparator of claim 2, wherein a current source
`provides the current to the capacitive element, and the current
`is proportional to the temperature of circuit components of
`the comparator.
`4. The comparator of claim 3, wherein the current source
`comprises:
`a first pair of transistors configured as a current mirror;
`a second pair of transistors with commonly connected con(cid:173)
`trol inputs connected to a drain terminal of one transistor
`of the first pair of transistors; and
`a single transistor with a control input connected to a ter(cid:173)
`minal of a resistive element.
`5. A successive approximation register analog-to-digital
`converter on an integrated circuit chip configured with a
`plurality of on-chip circuit components, comprising:
`a comparator for determin