Patent No. 8,487,659
`Petition For Inter Partes Review
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`
`v.
`
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 8,487,659
`
`_______________
`
`Inter Partes Review No. IPR2020-01219
`____________________________________________________________
`
`DECLARATION OF DR. DOUGLAS HOLBERG
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1002 Page 1
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`Inter Partes Review of U.S. Patent No. 8,487,659
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`TABLE OF CONTENTS
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`
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`Page
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`I.
`
`II.
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`III.
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`IV.
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`V.
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`INTRODUCTION ............................................................................................................. 1
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`EXPERIENCE AND QUALIFICATIONS ....................................................................... 1
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`DOCUMENTS CONSIDERED ........................................................................................ 4
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`THE STATE OF THE ART .............................................................................................. 5
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`THE (cid:146)659 PATENT ........................................................................................................... 7
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`A.
`
`B.
`
`C.
`
`Summary ................................................................................................................ 7
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`Effective Filing Date ............................................................................................ 14
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`Level of Ordinary Skill for the (cid:146)659 Patent ......................................................... 14
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`VI.
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`CLAIM CONSTRUCTION ............................................................................................. 15
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`VII. LEGAL STANDARDS ................................................................................................... 15
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`A.
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`B.
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`Anticipation.......................................................................................................... 15
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`Obviousness ......................................................................................................... 16
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`VIII. PRIOR ART ..................................................................................................................... 18
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`A.
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`B.
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`The (cid:146)659 Patent and Yoshioka ............................................................................. 19
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`The (cid:146)659 Patent and Ajit ...................................................................................... 21
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`IX. ANALYSIS AND OPINIONS ........................................................................................ 21
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`A.
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`Ground 1: Claims 5-6, and 9 Are Unpatentable as Anticipated by
`Yoshioka .............................................................................................................. 21
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`B.
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`C.
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`1.
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`2.
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`3.
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`4.
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`Summary of Yoshioka ............................................................................. 21
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`Claim 5 ..................................................................................................... 27
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`Claim 6 ..................................................................................................... 33
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`Claim 9 ..................................................................................................... 39
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`Ground 2: Claim 10 Is Unpatentable as Obvious over Yoshioka ....................... 45
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`Ground 3: Claims 1 and 2 Are Unpatentable as Obvious over Yoshioka
`and Applicant Admitted Prior Art........................................................................ 50
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`1.
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`2.
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`3.
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`The Combination ..................................................................................... 50
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`Claim 1 ..................................................................................................... 52
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`Claim 2 ..................................................................................................... 55
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`i
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`Inter Partes Review of U.S. Patent No. 8,487,659
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`D.
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`Ground 4: Claims 7 and 8 Are Unpatentable as Obvious over Yoshioka
`and Fiscus............................................................................................................. 61
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`1.
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`2.
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`3.
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`4.
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`Summary of Fiscus .................................................................................. 61
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`The Combination ..................................................................................... 63
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`Claim 7 ..................................................................................................... 67
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`Claim 8 ..................................................................................................... 68
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`E.
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`Ground 5: Claims 3 and 4 Are Unpatentable as Obvious over Yoshioka,
`Applicant Admitted Prior Art, and Fiscus ........................................................... 73
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`2.
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`3.
`
`4.
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`The Combination ..................................................................................... 73
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`Claim 3 ..................................................................................................... 75
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`Claim 4 ..................................................................................................... 75
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`F.
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`Ground 6: Claims 9-10 Are Unpatentable as Anticipated by Ajit ...................... 76
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`1.
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`2.
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`3.
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`4.
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`Summary of Ajit ...................................................................................... 76
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`Claim 9 ..................................................................................................... 89
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`Claim 10 ................................................................................................... 95
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`Claim 11 ................................................................................................... 96
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`G.
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`Ground 7: Claims 1 and 5 Are Unpatentable as Obvious over Ajit and
`Applicant Admitted Prior Art .............................................................................. 97
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`1.
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`2.
`
`3.
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`The Combination ..................................................................................... 97
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`Claim 1 ..................................................................................................... 98
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`Claim 5 ................................................................................................... 101
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`X.
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`CONCLUSION .............................................................................................................. 104
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`ii
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`APPENDIX LIST FOR DECLARATION OF DR. DOUGLAS HOLBERG
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`Appendix Description
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`Appendix
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`Curriculum Vitae
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`List of Materials Considered
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`
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`A
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`B
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`iii
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`Inter Partes Review of U.S. Patent No. 8,487,659
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`I.
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`INTRODUCTION
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`1.
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`My name is Dr. Douglas R. Holberg. I have been retained as an
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`expert witness on behalf of Petitioner Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd.
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`(collectively, (cid:147)Petitioner(cid:148) or (cid:147)Xilinx(cid:148)) to provide expert opinions on the validity of
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`United States Patent No. 8,487,659 ((cid:147)the (cid:146)659 patent,(cid:148) Ex. 1001).
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`2.
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`I am being compensated at my normal rate, plus reimbursement for
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`expenses, for my analysis. My compensation does not depend on the content of
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`my opinions or the outcome of this proceeding.
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`II.
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`EXPERIENCE AND QUALIFICATIONS
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`3.
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`In formulating my opinions, I have relied upon my knowledge,
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`training, and experience in the relevant art. My qualifications are stated more fully
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`in my curriculum vitae, which has been provided as Appendix A. Here, I provide a
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`brief summary of my qualifications.
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`4.
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`My education includes a B.S. in Electrical Engineering from Texas
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`A&M University in 1977, followed by a M.S. in Electrical Engineering from the
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`University of Texas at Austin in 1989. I earned a Ph.D. in Electrical Engineering
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`from the University of Texas at Austin in 1992.
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`5.
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`I have over 40 years of experience in the electronics field. During that
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`time, I have worked for several different electronics companies including: Mostek,
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`Texas Micro Engineering (acquired by Crystal Semiconductor), Crystal
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`Semiconductor, Cirrus Logic, Cygnal Integrated Products, and Silicon
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`
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`Laboratories. I joined Silicon Laboratories when they acquired Cygnal, which I
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`co-founded in 1999.
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`6.
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`I am a named inventor on 40 U.S. patents. I have held a variety of
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`engineering positions throughout my career, from circuit designer, design manager,
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`Director of Engineering, Chief Technology Officer (CTO), Vice President (V.P.)
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`of Engineering, and V.P. of Technology. In addition to my engineering
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`experience, I also have served as an adjunct faculty member at the University of
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`Texas, where I taught CMOS analog and mixed-signal design for six years.
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`7.
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`I am the co-author of the textbook (cid:147)CMOS Analog Circuit Design,(cid:148)
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`the first edition of which published in 1987. As explained in the Preface of the
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`second edition, published in 2002, the objective of the textbook is to teach the
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`fundamentals and background that are necessary to understand how a (cid:147)circuit
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`works.(cid:148) It is now available in third edition and published in English and Chinese
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`(first and second edition). This textbook is widely used throughout the world by
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`new and experienced engineers in industry and by students in the classroom.
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`8.
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`Upon graduating from Texas A&M University, I went to work for
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`Mostek Corporation designing integrated circuits for telecommunications
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`applications. I designed an integrated dual tone multi frequency (DTMF)
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`generator. I received my first patent for this integrated DTMF generator. After
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`2
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`leaving Mostek, I joined a startup company, Texas Micro Engineering, as its
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`
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`second employee. At Texas Micro Engineering, I designed, among other things, a
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`dual-channel (atrium-ventricle) pacemaker sense amplifier/filter using
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`discrete-time switched capacitor technology.
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`9. While enrolled in the Masters/Ph.D. program at the University of
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`Texas at Austin, I worked on the application of bipolar technology to dynamic
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`random access memory (DRAM) sense-amplifier architectures and
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`circuit-simulation algorithms. While at The University of Texas at Austin, I also
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`designed and laid out the mask set (The Holberg Mask Set) still in use by the
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`fabrication class/lab.
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`10. Upon graduating with a Ph.D., I went to work for Crystal
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`Semiconductor/Cirrus Logic, where I designed high frequency synthesizers for
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`hard-disk read-channel applications. I managed a group designing charge-coupled
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`device (CCD) interface circuits for digital camera applications, as well as
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`television encoder chips and CMOS imagers.
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`11. Upon leaving Cirrus, I started a company called Cygnal Integrated
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`Products that develops mixed-signal microcontrollers. At Cygnal, I was the
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`founder, CTO, V.P. of Engineering, and an individual contributor. While at
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`Cygnal, I designed analog-to-digital converters (ADCs), DVbe temperature
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`sensors, input/output (I/O) cells/pads (both design and layout), as well as many
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`3
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`additional miscellaneous circuits. My company was later purchased by Silicon
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`
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`Labs, where I remained employed as a manager of the microcontroller group,
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`followed by the position of V.P. of Technology.
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`12.
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`I have significant experience with the technology described in the
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`(cid:146)659 patent, including resistors, capacitors, diodes, inductors, transistors,
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`transformers, oscillators, operational amplifiers, comparators, general
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`integrated-circuit technology, analog/digital mixed-signal circuits, device analysis
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`and modeling, floor-planning and layout of integrated circuits, and the tools used
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`to design and verify integrated circuits (CAD tools). In addition, I have experience
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`with device modeling and characterization, which has been applied throughout my
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`career.
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`13. My analyses set forth in this declaration are informed by my
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`experience in the field of electrical engineering, including analog circuitry, ADCs,
`
`and digital circuits. Based on my above-described experience, I believe that I am
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`considered to be an expert in the field.
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`III. DOCUMENTS CONSIDERED
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`14.
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`In preparing this Declaration, I have reviewed the (cid:146)659 patent and file
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`history. I also have considered the accompanying Petition for inter partes review,
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`each of the documents cited in this Declaration, and the documents specifically
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`4
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`identified below and in Appendix B. In formulating my opinions, I have further
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`relied upon my extensive experience in the relevant fields.
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`IV. THE STATE OF THE ART
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`15. Figure 1 of the (cid:146)659 patent(cid:151)which Applicant admits is prior art
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`((cid:147)AAPA(cid:148))(cid:151)illustrates a (cid:147)conventional comparator configuration(cid:148) within a
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`successive approximation register analog-to-digital-converter ((cid:147)SAR ADC(cid:148)) 100.
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`(Ex. 1001, 1:16-17.) (cid:147)The comparator 120 includes a preamplifier 123, a delay
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`device 125 and latch 127.(cid:148) (Id. at 1:20-21.)
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`16. The preamplifier 123 amplifies the input signal and outputs the
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`amplified input signal to the latch 127. (Id. at 1:21-23.) To allow the
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`preamplifier 123 time to amplify the input signal before it is captured by latch 127,
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`a control signal RESET is delayed using delay device 125. (Id. at 1:24-30.) Delay
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`
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`device 125 introduces a fixed delay by inserting a series of inverters in the circuit
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`path. (Id.) When the delayed signal DEL_RESET is output from delay device 125
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`and provided to latch 127, latch 127 captures the amplified signal output from
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`preamplifier 123. (Id. at 1:27-37.)
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`17. The speed of a SAR ADC 100 is dependent upon the operating speed
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`of the digital logic and switches (e.g., inverters and latches) that form the
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`comparator 120. (Id. at 1:37-40.) The operating speed of the digital logic and
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`switches varies in response to circuit conditions, such as variations in process,
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`voltage, and temperature ((cid:147)PVT(cid:148)). (Id. at 1:40-44.)
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`18. For example, the circuit system may operate faster due to decreased
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`temperature or increased voltage. (Id.) When delay through delay element 125
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`becomes shorter because of faster operating conditions of the inverters, the signal
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`DEL_RESET would be output sooner. (Id. at 1:47-51.) According to the
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`(cid:146)659 patent, the preamplifier 123 would then have less time to amplify the input
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`signal before latch 127 captures the amplified signal output from preamplifier 123.
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`(Id. 1:66-2:4.) The increased operating speed of the comparator 120 is lost,
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`however, because the sampling rate of the SAR ADC is typically held constant(cid:151)
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`meaning the comparator still has to wait until the end of the sampling period to
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`output a signal. (Id. at 1:53-60.)
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`6
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`V. THE (cid:146)659 PATENT
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`A.
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`Summary
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`
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`19. The (cid:146)659 patent is directed to a delay device that adaptively adjusts its
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`delay to counteract PVT effects on a circuit system. Using admitted prior art
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`Figure 1 as an example, the (cid:146)659 patent asserts that in faster operating conditions,
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`it would be beneficial to allow other components of the comparator more time to
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`operate on the input signal to fill the set sampling period (see id. at 1:61-2:5),
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`thereby stabilizing throughput of the comparator and counteracting PVT effects
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`(id. at 3:19-29). Specifically, it would be beneficial if the delay between
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`amplifying the input signal and releasing the latch (cid:147)adaptively changed(cid:148) to allow
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`the preamplifier 123 more time to operate on the input signal before latch 127
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`captures the amplified signal output from preamplifier 123. (Id. 1:66-2:4.)
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`20. Figure 3 of the (cid:146)659 patent illustrates such an adaptive delay element
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`330. Comparing Figure 3 with AAPA Figure 1, adaptive delay element 330
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`replaces the series of inverters (i.e., delay element 125) in Figure 1, while the
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`remainder of the comparator structure remains the same (compare preamplifier 310
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`in FIG. 3 with 123 in FIG. 1; latch 320 in FIG. 3 with 127 in FIG. 1).
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`21. The circuit structure of adaptive delay element 330 includes an
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`inverter 331, a capacitor 333, a transistor 335, and an impedance element 337. (Id.
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`at 3:30-32.) The inverter 331 receives the control signal RESET and is powered by
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`
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`a high supply voltage HS. (Id. at 3:32-33.) The output of the inverter 331 is
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`connected to capacitor 333 and to a gate terminal of transistor 335. (Id. at 3:33-
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`35.) Capacitor 333 is also connected to a low supply voltage LS, which may be
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`ground. (Id. at 3:35-37.) The source terminal of transistor 335 is connected to
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`high supply voltage HS, and the drain terminal connected to impedance element
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`337, which is also connected to low supply voltage LS. (Id. at 3:37-41.) The
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`output of delay element 330 is a node between transistor 335 and impedance
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`element 337. (Id. at 3:41-43.)
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`22.
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`In operation, when a high RESET signal is applied to the inverter 331,
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`the inverter 331 outputs a low signal, causing the capacitor 333 to discharge. (Id.
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`at 3:43-46.) When capacitor 333 is discharged, the gate to source voltage across
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`transistor 335 becomes greater than the threshold voltage of transistor 335, causing
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`transistor 335 to strongly conduct and turn on. This pulls the output RESET_DEL
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`high. (Id. at 3:43-48.) An annotated portion of Figure 3 below illustrates the
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`circuit operation with high RESET.
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`23. When the RESET signal goes low, the inverter 331 outputs a high
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`signal, causing the capacitor 333 to charge. (Id. at 3:49-50.) The voltage at the
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`terminal of capacitor 333, which is connected to the gate of transistor 335, may
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`eventually rise to the threshold voltage of transistor 335, causing transistor 335 to
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`shut off. (Id. at 3:50-52.) This causes the output voltage RESET_DEL to be
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`pulled low through impedance element 337, which is connected to low supply
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`voltage LS. (Id. at 3:52-54.) An annotated portion of Figure 3 below illustrates
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`the circuit operation with low RESET.
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`24. Changes in PVT will impact the threshold voltage at which the
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`transistor (e.g., 335 in FIG. 3 or 420 in FIG. 4) turns on or off, thereby resulting in
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`a change to the delay generated by the adaptive delay element. Figure 5 illustrates
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`an exemplary timing chart of the adaptive delay element.
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`25.
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`In Example 1 (Ex. 1), when the signal RESET is high, the gate voltage
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`applied to the gate transistor (e.g., 335 in FIG. 3 or 420 in FIG. 4) is low, causing
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`the transistor to conduct, and pulling RESET_DEL high, as shown at t0 of
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`Figure 5. When RESET goes low at t1, the inverter outputs a high signal, causing
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`the capacitor (e.g., 333 in FIG. 3 or 425 in FIG. 4) to charge. As shown between
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`t1 and t2, the capacitor voltage rises as it charges. When the capacitor voltage is
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`below HS (cid:150) Vth (see green regions in annotated FIG. 5), the transistor is on and
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`RESET_DEL remains high. When the capacitor voltage reaches HS (cid:150) Vth (i.e.,
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`HS (cid:150) 0.7V in Ex. 1), the transistor shuts off, pulling RESET_DEL low, as shown
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`at t2 (see red regions in annotated FIG. 5). RESET_DEL remains low until the
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`RESET signal goes high again at t3, and the cycle may repeat based on the RESET
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`signal. (See id. at 4:39-5:3.)
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`26.
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`In Example 2 (Ex. 2) of Figure 5, due to fabrication process variations
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`such as different oxide thickness of the integrated circuit, the threshold voltage to
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`turn off the PMOS transistor 335 in Figure 3 is higher than that in Example 1 (i.e.,
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`HS (cid:150) 0.6 V in Ex. 2 compared with HS (cid:150) 0.7 V in Ex. 1). The capacitor voltage
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`must therefore rise higher (to HS (cid:150) 0.6 V) to reach the threshold voltage for the
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`transistor to turn off. (Id. at 5:9-18.) Assuming the capacitor voltage rises at the
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`same rate, it takes longer to reach HS (cid:150) 0.6 V; therefore, the transistor shuts off
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`later, and RESET_DEL falls to low later at t4 in Figure 5 (see dotted vertical blue
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`line). Examples 1 and 2 illustrate that in order to shut off the transistor, the
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`capacitor must charge to a voltage that is responsive to conditions that affect circuit
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`components (i.e., PVT). Thus, the delay between RESET and RESET_DEL, as
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`depicted by t1 (cid:150) t2 and t1 (cid:150) t4, respectively, adapts to the effects of PVT
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`
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`variations. (Id. at 5:18-25.)
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`B.
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`Effective Filing Date
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`27.
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`I understand that Application No. 13/092,465, which eventually
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`issued as the (cid:146)659 patent, was filed on April 22, 2011, and does not claim priority
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`to any earlier filed application. Based on this, I understand that April 22, 2011 is
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`therefore the effective filing date of the challenged claims for the purposes of this
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`Petition.
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`C. Level of Ordinary Skill for the (cid:146)659 Patent
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`28.
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`I am informed and understand that various factors can be considered
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`in determining a person of ordinary skill in the art (POSITA). I am informed and
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`understand that those factors include: (1) the educational level of the inventors;
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`(2) the type of problems encountered in the art; (3) prior art solutions to those
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`problems; (4) the rapidity with which innovations are made; (5) sophistication of
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`the technology; and (6) education level of active workers in the field.
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`29.
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`I understand that Xilinx proposed in the petition that a person of
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`ordinary skill in the art ((cid:147)POSITA(cid:148)) in the field of the (cid:146)659 patent in 2011 would
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`have at least a Bachelor of Science degree in electrical engineering with two years(cid:146)
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`experience in circuit design. Alternatively, three to four years of relevant
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`professional or practical experience in circuit design may also suffice to qualify a
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`
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`person as one skilled in the art.
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`30.
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`I agree with this level of ordinary skill for the (cid:146)659 patent. Based on
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`my experience, I understand and know of the capabilities of a person of this skill
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`level as of the time the (cid:146)659 patent was filed in 2011. I am familiar with how a
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`POSITA would have understood and used the terminology found in the (cid:146)659 patent
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`at the time of its filing, and with the state of the art at that time.
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`VI. CLAIM CONSTRUCTION
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`31.
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`I have been advised and understand that (cid:147)claim construction(cid:148) is the
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`process of determining a patent claim(cid:146)s meaning. I also understand that, during an
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`inter partes review, a claim construction analysis begins with the plain meaning of
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`the claim term, which is the ordinary and customary meaning given to the term by
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`those of ordinary skill in the art at the time of the invention. I also understand that
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`this standard is sometimes referred to as the Phillips standard. I have been
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`informed that Xilinx does not believe any claim construction is necessary here.
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`VII. LEGAL STANDARDS
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`A. Anticipation
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`32.
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`It is my understanding that the claims of a patent are anticipated by a
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`prior art reference if each and every element of the claim is found either explicitly
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`or inherently in a single prior art reference or system. I understand that inherency
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`requires a showing that the missing descriptive matter in the claim is necessarily or
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`implicitly present in the allegedly anticipating reference, and that it would have
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`been so recognized by a POSITA. In addition, I understand that an enabling
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`disclosure is a disclosure that allows a POSITA to make the invention without
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`undue experimentation. Although anticipation typically involves the analysis of a
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`single prior art reference, I understand that additional references may be used to
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`show that the primary reference has enabling disclosure, to explain the meaning of
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`a term used in the primary reference, and/or to show that a characteristic is inherent
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`in the primary reference.
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`33.
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`I understand that if the reference is a device or system, the public need
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`not have access to the inner workings of a device for it to be considered in public
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`use or used by others.
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`B. Obviousness
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`34.
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`I understand that a claim is unpatentable if the differences between the
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`claimed subject matter and the prior art are such that the subject matter as a whole
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`would have been obvious at the time the claimed subject matter was made to a
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`POSITA to which the subject matter pertains. I understand that a patent claim may
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`be obvious to a POSITA in view of the prior art teachings of a single reference or a
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`combination of references.
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`16
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`Inter Partes Review of U.S. Patent No. 8,487,659
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`35. To assess obviousness, I understand that I am to consider the scope
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`and content of the prior art, the differences between the prior art and the claim, the
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`level of ordinary skill in the art, and any secondary considerations to the extent
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`they exist.
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`36.
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`It is also my understanding that there are principles that may be used
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`as further guidance in obviousness analysis (especially when considering
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`combinations of references), which include considering whether:
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`• the claimed subject matter is simply a combination of prior art elements
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`according to known methods to yield predictable results;
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`• the claimed subject matter is a simple substitution of one known element
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`for another to obtain predictable results;
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`• the claimed subject matter uses known techniques to improve similar
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`devices or methods in the same way;
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`• the claimed subject matter applies a known technique to a known device
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`or method that is ready for improvement to yield predictable results;
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`• the claimed subject matter would have been (cid:147)obvious to try(cid:148) choosing
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`from a finite number of identified, predictable solutions, with a
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`reasonable expectation of success;
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`• there is known work in one field of endeavor that may prompt variations
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`of it for use in either the same field or a different one based on design
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`incentives or other market forces if the variations would have been
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`predictable to a POSITA;
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`• there existed at the time of conception and reduction to practice a known
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`problem for which there was an obvious solution encompassed by the
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`patent(cid:146)s claims; and
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`• there is some teaching, suggestion, or motivation in the prior art that
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`would have led a POSITA to modify the prior art reference or to combine
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`prior art reference teachings to arrive at the claimed subject matter.
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`37.
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`I understand that there are secondary considerations that may tend to
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`show that a claimed invention would not have been obvious to a POSITA. These
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`include, for example, commercial success, long-felt but unsolved needs, failure of
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`others, and unexpected results. I further understand that there must be a
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`relationship, or nexus, between any secondary considerations and the novelty of
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`the claimed invention.
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`VIII. PRIOR ART
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`38.
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`I understand that each of the references discussed herein qualifies as
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`prior art against the (cid:146)659 patent:
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`39. Masato Yoshioka, et al., A 10-b 50-MS/s 820-(cid:181)W SAR ADC With On-
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`Chip Digital Calibration, IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND
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`SYSTEMS, VOL. 4, NO. 6 (2010) ((cid:147)Yoshioka,(cid:148) Ex. 1004) is a paper published in the
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`journal (cid:147)IEEE Transactions on Biomedical Circuits and Systems.(cid:148) It was
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`published on November 24, 2010. I am informed that it is therefore prior art to the
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`(cid:146)659 patent under at least 35 U.S.C. § 102(a).
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`40. U.S. Patent No. 7,268,595 to Ajit ((cid:147)Ajit,(cid:148) Ex. 1005) was filed on
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`January 10, 2006, and issued on September 11, 2007. I am informed that Ajit is
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`therefore prior art to the (cid:146)659 patent under at least 35 U.S.C. § 102(b).
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`41. U.S. Patent No. 6,628,558 to Fiscus ((cid:147)Fiscus,(cid:148) Ex. 1006) was filed on
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`June 20, 2001, and issued on September 30, 2003. I am informed that Fiscus is
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`therefore prior art to the (cid:146)659 patent under at least 35 U.S.C. § 102(b).
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`A. The (cid:146)659 Patent and Yoshioka
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`42. As discussed above, the (cid:146)659 patent is directed to a delay element
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`within a comparator of a SAR ADC that (cid:147)dynamically adapt[s](cid:148) its delay in
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`response to process, voltage, and temperature ((cid:147)PVT(cid:148)) variations in the circuit
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`environment to counteract PVT effects on other components of the circuit system.
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`(See, e.g., Ex. 1001, 2:29-39.) A conventional comparator in a SAR ADC will
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`include a preamplifier and a latch. When a signal commands the preamplifier to
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`capture an input, it takes some time for the preamplifier to respond to the input. It
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`is important for the signal latching the preamplifier output be delayed in order to
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`
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`correctly capture the state of the preamplifier. A circuit is required to delay the
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`preamplifier start signal and the latch capture signal. A sufficient delay is
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`necessary for the comparator to operate properly. If the delay is too short, the
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`amplifier has less time to amplify the input for the result is latched. The
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`preamplifier response time as well as the delay in the delay circuit typically vary as
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`a function of process, temperature and supply voltage (PVT). The inventor, like a
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`POSITA at the time of claimed invention, recognized the need to counteract the
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`situation where, due to PVT variations, digital switching speeds increase. His
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`solution was to design the delay circuit to have an opposite effect (decrease in
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`speed).
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`43.
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`Just like the (cid:146)659 patent, Yoshioka is directed to a (cid:147)SAR analog-to-
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`digital converter (ADC).(cid:148) (Ex. 1004 at Abstract.) Also mirroring the adaptive
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`delay element in the (cid:146)659 patent, the disclosed delay element in Yoshioka
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`(cid:147)compensate[s] for PVT variations(cid:148