U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`UTILITY PATENT APPLICATION
`TRANSMITTAL LETTER UNDER
`37 C.F.R. 1.53(b)
`
`ATTORNEY DOCKET NO.:
`13641/430101
`
`Address to: Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Transmitted herewith for filing is the patent application of:
`
`Inventor(s): Ronald KAPUSTA (Bedford, Massachusetts, US)
`
`For:
`
`COMPARATOR WITH ADAPTIVE TIMING
`
`Enclosed are:
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`11 sheets of specification, 5 sheets of claims, 1 sheet of abstract, and 7 sheets of drawings.
`
`Declaration and Power of Attorney (signed).
`
`Application Data Sheet.
`
`Information Disclosure Statement.
`
`The filing fee calculated as shown below:
`
`FILING FEES
`
`BASIC FEE
`
`EXAMINATION FEE
`
`SEARCH FEE
`
`FEE($)
`
`CLAIMS FEES
`
`NUMBER FILED
`
`NUMBER EXTRA
`
`RATE($)
`
`FEE($)
`
`TOTAL BASIC, EXAM Ai"i"D SEARCH FEES
`
`TOTAL CLAIMS
`
`INDEPENDENT CLAIMS
`
`28-20 =
`
`5 - 3 =
`
`8x
`
`2x
`
`52.00
`
`220.00
`
`MULTIPLE DEPENDENT CLAIM PRESENT
`
`390.00
`TOTAL CLAIMS FEES
`D Additional fee for specification and drawings filed in paper over 100 sheets (excluding sequence listing or
`computer program listing filed in an electronic medium). The fee is $270 for each additional 50 sheets of paper or
`fraction thereof.
`Total Sheets
`
`330.00
`
`220.00
`
`540.00
`
`1,090.00
`
`416.00
`440.00
`
`0.00
`856.00
`
`1,946.00
`
`I
`I
`
`Extra Sheets
`0
`
`I
`I
`
`Number Extra
`0
`
`I
`I
`
`RATE
`X $270.00
`TOTAL FEES=
`
`If the applicant is a small entity under 37 C.F.R. §§ 1.9
`and 1.27, then divide total fee by 2, and enter amount here.
`
`SMALL E:t-...'TITY
`TOTAL
`
`- 1 -
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 1
`
`

`

`13641/430101
`
`The required application filing fee of $1,946.00 is being paid by credit card.
`
`The Commissioner is hereby authorized to charge payment of the following fees, associated
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`overpayment to deposit account number 11-0600:
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`A. Any additional filing fees required under 37 C.F.R. § 1.16;
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`
`D. Any additional post-patent processing fees under 37 C.F.R. § 1.20; or
`
`E. Any additional miscellaneous fees under 37 C.F.R. § 1.21.
`
`Respectfully submitted,
`
`Date: April 22, 2011
`
`By:
`
`/Martin E. Miller/
`. Martin E. Miller (Reg. No. 56,022)
`
`KENYON & KENYON LLP
`1500 K Street, N.W., Suite 700
`Washington D.C. 20005
`T: (202) 220-4200
`F: (202) 220-4201
`CUSTOMER NO. 79338
`
`- 2 -
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 2
`
`

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`PTO/SB/14 (11-08)
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`Application Data Sheet 37 CFR 1.76
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`Attorney Docket Number
`
`13641/430101
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`Application Number
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`Title of Invention
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`COMPARATOR WITH ADAPTIVE TIMING
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`The application data sheet is part of the provisional or nonprovisional application for which it is being submitted. The following form contains the
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`D Portions or all of the application associated with this Application Data Sheet may fall under a Secrecy Order pursuant to
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`r
`,DD 1can n orma 10n:
`t I f
`f
`A
`Aoolicant 1
`Applicant Authority (!)Inventor I QLegal Representative under 35 U.S.C. 117
`Prefix Given Name
`Middle Name
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`Family Name
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`KAPUSTA
`Ronald
`Residence Information (Select One) (!) US Residency 0 Non US Residency 0 Active US Military Service
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`81 Wilson Road
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`Application Type
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`Nonprovisional
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`Subject Matter
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`Utility
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`Suggested Class (if any)
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`Suggested Technology Center (if any)
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`Total Number of Drawing Sheets (if any)
`
`7
`
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`
`EFS Web 2.2.2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 3
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`PTO/SB/14 (11-08)
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`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid 0MB control number.
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`D C. 122(b) and certify that the invention disclosed in the attached application has not and will not be the subject of
`an application filed in another country, or under a multilateral international agreement, that requires publication at
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`PTO/SB/14 (11-08)
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`U.S. Patent and Trademark Office; U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it contains a valid 0MB control number.
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`Application Data Sheet 37 CFR 1.76
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`COMPARATOR WITH ADAPTIVE TIMING
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`I Analog Devices, Inc.
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`/Martin Miller/
`
`Date (YYYY-MM-DD) 2011-04-22
`
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`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 6
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`

`

`DECLARATION
`APD4301-1-US
`
`PATENT
`Docket No. 13641-430101
`
`DECLARATION FOR PATENT APPLICATION
`
`As a below named inventor, I hereby declare that:
`
`My residence, post office address and citizenship are as stated below next to my name.
`
`I believe l am the original, first and sole inventor (if only one name is listed below) or an original, first and joint
`inventor (if plural names are listed below) of the subject matter which is claimed and for which a patent is
`sought on the invention entitled:
`
`the specification of which is attached hereto unless the following is entered:
`
`COMPARATOR WITH ADAPTIVE TIMING
`
`was filed on
`
`as United States Application Number or
`PCT International Application Number
`
`and was amended on (if applicable)
`
`I hereby state that I have reviewed and understand the contents of the above-identified specification, including
`the claims, as amended by any amendment referred to above.
`
`I acknowledge the duty to disclose information which is material to patentability as defined in 37 CFR §1.56.
`
`PRIOR FOREIGN APPLICATION($)
`I hereby claim foreign priority benefits under 35 USC §119(a-d) or §365(b) of any foreign application(s) for
`patent or inventor's certificate, or §365(a) of any PCT International application which designated at least one
`country other than the United States, listed below and have also identified below any foreign application(s) for
`patent or inventor's certificate, or PCT International application having a filing date before that of the application
`on which priority is claimed:
`
`Application Number
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`Country
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`Filing Date
`(day/month/year)
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`Priority Not Claimed
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`PROVISIONAL APPLICATION($)
`I hereby claim the benefit under 35 USC §119{e) of any United States provisional application(s) listed below:
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`Application Number
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`Filing Date
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`PRIOR UNITED STATES APPLICATION($)
`I hereby claim the benefit under 35 USC §120 of any United States application(s), or §365(c) of any PCT
`International application designating the United States, listed below and, insofar as the subject matter of each of
`the claims of this application is not disclosed in the prior United States or PCT International application in the
`manner provided by the first paragraph of 35 USC §112, I acknowledge the duty to disclose information which
`is material to patentability as defined in 37 CFR §1.56 which became available between the filing date of the
`ptior application and the national or PCT International filing date of this application:
`
`Application Number
`
`Filing Date
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`Status (patented, pending,
`abandoned)
`
`NYOI 2139090 vi
`
`Page 1 of2
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 7
`
`

`

`DECLARA TlON
`APD430H-US
`
`PATENT
`Docket No. 13641-430101
`
`DECLARATION FOR PATENT APPLICATION
`
`I hereby appoint the following attomey{s) and/or agent(s) to prosecute this application and to transact all
`business in the Patent and Trademark Office connected therewith:
`
`POWER OF ATTORNEY
`
`CUSTOMER NUMBER 79,338
`
`with full power of substitution and revocation, to prosecute this application and to transact all business in the
`Patent and Trademark Office connected herewith.
`
`Direct telephone calls to:
`
`Send correspondence to:
`
`Robert L. Halls (Reg. No. 39,702)
`{202) 220-4200
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`The address designated for customer number 79,338
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`I hereby declare that all statements made herein of my own knowledge are true and all statements made on information and
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`that such willful statements may jeopardize the validity of the application or any patent issuing thereon.
`
`Full name of first
`or sole inventor
`
`-
`
`Residence
`
`.
`
`Post Office
`Address
`
`Last Name
`
`KAPUSTA
`
`City
`
`Bedford
`
`Street
`
`---~
`
`First Name
`
`Middle Name
`
`Ronald
`
`State or Country
`
`Massachusetts
`
`.. -
`
`---
`Country of Citizenship
`us
`
`Crty, State
`
`Country & Zip Code
`
`81 Wilson Road
`
`Bedford, MA
`
`01730 USA
`
`Signature
`
`·kJJA i~ki
`
`,
`
`I
`
`Date
`
`tf /21/u
`
`NYOl 213409{) vi
`
`Page 2 of2
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 8
`
`

`

`DECLARATION
`APD4301-1-US
`
`PATENT
`Docket No. 13641-430101
`
`Title 37, Code of Federal Regulations, Section 1.56
`Duty to Disclose Information Material to Patentability
`
`(a)
`A patent by its very nature is affected with a public interest. The public interest is best served,
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`
`( 1)
`
`Prior art cited in search reports of a foreign patent office in a counterpart appHcation,
`
`and
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`The closest information over which individuals associated with the filing or prosecution
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`of a patent application believe any pending claim patentably defines, to make sure that any material
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`Under this section, information is material to patentability when it is not cumulative to
`(b)
`information already of record or being made of record in the application, and
`
`It establishes, by itself or in combination with other information, a prima facie case of
`(1)
`unpatentability of a claim; or
`
`(2}
`
`It reMes, or is inconsistent with, a position the applicant takes in:
`
`(i)
`
`(ii)
`
`Opposing an argument of unpatentability relied on by the Office, or
`
`Asserting an argument of patentability,
`
`A prima facie case of unpatentability is established when the information compels a conclusion that a claim is
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`broadest reasonable construction consistent with the specification, and before any consideration is given to
`evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.
`
`{c)
`this section are:
`
`Individuals associated with the filing or prosecution of a patent applfcation within the meaning of
`
`(1)
`
`(2)
`
`Each inventor named in the application;
`
`Each attorney or agent who prepares or prosecutes the application; and
`
`Every other person who is substantively involved in the preparation or prosecution of
`(3)
`the application and who is associated with the inventor, with the assignee or with anyone to whom there
`is an obligation to assign the application.
`
`Individuals other than the attorney, agent or inventor may comply with this section by disclosing
`(d)
`information to the attorney, agent, or inventor.
`
`In any continuation-in-part application, the duty under this section includes the duty to disclose
`(e)
`to the Office all information known to the person to be material to patentability, as defined in paragraph (b) of
`this section, which became available between the filing date of the prior application and the national or PCT
`international filing date of the continuation-in-part application.
`
`NYOI 2139090 vl
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1003 Page 9
`
`

`

`13641/430101
`
`COMPARATOR WITH ADAPTIVE TIMING
`Inventor:
`Ron Kapusta
`
`FIELD OF INVENTION
`
`[01]
`
`The present invention relates to signal processors, and more particularly to a
`
`device for tracking operation of adjacent circuitry in response to process, voltage and
`
`temperature (PVT) variations experienced by the adjacent circuitry.
`
`BACKGROUND
`
`[02]
`
`Successive approximation register (SAR) analog-to-digital converters (ADC)
`
`perform analog to digital conversions. The SAR ADC includes a number of different
`
`components including comparators.
`
`[03]
`
`FIG. 1 illustrates a conventional comparator configuration within a SAR ADC. A
`
`conventional SAR ADC 100 includes an analog input, a sample and hold amplifier 105, a
`
`digital-to-analog converter (DAC) 110, a comparator 120, and
`
`logic 130.
`
`The
`
`comparator 120 includes a pre-amplifier 123, a delay device 125 and latch 127. The
`
`pre-amplifier 123 amplifies the input signals and outputs the amplified input signal to the
`
`latch, improving the input referred noise and linearity of the comparator.
`
`In order to
`
`allow the preamplifier 123 time to amplify the input signal, a control signal RESET is
`
`delayed before going to the latch, so that the latch is held in a known reset state while
`
`the preamplifier is amplifying. Once the delayed reset signal is released, the latch will
`
`regenerate and the comparator makes it decision. The delay of the delay device 125 is
`
`fixed by inserting an inverter or series of inverters in the circuit path. A delayed output
`
`signal DEL_RESET from the delay device 125 is provided to the latch 127. FIG. 2
`
`illustrates an exemplary timing diagram of a conventional comparator, such as
`
`comparator 120.
`
`[04]
`
`Typically, as shown, by the preamplifier output 230, the preamplifier 123
`
`operates for some period of time (tl to t2) before the latch 127 is released. The
`
`maximum speed of a SAR ADC 100 is dependent upon the operating speed of the digital
`
`logic and switches such as those that form the comparator 120. The operating speed of
`
`the digital logic and switches, e.g., inverters and latches, vary in response to various
`
`circuit conditions such as variations in the supply voltage, variations in temperature, or
`
`fabrication process variations across different manufacturing lots of integrated chips.
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`Examples of fabrication process parameters may be device characteristics, such as
`
`threshold voltage and oxide thickness.
`
`[05]
`
`When the delay through the delay elements 125 becomes shorter because of the
`
`faster operating conditions, such as rises
`
`in circuit temperature, supply voltage
`
`increases, process effects, or other conditions, the signal DEL_RESET 220 may be output
`
`sooner. Consequently, the preamplifier 123 has less time to amplify before the latch 127
`
`is released, as shown by 240. However, the increased comparator 120 operating speed
`
`due to the change in parameters is generally lost because the sample rate of the ADC is
`
`typically held constant.
`
`In other words, the preamplifier 123 and latch 127 within the
`
`comparator 120 may finish operating sooner on a given input, but ultimate output of the
`
`latch signal still has to wait until the end of the sampling period because the ADC is still
`
`clocked at the sampling rate, which remains unchanged.
`
`[06]
`
`The inventor has recognized the benefit of a device that operates opposite to the
`
`effects of PVT variations. An exemplary implementation of an application of the device
`
`is for a comparator in a SAR ADC that adaptively adjusts its timing to take advantage of
`
`changes in conditions and circuit parameters to provide better performance.
`
`For
`
`example, it would be beneficial if, as the digital logic and switching speeds increase, the
`
`delay between amplifying the input signal and releasing the latch adaptively changed to
`
`allow the preamplifier or latch more time to operate on the input signal to fill the
`
`sampling period. This provides the advantage of better signal-to-noise ratios and/or
`
`lower power.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`[07]
`
`[08]
`
`FIG. 1.
`
`FIG. 1 illustrates a conventional comparator configuration within a SAR ADC.
`
`FIG. 2 illustrates an exemplary timing diagram of the conventional comparator of
`
`[09]
`
`FIG. 3 illustrates an exemplary implementation of a comparator with an adaptive
`
`delay according to an embodiment of the present invention.
`
`[10]
`
`FIG. 4 illustrates an exemplary configuration of an adaptive delay device
`according to an embodiment of the present invention.
`
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`13641/430101
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`[11]
`
`FIG. 5 illustrates an exemplary timing chart of an adaptive delay according to an
`
`embodiment of the present invention.
`
`[12]
`
`FIG. 6 illustrates an exemplary timing diagram of the operation of an adaptive
`
`delay device according to an embodiment of the present invention.
`
`[13]
`
`FIG. 7 illustrates an analog-to-digital converter according to an embodiment of
`
`the present invention.
`
`DETAILED DESCRIPTION
`
`[14]
`
`Embodiments of the present invention may provide a delay device that may
`
`dynamically adapt its delay based on PVT variations in the circuit environment in a
`
`manner that counteracts traditional PVT effects. Thus, if PVT effects ordinarily cause
`
`other transistors within a circuit to switch at a faster rate (for example, driving voltages
`
`increase or temperature decreases), the delay device increases its delay to operate at a
`
`slower rate. The delay device may be used as a control element to gate operations of
`
`other components within a circuit system, which can stabilize the system's throughput
`
`even when large PVT variations occur.
`
`[15]
`
`In another embodiment, the delay element may include an inverter, a capacitor
`
`and an output transistor. The inverter may invert a control signal that is input to the
`
`delay element. The capacitor may be coupled to the inverter's output and may begin
`
`charging when the inverter's output transitions to a high voltage level. The output
`
`transistor may have a gate coupled to the capacitor and its source coupled to a high
`
`supply voltage. The output transistor may pull an output of the delay element high
`
`when the gate voltage is lower than the high supply voltage (e.g., VDD) by an amount
`
`that exceeds the threshold voltage (e.g., Vth). When the capacitor charges to an
`
`amount (e.g., VC) that is within the threshold (IVDD-VC]l<Vth), the output transistor
`
`may cease to conduct and the output voltage may drop to ground.
`
`[16]
`
`In another embodiment, a comparator may include an adaptive delay device. A
`
`comparator may include an input for an input signal, a control signal input, an output, a
`
`preamplifier, an adaptive delay device and a latch, both the preamplifier and the latch
`may be responsive to a control signal. The control signal may allow the preamplifier to
`
`amplify the input signal, and provide it to the latch. The adaptive delay device may
`
`respond to circuit conditions in the comparator, and in response, may adaptively delay
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`13641/430101
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`the control signal applied to the preamplifier from being applied to the latch. After the
`
`delay time period, the control signal may be output to the latch. The latch may resolve
`
`the amplified input signal upon receipt of the delayed control signal, and output a digital
`
`representation of the input signal.
`
`[17]
`
`FIG. 3
`
`illustrates a comparator with an adaptive delay according
`
`to an
`
`embodiment of the present invention. The exemplary comparator 300 may include a
`
`preamplifier 310, a latch 320 and an adaptive delay element 330, all of which may be
`
`fabricated in a common integrated circuit, and may operate from a common supply
`
`voltage, e.g., VDD (not shown). Thus, PVT conditions should apply to all circuit
`
`elements within the comparator 300 nearly identically.
`
`[18]
`
`The preamplifier 310 may have inputs for an input signal (IN) and a control
`
`signal (RESET) and an output for outputting an amplified representation of the input
`
`signal. The latch 320 may have an input coupled to an output of the preamplifier and an
`
`input for receiving a delayed control signal (RESET _DEL) from the adaptive delay
`
`element 330 and an output for outputting a voltage (OUT) representative of the digital
`
`value of the input signal IN.
`
`[19]
`
`The adaptive delay element 330 may have an input for receiving the control
`
`signal RESET, and an output for outputting the delayed control signal RESET _DEL. The
`
`adaptive delay element 330 may have a circuit structure that inverts effects of PVT that
`
`may occur in the preamplifier 310 and the latch 320. Thus, if switches of the
`
`preamplifier 310, latch 320 and delay element 330 may operate faster in response to
`
`decreased temperature and/or increased supply voltage VDD), the circuit structure of
`
`the adaptive delay element 330 may add delay to its operations in a manner that
`
`cou