Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 1
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`EXHIBIT A
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 3
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`Journals & Magazines > IEEE Transactions on Biomedic... > Volume: 4 Issue: 6
`
`A 10-b 50-MS/s 820- W SAR ADC With On-Chip Digital
`Calibration
`Publisher: IEEE
`
`Cite This
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`
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`Cite This
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` PDF
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`4 Author(s) Masato Yoshioka ; Kiyoshi Ishikawa ; Takeshi Takayama ; Sanroku Tsukamoto All Authors
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`67
`Paper
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`Abstract
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`Document Sections
`
`Downl
`PDF
`
`I.
`
`Introduction
`
`II. Circuit Design
`
`III. Digital Calibration
`
`IV. Experimental
`Results
`
`V. Conclusion
`
`Authors
`
`Figures
`
`References
`
`Citations
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`Keywords
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`Metrics
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`Abstract: This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-
`chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-
`anal... View more
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`Abstract:
`This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital
`calibration techniques, comparator offset cancellation, a capacitor digital-to-analog
`converter (CDAC) linearity calibration, and internal clock control to compensate for PVT
`variations. A split-CDAC reduces the exponential increase in the number of unit
`capacitors needed and enables the input load capacitance to be as small as the kT/C
`noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide
`semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz
`input frequency and consumes 820 μW from a 1.0-V supply, including the digital
`calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist
`condition. The ADC occupied an active area of 0.039 mm .2
`
`Published in: IEEE Transactions on Biomedical Circuits and Systems ( Volume: 4 ,
`Issue: 6 , Dec. 2010 )
`
` Export to
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`Collabratec
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 4
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`μ
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`More Like This
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`Page(s): 410 - 416
`
`INSPEC Accession Number: 11661372
`
`Date of Publication: 09 November 2010
`
`DOI: 10.1109/TBCAS.2010.2081362
`
`Publisher: IEEE
`
` Contents
`
` ISSN Information:
`
`SECTION I.
`Introduction
`
`A System-On-Chip (SoC) for ultrasound systems and sensors needs two
`or more analog-to-digital converters (ADCs) for multichannel inputs.
`Power and area reductions are very important since they enable more
`channels to be implemented in one chip. Reduction of the number of
`chips results in a miniaturization of the system. Technology scaling
`improves the digital performance of SoC, enabling large-scale on-chip
`integration and high-speed operation with superior energy efficiency. On
`the other hand, the poor performance of the metal–oxide semiconductor
`field-effect transistors (MOSFETs) in the saturation region makes it
`difficult to design a high gain amplifier, and the lower power-supply
`voltage intensifies floating switch and thermal noise problems. As a
`result, it is steadily becoming more difficult to design pipelined ADCs
`because the ADC's performance depends on the amplifier's performance.
`In addition, at a lower supply voltage, the analog signal suffers from the
`increased resistance of the analog switches. Successive approximation
`register (SAR) ADCs are more compatible with technology scaling
`because they do not need operational amplifiers and have fewer floating
`switches. The only analog part is the comparator, whose design is close
`to that of a digital regenerative latch. This means that no static current
`flows if charge leakage from the capacitor digital-to-analog converter
`(CDAC) can be avoided; hence, the power consumption will be a linear
`function of the conversion rate. In fact, a low-power pipelined ADC that
`does not require amplifiers has been developed [1]. However, the
`pipeline architecture has more circuits than the SAR architecture.
`Hence, an SAR architecture would still be a better choice for low-power
`and compact ADCs.
`
`Designing the ADC using small devices takes advantage of the scaling
`merits. Higher conversion rate and smaller area are direct benefits.
`Smaller area in turn contributes to reducing the power consumption,
`because the smaller parasitics reduce the required drive power.
`However, accuracy suffers from device mismatch. Many digitally
`assisted techniques have been reported in an attempt to resolve this
`issue. Foreground calibration was reported [2] as a way to align the
`mismatch of the capacitors, but the actual calibration was done via off-
`chip software processing. A nonbinary CDAC design based on unit
`capacitors [3] has redundancy for correcting the misjudgments of the
`comparator and/or incomplete CDAC settling. However, the linearity is
`still affected by capacitor mismatch. Nonbinary designs using
`-
`CDACs are reported in [4]. Redundancy works because the upper bit
`decision can have a larger redundancy. However, this structure needs
`additional stages as well as digital postprocessing. Another nonbinary
`design
` 1.86 was implemented with individually arranged
`capacitors which can maintain linearity by using the perturbation
`technique [5]. This technique can correct the mismatch of the radix
`between each bit. However, it also needs additional stages and digital
`postprocessing.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 5
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`C 2C
`Radix =
`

`

`This paper presents on-chip digital calibration techniques to correct the
`CDAC mismatches based on [2] and an internal clock control that
`enables a very slow conversion rate while avoiding the charge leakage
`problem of the CDAC. Section II describes the design and architecture of
`the proposed SAR ADC. Section III presents the calibration techniques
`and Section IV shows the experimental results. Conclusions are given in
`Section V.
`
`SECTION II.
`Circuit Design
`
`A. ADC Architecture
`Fig. 1 shows the block diagram of the SAR ADC. The actual design is
`differential, but the figure shows a single-ended design for simplicity. It
`consists of a 10-b split-CDAC, a comparator, an internal clock generator,
`SAR controller, and a digital calibration circuit. The split-CDAC can
`reduce the number of unit capacitors relative to a conventional binary
`weighted CDAC design; however, it is very sensitive to mismatch as well
`as to parasitic capacitance. This causes a linearity error as a result. A
`variable capacitor
` is used to compensate for the mismatches of the
`splitting capacitor
`. The capacitance of
` is adjusted prior to the
`conversion. The calibration CDAC corrects the mismatches of the upper
`three bits by operating in parallel with the main CDAC. The comparator
`offset is cancelled in order to correctly detect the mismatches of the
`CDAC.
`
`Fig. 1.
`ADC architecture.
`
` period
`The SAR ADC samples the analog signal during the
`and completes ten comparisons for 10-b conversion on the basis of an
`internal clock
`, which is generated by a loop consisting of the same
`comparator used with the CDAC and delay elements. This loop is
`dependent on the PVT conditions, so its frequency is controlled during
`the conversion. Section III describes the CDAC linearity calibration and
`internal clock generation.
`
`B. Cdac
`
`The CDAC is a split capacitor array designed with the upper 4 b (
`), middle 4 b (
`) and lower 2 b (
`) arrays as
`shown in Fig. 2.
` is used to reduce the input load capacitance. Its
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 6
`
`C
`V
`C
`B1
`C
`V
`CLK =" H "
`Φ
`c
`∼C
`9
`C
`6
`∼C
`5
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`2
`∼C
`1
`C
`0
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`X
`

`

`capacitance corresponds to the equivalent capacitance of the L-side. The
`analog signal is sampled by
`; as a result, the capacitors on the L-side
`do not need to sample the analog signal.
` and
` attenuate the
`power-supply VDD to generate an adequate full-scale range of ADC.
`They are connected to the analog signal during the sample phase and are
`respectively switched to ground and VDD during the conversion phase.
`The common mode level is designed to be at
`, so
` and
`have the same capacitance value. The capacitance is designed to be
`where the unit
` is designed to be 17 fF, so that the full-scale range is
`around VDD [peak-to-peak differential].
`
`,
`
`Fig. 2.
`The 10-b split-CDAC.
`
`The total amount of input load capacitance is 30 C. This means that the
`input load capacitance is 510 fF, which is large enough to meet the
`noise requirement for covering process variations. Mismatches of the
`CDAC are compensated by
` and the calibration CDAC. The total
`number of unit capacitors is 300 for both differential sides, which is
`approximately 1/7th the amount of a full straight binary weighted CDAC.
`
`The switches in the CDAC are connected to either VDD or ground, so no
`complementary switch is needed. They are designed by using either
`NMOS or PMOS to save the area and power. Bootstrapped switches
`based on [6] are used for analog signal sampling to suppress distortion.
`
`C. Comparator and Internal Clock Generator
`Fig. 3 shows the internal clock generator, which includes a comparator
`in its loop. A strong arm latch type comparator without a preamplifier
`(Fig. 5) is used. It does not consume static current. Both of the
`comparator outputs,
` and
`, become “H” during the sample
`phase. During the conversion phase, one of them goes to “L”, which
`enables the end of the comparison to be detected from the output signal
` of the and gate. We carefully designed the threshold of the and in
`order to avoid incorrect detections resulting from the transient response
`of the comparator.
` is generated by adding an adequate delay
` to
`. Finally,
` goes to “H” and the comparator resets after completing
`one loop. This loop is repeated ten times during the conversion phase.
`The frequency of
` depends on the comparator response delay and
` is automatically controlled by
` to be approximately 700 MHz in
`order to make ten comparisons in 15 ns. Five nanoseconds is the period
`given for the analog signal sampling at 50 MSamples/s.
`
`.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 7
`
`C
`X
`C
`H
`C
`L
`VDD/2
`C
`H
`C
`L
`7C
`C
`kT/C
`C
`V
`V
`QP
`V
`QM
`V
`A
`V
`B
`T
`d
`V
`A
`Φ
`c
`Φ
`c
`T
`d
`T
`d
`Φ
`c
`

`

`Fig. 3.
`Internal clock generator.
`
`Fig. 4.
`Calibration scheme and status of each circuit.
`
`Fig. 5.
`Comparator with offset cancellation.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 8
`
`

`

`Fig. 6.
` calibration. (a) Sample phase. (b) Conversion phase.
`
`SECTION III.
`Digital Calibration
`
`A. Comparator Offset Cancellation
`
`Fig. 4 shows the calibration scheme and status of each circuit after the
`ADC is powered on. The principle of the CDAC linearity calibration is to
`correct its nonlinearity by comparing the capacitance mismatches
`between the upper bit capacitor and the rest of the lower bit capacitors
`including the dummy. Therefore, as shown in Fig. 4, the comparator
`offset should be canceled prior to the CDAC linearity calibration;
`otherwise, it will result in a mismatch in the CDAC, causing a linearity
`error. Various comparator offset cancellation techniques have been
`published [7]–[8][9]. A dynamic offset control technique adjusts the
`output load capacitance controlling the offset; this, however, degrades
`the response [7]. Another dynamic offset cancel technique [8] controls
`the clock skew, which results in less of a response penalty; however, the
`timing control is sensitive to PVT variations. The threshold control
`technique shown in Fig. 5 can be used to cancel the comparator offset
`[9]. The threshold of either of the differential pair
` or
` is
`controlled by foreword body biasing. As a result, the difference between
` and
` is minimized. for instance, if
`,
` is raised to
`increase
`. This technique does not have a response penalty and does
`not require sensitive timing control.
`
`The offset cancellation is done by feeding the same analog input signal to
`the comparator by connecting
` and
` to the common level
`.
` and
` are initially connected to ground (0 V). Several
`comparisons are made to avoid thermal noise effects inherent in the
`comparator. The final result, “L” or “H,” is determined by the majority
`value and is stored in the register. If the result is the same as the
`previous one, either
` or
` is raised accordingly to reduce the
`offset voltage. This routine is continued until the result reverses. The
`comparator offset cancellation then finishes by fixing
` and
`.
`
`The body biasing is controlled by a resister DAC. This DAC consists of
`256 taps and a polarity selector, amounting to a total of 512 steps. The
`minimum step and dynamic range are designed to cover the offset
`distribution with an error smaller than 0.25 LSB at the ADC output. The
`resistor DAC dissipates 20 A.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 9
`
`C
`B1
`M
`IP
`M
`IM
`I
`P
`I
`M
`>I
`P
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`BP
`V
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`V
`BP
`V
`BM
`μ
`

`

`B. CDAC Linearity Calibration
`
`The CDAC linearity error caused by parasitics and process mismatch is
`calibrated after the comparator offset cancellation is completed. The
`mismatch as well as the parasitic effects of the split capacitor
` is
`calibrated by a variable capacitor
`, and the mismatch of the upper
`three bits are corrected by the calibration CDAC.
` could be calibrated
`by using the calibration CDAC; however, the CDAC would then need a
`larger dynamic range, resulting in a larger area. Using
`, however,
`obviates the need for a large dynamic range, so it is simpler than using
`the calibration CDAC.
` between the nodes
` and
` is not
`calibrated because its error is negligible.
`
`) calibration
` is calibrated first because the upper three-bit (
` calibration is
`uses the lower bit capacitors. The principle of the
`shown in Fig. 6 [8]. In the ideal case with no parasitics,
` should be 16
`C/15; in practice, however, its value is set to be
` (
`). The
`calibration CDAC's state is fixed during the calibration period of
`. In
`the first step of the calibration,
` is given a minimum capacitance. In
`the sample phase, all of the capacitors on the L-side are connected to
`ground (“L”) and all capacitors on the H-side are connected to VDD
`(“H”), biasing the comparator input node
` to the
` [Fig. 6(a)].
`Next, in the conversion phase,
` is disconnected from
` and all of
`the L-side capacitors are switched to VDD (“H”), and
` is switched to
`ground (“L”) [Fig. 6(b)]. Mismatches between all of the L-side capacitors
`and
` appear on
` and are judged by the comparator. If
` is
`smaller than the value needed to compensate for the mismatch of
`the equivalent capacitance on the L-side will be larger than
`. The
`result is a higher voltage on
` and the comparator judges the result as
`a “H.” The result is fed to the digital calibration circuit, and a larger
`capacitance is chosen for
`. This routine is repeated until the
`comparator's result becomes “L.” The comparator's result is also based
`on selecting the majority decision; the same method is used for the
`comparator offset cancellation. The step of
` is designed to be smaller
`than 0.25 LSB.
`
`,
`
`. The calibration CDAC has the
` are calibrated after
`, and
`,
`same structure as the switched capacitor DAC architecture in order to
`operate with
`,
` and
`. The calibration CDAC is connected to node
`, not
` [10]; therefore, it influences the main CDAC as a parasitic.
`However, it is compensated during the
` calibration. Fig. 7 shows the
`principle of the
` calibration, which is similar to that of
`. In the
`sample phase,
` is connected to VDD (“H”) and the rest of the
`capacitors,
` to
`, dummy capacitor
` and
` are connected to
`ground (“L”), biasing the
` to
`, and
` and
` to ground,
`respectively [Fig. 7(a)]. Next, in the conversion phase,
`,
`, and
`are disconnected.
` is switched to ground (“L”), and
` to
` including
` are switched to VDD (“H”).
` remains connected to ground (“L”)
`[Fig. 7(b)]. If there is no mismatch between
` and the rest of the
`capacitors,
` to
` and
`,
` stays at
`. In the other words, the
`mismatch causes some change in
`. The change is detected by the
`comparator on the basis of the majority decision and is fed back to the
`calibration CDAC to cancel it. This is repeated as in the
` calibration,
` and
` are also calibrated in the same way [2]. The calibration CDAC
`control codes are stored and used during the actual conversion.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 10
`
`C
`B1
`C
`V
`C
`B1
`C
`V
`C
`B2
`N
`B
`N
`C
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`∼C
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`B1
`C
`B1
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`C
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`N
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`A
`V
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`C
`6
`C
`6
`N
`A
`C
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`C
`6
`N
`A
`C
`V
`C
`V
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`C
`8
`C
`7
`C
`B1
`C
`9
`C
`8
`C
`7
`N
`B
`N
`A
`C
`B1
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`C
`B1
`C
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`C
`8
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`C
`X
`N
`A
`V
`CM
`N
`B
`N
`C
`N
`A
`N
`B
`N
`C
`C
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`0
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`D
`C
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`

`

`Fig. 7.
` calibration. (a) Sample phase. (b) Conversion phase.
`
`Fig. 8.
` control implementation.
`
`Fig. 9.
`Delay controller.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 11
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`C
`9
`T
`d
`

`

`Fig. 10.
`Die photograph.
`
`C. Internal Clock Control
`
` is generated by a loop, which includes the
`The internal clock
`comparator and a delay controller (Fig. 3). The cycle period is
` is spent
`. Thirty percent of the
` period
`for comparison. The remaining 70%
` is spent for the CDAC response
`and SAR controller. It is useful to synchronize
` with the CDAC and
`SAR controller. However, prior ADCs use a fixed
` and provide no
`means to control it [4].
` has a large PVT variation, so it becomes hard
`to synchronize it with the CDAC and SAR controller. If
` becomes
`shorter than the CDAC and SAR controller delay, an incomplete settling
`will degrade the accuracy. An excessively long
` limits the number of
`available comparison cycles. The
` controller implemented for this
`ADC is shown in Fig. 8. It delivers the longest
` within the comparison
`period given by the external clock. The
` controller works in the
`background, as shown in Fig. 4, because the voltage and temperature
`conditions are not constant during operation.
`
` during the
` cycles
`The algorithm is based on counting the
` equal
`conversion phase;
` is calibrated to make the number of cycles
`to 10. In practice, a delayed
` signal (
`) is actually used to provide a
`wide enough margin, and this results in an improvement in the clock
`jitter tolerance. The transition point of the comparator as it starts to
`reset is used for the trigger edge to count the
` cycles. If
` (
`),
` is made longer (shorter) by using the ADJ code. In this
` converges to provide the longest comparison period.
` stays at
`way,
`“L” during the sampling phase and starts to work after a delay of
`after the falling edge of CLK. The delay
` is designed to meet the
`CDAC settling time requirement for MSB decision, and it is generated by
`a fixed delay circuit.
`
`Fig. 9 shows the delay controller. A 4-b coarse delay control is achieved
`by a series of inverter delay selectors. Fine delay control is afforded by a
`3-b-controlled MOS variable capacitor.
` is chosen so that all PVT
`conditions can be covered; the coverage in typical condition is between
`240 ps and 720 ps. This corresponds to 0.5 to 1.5 GHz. The longest delay
`also helps very slow conversions, because it can help to avoid charge
`leakage in the CDAC. The delay controller is composed of digital circuits
`that are smaller in area and consume less power than a phase locked
`loop (PLL).
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 12
`
`Φ
`c
`+
`+ 2
`T
`C1
`T
`C2
`T
`d
`Φ
`c
`+T
`C1
`T
`C2
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`d
`T
`d
`T
`d
`T
`d
`T
`d
`T
`d
`T
`d
`T
`d
`T
`d
`Φ
`c
`N
`T
`d
`N
`Φ
`c
`Φ
`cd
`Φ
`c
`N > 10
`N < 10
`T
`d
`T
`d
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`c
`T
`MSB
`T
`MSB
`Td
`

`

`SECTION IV.
`Experimental Results
`
`The prototype ADC was fabricated in a one-polysilicon seven-metal 65-
`nm CMOS process with MIM capacitors. A microphotograph is shown in
`2
`Fig. 10. The ADC active area was 0.039 mm . All digital calibration
`2
`circuits were implemented on a chip measuring 0.013 mm , which is
`33% of the ADC area. If the CDAC linearity calibration were not
`implemented, CDAC would have to be designed using a six upper bits +
`four lower bits split CDAC design with 20-fF capacitors. The CDAC area
`will be twice as large as the current design, but it will not need a
`calibration scheme. So the difference is small from the viewpoint of area.
`However, the CDAC linearity calibration has the advantage of tolerance
`to process variations and input load.
`
`Figs. 11 and 12 shows the effects of the calibration in the code density
`test. Before calibration, the peak DNL and INL were 1.4 LSB and 3.9
`LSB, respectively; these values were mostly caused by the mismatch of
`the split capacitor
`. After calibration, peak DNL and INL were
`improved to 0.82 LSB and 0.72 LSB, respectively.
`
`Fig. 13 illustrates the results of the dynamic performance measurement
`at 50 MSamples/s and a 1.0-V power supply. SNDR was 56.9 dB (
` 9.16) and the spurious-free dynamic range (SFDR) was 75.2
`dB at a 2-MHz input frequency, whereas the SNDR was 56.6 dB (
` 9.10) and the SFDR was 76.9 dB under the Nyquist condition.
`The effective resolution bandwidth was 150 MHz.
`
`Fig. 11.
`Measured DNL and INL before calibration.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 13
`
`C
`B1
`ENOB =
`ENOB =
`

`

`Fig. 12.
`Measured DNL and INL after calibration.
`
`Fig. 13.
`Measured SNDR and SFDR versus the input frequency at 50 MSamples/s.
`
`Fig. 14 shows the spectrum at the 2-MHz input. The SFDR was 75.2 dB
`and SNDR was 56.9 dB, which corresponds to an ENOB of 9.16. Fig. 15
`plots the measured SNDR versus the conversion rate with and without
`the internal clock control. Without the internal clock control, the delay
` was fixed at 30 MSamples/s and conversion speed increases. Lower
`bit comparison could not be completed due to the lack of comparison
`cycles. The internal clock control could track the conversion speed. The
`degradation at more than 70 MSamples/s was caused by incomplete
`settling of the CDAC. Fig. 16 shows the power-supply dependency with
`and without the internal clock control. Without the internal clock
`control, the ADJ code was fixed at a 1.3-V supply and the VDD was
`swept. As the supply fell,
` became longer for the same ADJ code. This
`means that the lower bit comparison could not be achieved within the
`conversion phase. The internal clock control adjusted suitable
` to the
`variation in the supply voltage. Fig. 17 shows the temperature
`dependency of SNDR and SFDR when the CDAC linearity calibration
`was performed at 25°C. The SNDR variation between −30°C to 120°C
`was less than 1 dB. Table I summarizes the performance of the ADC.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 14
`
`T
`d
`T
`d
`T
`d
`

`

`Fig. 14.
`Measured ADC output spectrum at 2-MHz input.
`
`Fig. 15.
`Measured SNDR versus conversion rate at the 2-MHz input with and without
`internal clock control.
`
`Fig. 16.
`Measured SNDR versus supply voltage at 50 MSamples/s and 2-MHz input with
`and without internal clock control.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 15
`
`

`

`Fig. 17.
`Measured SNDR and SFDR versus temperature at 50 MSamples/s and 2-MHz
`input.
`
`Table I ADC Performance Summary
`
`SECTION V.
`Conclusion
`
`The SAR ADC with a split-CDAC and internal clock generator uses two
`calibration techniques to ensure stable operation. Digital calibration
`improves CDAC linearity, which is affected by parasitics and
`mismatching of the capacitors. The internal clock is controlled in the
`background to compensate for PVT variations. The calibration scheme is
`implemented on-chip, so no off-chip software processing is needed. The
`10-b SAR ADC can perform 50 MSamples/s with a 1.0-V power supply.
`Power consumption is 820 W, including the power of the CDAC
`operation. This means that the ADC needs no additional power for
`providing the reference voltages. The active area, including the digital
`2
`calibration circuits, is 0.039 mm .
`
`, is 29.7 fJ/conv-step.
`The FoM, defined as
`Table II compares state-of-the-art ADCs. If the power and area of the
`ADCs are especially small, more ADCs can be implemented in one chip.
`This makes it possible to build more compact portable medical
`equipment, such as ultrasound scanners.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 16
`
`μ
`FoM = P/(
`∗ 2BW)
`2
`ENOB
`

`

`Table II Comparison of State-of-the-Art ADCs
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1004 Page 17
`
`

`

`410
`
`IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 6, DECEMBER 2010
`
`A 10-b 50-MS/s 820-W SAR ADC
`With On-Chip Digital Calibration
`
`Masato Yoshioka, Kiyoshi Ishikawa, Takeshi Takayama, and Sanroku Tsukamoto, Member, IEEE
`
`Abstract—This 10-b 50-MSamples/s SAR analog-to-digital con-
`verter (ADC) features on-chip digital calibration techniques, com-
`parator offset cancellation, a capacitor digital-to-analog converter
`(CDAC) linearity calibration, and internal clock control to com-
`pensate for PVT variations. A split-CDAC reduces the exponen-
`tial increase in the number of unit capacitors needed and enables
`the input load capacitance to be as small as the kT C noise re-
`striction. The prototype fabricated in 65 nm 1P7M complementary
`metal–oxide semiconductor with MIM capacitor achieves 56.6 dB
`SNDR at 50-MSamples/s, 25-MHz input frequency and consumes
`820 W from a 1.0-V supply, including the digital calibration cir-
`cuits. The figure of merit was 29.7 fJ/conversion-step under the
`Nyquist condition. The ADC occupied an active area of 0.039 mm2.
`Index Terms—Analog-to-digital converter (ADC), digital cali-
`bration, successive approximation register.
`
`I. INTRODUCTION
`
`A SYSTEM-ON-CHIP (SoC) for ultrasound systems and
`
`sensors needs two or more analog-to-digital converters
`(ADCs) for multichannel inputs. Power and area reductions
`are very important since they enable more channels to be
`implemented in one chip. Reduction of the number of chips
`results in a miniaturization of the system. Technology scaling
`improves the digital performance of SoC, enabling large-scale
`on-chip integration and high-speed operation with superior
`energy efficiency. On the other hand, the poor performance of
`the metal–oxide semiconductor field-effect transistors (MOS-
`FETs) in the saturation region makes it difficult to design a high
`gain amplifier, and the lower power-supply voltage intensifies
`floating switch and thermal noise problems. As a result, it is
`steadily becoming more difficult to design pipelined ADCs
`because the ADC’s performance depends on the amplifier’s
`performance. In addition, at a lower supply voltage, the analog
`signal suffers from the increased resistance of the analog
`switches. Successive approximation register (SAR) ADCs
`are more compatible with technology scaling because they
`do not need operational amplifiers and have fewer floating
`switches. The only analog part is the comparator, whose design
`is close to that of a digital regenerative latch. This means that
`
`no static current flows if charge leakage from the capacitor
`digital-to-analog converter (CDAC) can be avoided; hence, the
`power consumption will be a linear function of the conversion
`rate. In fact, a low-power pipelined ADC that does not require
`amplifiers has been developed [1]. However, the pipeline archi-
`tecture has more circuits than the SAR architecture. Hence, an
`SAR architecture would still be a better choice for low-power
`and compact ADCs.
`Designing the ADC using small devices takes advantage of
`the scaling merits. Higher conversion rate and smaller area are
`direct benefits. Smaller area in turn contributes to reducing
`the power consumption, because the smaller parasitics reduce
`the required drive power. However, accuracy suffers from
`device mismatch. Many digitally assisted techniques have
`been reported in an attempt to resolve this issue. Foreground
`calibration was reported [2] as a way to align the mismatch of
`the capacitors, but the actual calibration was done via off-chip
`software processing. A nonbinary CDAC design based on unit
`capacitors [3] has redundancy for correcting the misjudgments
`of the comparator and/or incomplete CDAC settling. However,
`the linearity is still affected by capacitor mismatch. Nonbinary
`designs using
`-
`CDACs are reported in [4]. Redundancy
`works because the upper bit decision can have a larger redun-
`dancy. However, this structure needs additional stages as well
`as digital postprocessing. Another nonbinary design
`1.86 was implemented with individually arranged capacitors
`which can maintain linearity by using the perturbation tech-
`nique [5]. This technique can correct the mismatch of the radix
`between each bit. However, it also needs additional stages and
`digital postprocessing.
`This paper presents on-chip digital calibration techniques to
`correct the CDAC mismatches based on [2] and an internal clock
`control that enables a very slow conversion rate while avoiding
`the charge leakage problem of the CDAC. Section II describes
`the design and architecture of the proposed SAR ADC. Sec-
`tion III presents the calibration techniques and Section IV shows
`the experimental results. Conclusions are given in Section V.
`
`II. CIRCUIT DESIGN
`
`Manuscript received June 11, 2010; revised September 12, 2010; accepted
`September 20, 2010. Date of publication November 09, 2010; date of current
`version November 24, 2010. This paper was recommended by Associate Editor
`A. Hamoui.
`M. Yoshioka, K. Ishikawa, and S. Tsukamoto are with Fujitsu Laboratories
`Ltd., Kawasaki, Kanagawa 211-8588, Japan (e-mail: myoshi@labs.fujitsu.com;
`ishikawa.kiyo@jp.fujitsu.com; tsuka3@labs.fujitsu.com).
`T. Takayama is with the Fujitsu VLSI Ltd., Kasugai, Aichi 487-0013, Japan
`(e-mail: takayama.takesi@jp.fujitsu.com).
`Color versions of one or more of the figures in this paper are available online
`at http://ieeexplore.ieee.org.
`Digital Object Identifier 10.1109/TBCAS.2010.2081362
`
`A. ADC Architecture
`Fig. 1 shows the block diagram of the SAR ADC. The actual
`design is differential, but the figure shows a single-ended design
`for simplicity. It consists of a 10-b split-CDAC, a comparator,
`an internal clock generator, SAR controller, and a digital cali-
`bration circuit. The split-CDAC can reduce the number of unit
`capacitors relative to a conventional binary weighted CDAC de-
`sign; however, it is very sensitive to mismatch as well as to para-
`sitic capacitance. This causes a linearity error as a result. A vari-
`
`1932-4545/$26.00 © 2010 IEEE
`
`Authorized licensed use limited to: IEEE Publications Operations