US007268595B2
`
`(12)
`
`United States Patent
`Ajit
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,268,595 B2
`Sep. 11, 2007
`
`(54) SYSTEM AND METHOD FOR
`COMPENSATING FOR THE EFFECTS OF
`PROCESS, VOLTAGE, AND TEMPERATURE
`VARIATIONS IN A CIRCUIT
`
`(75) Inventor: Janardhanan S. Ajit, Irvine, CA (US)
`
`(73) Assignee: Broadcom Corporation, Irvine, CA
`(Us)
`
`.
`_
`( * ) Not1ce.
`
`.
`.
`.
`.
`Subject‘ to any d1scla1mer,'the term ofth1s
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 51 days.
`
`(22) Filed:
`
`’
`Jan. 10, 2006
`
`4,757,214 A
`4,772,812 A
`
`7/1988 Kobayashi
`9/1988 Desmarais
`_
`(Con?rmed)
`FOREIGN PATENT DOCUMENTS
`
`DE
`
`27 44 209
`
`4/1979
`
`OTHER PUBLICATIONS
`
`European Search Report from European Application No. 03004687.
`4, 3 pages, (dated Jun‘ 30, 2003)‘
`
`(Continued)
`ExamineriTuan Lam
`(74) Attorney, Agent, or F irmiSterne, Kessler, Goldstein &
`FOX PLLC
`
`(65)
`
`Prior Publication Data
`
`(57)
`
`ABSTRACT
`
`Us 2006/0114037 A1
`
`Jun‘ 1’ 2006
`_
`_
`Related U's' Apphcatlon Data
`(62) Division of application No. 10/293,259, ?led on Nov.
`14, 2002, noW Pat. No. 6,985,014.
`(60) Provisional a lication NO 60/361 033 ?led on Mar
`1 2002
`pp
`'
`’
`’
`'
`’
`'
`(51) Int C1
`H0'3B /00
`
`(2006 01)
`_
`_
`_
`'
`(52) US. Cl. ...................... .. 327/108, 327/112, 33226608823,
`_
`_
`_
`None
`(58) Field of'Cla'ssl?catlon Search ..............
`See apphcanon ?le for Complete Search hlstory'
`References Cited
`
`(56)
`
`U.S. PATENT DOCUMENTS
`
`4,170,740 A
`4,216,388 A
`
`10/1979 PernyesZi
`8/1980 Wilson
`
`400x
`
`A system and method for compensating for process, voltage,
`and temperature variations in a circuit is provided. A system
`includes an inverter having an input port, and an output port,
`and is con?gured to (i) receive an input signal, (ii) delay the
`received input signal, and (iii) provide the delayed signal to
`the inverter output port. The system also includes a logic
`device including at least tWo input ports and an output port.
`A ?rst of the at least tWo input ports is con?gured to receive
`the delayed signal. Finally, the system includes a charge
`storing device having a ?rst end coupled, at least indirectly,
`to a second of the at least tWo input ports and a second end
`Coupled to a logic device Common node‘ The Charge Storing
`device is con?gured to (i) receive the input signal and (ii)
`Sense a rate ofchange in Voltage Ofthe received input Signal’
`the sensed voltage being representative of a corresponding
`current. The logic device output port is con?gured to output
`an output signal responsive to the delayed signal and the
`corresponding current.
`
`5 Claims, 9 Drawing Sheets
`
`VDDO
`
`Vnno
`
`bias-p
`
`p0_gate
`
`V000
`
`V000
`
`p2_gate
`
`Vssc
`
`C
`fhpau
`
`V
`SSC
`
`Vssc
`
`Vssc
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 1
`
`

`

`US 7,268,595 B2
`Page 2
`
`US. PATENT DOCUMENTS
`
`5,107,139
`5,334,888
`5,546,029
`5,561,393
`5,736,888
`5,945,850
`6,084,437
`6,222,413
`6,351,138
`
`A
`A
`A
`*
`A
`A
`*
`A
`A
`B1
`
`4/1992
`8/1994
`8/1996
`10/1996
`4/1998
`8/1999
`7/2000
`4/2001
`2/2002
`
`Houston et al.
`Bodas
`Koke ....................... .. 327/108
`Sakurai et al.
`Sharpe-Geisler .......... .. 327/382
`Segan et a1.
`Sako
`Cahill
`Wong ........................ .. 326/30
`
`3/2002 Kwon
`6,353,349 B1
`4/2003 Maloney et al.
`6,545,520 B2
`3/2003 Nolan
`2003/0058005 A1
`2003/0067329 A1* 4/2003 Sendelweck .............. .. 327/112
`
`OTHER PUBLICATIONS
`
`English-language Abstract of Japanese Patent Publication No.
`11017520,
`1
`page, European Patent O?ice, (date of
`publicationiJan. 22, 1999).
`* cited by examiner
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 2
`
`

`

`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 3
`
`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 2 0f 9
`
`US 7,268,595 B2
`
`FIG. 2A
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 4
`
`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 3 0f 9
`
`US 7,268,595 B2
`
`FIG. 2B
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 5
`
`

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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 7
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`

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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 8
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`

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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 9
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`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 8 0f 9
`
`US 7,268,595 B2
`
`400x
`
`vDDO
`
`V000
`
`bias-p ‘
`
`p0_gate
`
`Vssc
`
`I
`
`‘
`
`I
`
`
`
`‘E90 T» V000
`
`p2_gate
`
`p
`
`'
`
`a i
`
`% fbpSU
`
`VSSC
`
`V
`ssc
`
`V
`ssc
`
`FIG. 4A
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 10
`
`

`

`U.S. Patent
`
`Sep. 11,2007
`
`Sheet 9 0f 9
`
`US 7,268,595 B2
`
`402x
`
`VDDO
`
`DDO
`
`DDO
`
`DDO
`
`n0_gate ’
`
`VSSC
`
`VSsc
`
`n2_gate
`
`_{
`
`bias_n
`
`I
`
`V880
`
`V830
`
`FIG. 4B
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 11
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`

`

`US 7,268,595 B2
`
`1
`SYSTEM AND METHOD FOR
`COMPENSATING FOR THE EFFECTS OF
`PROCESS, VOLTAGE, AND TEMPERATURE
`VARIATIONS IN A CIRCUIT
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The present application is a Divisional of US. Non
`Provisional application Ser. No. 10/293,259, ?led Nov. 14,
`2002 now US Pat. No. 6,985,014, Which claims the bene?t
`of US. Provisional Application No. 60/361,033, ?led Mar.
`1, 2002, all of Which is incorporated by reference herein in
`its entirety.
`
`BACKGROUND OF THE INVENTION
`
`2
`indirectly, to a second of the at least tWo input ports and a
`second end coupled to a logic device common node. The
`charge storing device is con?gured to (i) receive the input
`signal and (ii) sense a rate of change in voltage of the
`received input signal, the sensed voltage being representa
`tive of a corresponding current. The logic device output port
`is con?gured to output an output signal responsive to the
`delayed signal and the corresponding current.
`The present invention enables control of the output cur
`rent drive of I/O circuits independent of the PVT conditions.
`This is made possible by making the gate drive and the
`effective Width of the output driver p-channel metal oxide
`semiconductor (PMOS) and n-channel metal oxide semi
`conductor (NMOS), dependent on the rate of rise of a sense
`voltage. When the sense voltage rises faster than normal, the
`gate drive of the output driver PMOS is reduced or the
`number of ?ngers of the output driver PMOS that is con
`ducting is reduced and When the sense voltage falls faster
`than normal, the gate drive of the output driver NMOS is
`reduced or the number of ?ngers of the output driver NMOS
`that is conducting is reduced. This keeps the pad voltage rise
`and fall time relatively independent of fabrication process,
`supply-voltage and temperature.
`
`BRIEF DESCRIPTION OF THE
`DRAWINGS/FIGURES
`
`The accompanying draWings, Which are incorporated in
`and constitute a part of the speci?cation, illustrate an
`embodiment of the invention and, together With the descrip
`tion, explain the purpose, advantages, and principles of the
`invention.
`FIG. 1 is a schematic diagram of an exemplary output
`circuit constructed and arranged in accordance With the
`present invention;
`FIG. 2a is a schematic diagram of a PMOS portion of a
`circuit constructed and arranged in accordance With a ?rst
`embodiment of the present invention;
`FIG. 2b is a schematic diagram of the NMOS portion of
`the circuit constructed and arranged in accordance With the
`?rst embodiment of the present invention;
`FIG. 3a is a schematic diagram of a PMOS portion of a
`circuit constructed and arranged in accordance With a second
`embodiment of the present invention;
`FIG. 3b is a schematic diagram of the NMOS portion of
`the circuit constructed and arranged in accordance With the
`second embodiment of the present invention;
`FIG. 30 is an illustration of current ?oW through the
`circuit shoWn in FIG. 3a;
`FIG. 3d is an illustration of current ?oW through the
`circuit shoWn in FIG. 3b;
`FIG. 4a is a variation of the circuit shoWn in FIG. 3a; and
`FIG. 4b is a variation of the circuit shoWn in FIG. 3b.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`The folloWing detailed description of the present inven
`tion refers to the accompanying draWings that illustrate
`exemplary embodiments consistent With this invention.
`Other embodiments are possible, and modi?cations may be
`made to the embodiments Within the spirit and scope of the
`present invention. Therefore, the folloWing detailed descrip
`tion is not meant to limit the invention. Rather, the scope of
`the invention is de?ned by the appended claims.
`It Would be apparent to one of skill in the art that the
`present invention, as described beloW, may be implemented
`
`20
`
`25
`
`30
`
`1. Field of the Invention
`The present invention relates generally to controlling
`electrical characteristics associated With input/output (I/O)
`circuits. More particularly, the present invention relates to
`developing I/O circuits having electrical characteristics,
`such as operating frequencies, that are independent of varia
`tions in fabrication process, supply-voltage, and temperature
`(PVT) conditions.
`2. Related Art
`I/O circuits are used to interface traditional integrated
`circuits (ICs) With electrical environments external to the IC.
`The U0 circuit acts as a driver for signals generated by the
`IC and provides these signals to a pad, Which in-turn
`interfaces With the external electrical environment. The U0
`circuit may also receive signals from the external electrical
`environment through the pad. A critical challenge in the
`design, fabrication, and operation of these I/O circuits is that
`their electrical characteristics may vary depending on the
`particular PVT conditions.
`In order to create independence betWeen the electrical
`characteristics of the I/O circuits and PVT conditions, it is
`desirable that the SleW-rate (change in pad-voltage Vpad
`With rise time/fall time) should be relatively constant. In
`other Words, the transient current drive [I:(dVpad/dt)/
`CZOGdISIeW-rate/CZOM, Where Cloafload capacitance] of the
`I/O circuit should be independent of the PVT conditions.
`Traditional approaches for ensuring that the electrical
`characteristics of I/O circuits remain independent of PVT
`45
`conditions include complicated sWitching arrangements.
`These sWitching arrangements, for example, sWitch the
`number of ?ngers betWeen the pre-driver and the output
`driver devices. These traditional approaches, hoWever, con
`sume unacceptable amounts of the IC’s real estate and are
`therefore less than optimal.
`What is needed, therefore, is an e?icient technique to
`ensure that the electrical performance of I/O circuits remains
`substantially stable and independent from PVT variations.
`
`35
`
`40
`
`50
`
`SUMMARY OF THE INVENTION
`
`Consistent With the principles of the present invention as
`embodied and broadly described herein, an exemplary appa
`ratus includes an inverter having an input port, and an output
`port, and con?gured to (i) receive an input signal, (ii) delay
`the received input signal, and (iii) provide the delayed signal
`to the inverter output port. The apparatus also includes a
`logic device including at least tWo input ports and an output
`port. A ?rst of the at least tWo input ports is con?gured to
`receive the delayed signal. Finally, the system includes a
`charge storing device having a ?rst end coupled, at least
`
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`60
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`US 7,268,595 B2
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`20
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`30
`
`3
`in many different embodiments of hardware, software, ?rm
`ware, and/or the entities illustrated in the ?gures. Any actual
`software code with specialized control hardware to imple
`ment the present invention is not limiting of the present
`invention. Thus, the operation and behavior of the present
`invention will be described with the understanding that
`modi?cations and variations of the embodiments are pos
`sible, given the level of detail presented herein.
`An exemplary output circuit 100 is shown in FIG. 1. Apad
`102 is driven by ?ngers of PMOS 104 and 106 and ?ngers
`ofNMOS 108 and 110. A gate signal received by PMOS 104
`is indicated by p0 _gate and is directly generated from a
`pre-driver-p signal 112. A gate signal of NMOS 108 is
`indicated by n0_gate and is directly generated from a
`pre-driver-n signal 114. The gate signal for PMOS 106 is
`derived from PMOS PVT compensator circuit 116 and the
`gate signal of NMOS 110 is derived from an NMOS PVT
`compensator circuit 118.
`When the PVT condition is such that the fall of the
`p0 _gate signal is slow, the PMOS PVT compensator circuit
`116 produces a quickly falling p2_gate signal. When the
`PVT condition is such that the fall of the p0_gate signal is
`fast, the PMOS PVT compensator circuit 116 produces a
`slowly falling p2_gate signal. When the PVT condition is
`such that the rise of the n0-gate signal is slow, the NMOS
`25
`PVT compensator circuit 118 produces a quickly rising
`n2 _gate signal. When the PVT condition is such that the rise
`of the n0_gate signal is fast, the NMOS PVT compensator
`circuit 118 produces a slowly rising n2 _gate signal.
`The basic idea of the compensator circuits 116 and 118 is
`that the rate of change of the voltage signals p0_gate/
`n0 _gate at gates of drivers, PMOS 104 and NMOS 108, is
`sensed by a capacitor Cfb, within corresponding PVT com
`pensator circuits 116 and 114. A resulting current
`[lsensfCfb’l‘dVgate/dt] is used to adjust respective gate
`35
`drive signals p2_gate/n2_gate of remaining drivers PMOS
`106 and NMOS 110.
`Exemplary transistor level implementations of the com
`pensator circuits 116 and 114 are respectively shown in
`FIGS. 2a and 2b. The PMOS PVT compensator circuit 116
`shown in FIG. 211 includes an inverter/delay stage 200, a
`logic gate stage 202, and a capacitor (C?w) 204. In the
`present exemplary embodiment, the inverter/ delay stage 200
`is implemented using an inverter and the logic gate stage 202
`is implemented using a NAND gate.
`The inverter/delay stage 200 is comprised of a PMOS
`active device 206 and an NMOS active device 207.
`Although the active devices 206 and 207 are implemented
`using respective pull-up and pull down transistors, the
`present invention can be implemented using other varieties
`of active devices. Further, although the active device 207 is
`shown to have a substrate node 208, the substrate node 208
`is not used in the present embodiment. Traditional power
`supplies provide supply voltages VDDO for the PMOS device
`206 and VSSC for the NMOS device 207. As shown in FIG.
`2A, gates of the active device 206 and 207 form a ?rst input
`port 209 to the compensator circuit 116. The ?rst input port
`209 is con?gured to receive the input signal p0_gate. A
`connection between a source of the active device 206 and a
`drain of the active device 207 forms an output port of the
`inverter/ delay stage 200.
`The logic gate stage 202 is implemented in the present
`invention as a NAND gate including active devices 212,
`214, 216, and 218. As shown, a logic gate stage 202 input
`port 211 is formed of gates of the active devices 212 and
`214. A connection of the source of the active device 212, the
`drain of the active device 214, and the source of the active
`
`55
`
`4
`device 218 forms an output port 220 of the compensator
`circuit 116. A connection point between gates of the active
`devices 216 and 218 and a ?rst end of the capacitor 204 form
`a node 222. An optional resistor 205 may also be connected
`between the node 222 and the power supply providing the
`voltage VDDO. The optional resistor 205 can be used to set
`the steady-state bias voltage of node 222 to VDDO. The
`resistors used herein can be implemented as MOSFET
`resistors. The other end of the capacitor 204 forms a second
`input port 224 to the compensator circuit 116. The second
`circuit input port 224 is also con?gured to receive the input
`signal p0_gate.
`The voltage at the node 222 is dependent on PVT con
`ditions and thus the gate drive signal p2_gate also depends
`on PVT conditions. When the voltage of the pad 102 is to be
`pulled high, due to the PVT conditions, the voltage p0_gate
`falls and becomes low. When the fall of the p0_gate signal
`is fast, the corresponding current [lp:Cfbp*dV(p0_gate)/dt]
`through capacitor 204 is large. This quickly reduces the
`voltage at the node 222 and therefore one of the inputs 211
`and 222 to the logic gate stage 202 becomes low. This makes
`the output drive voltage p2_gate of the NAND gate within
`the logic gate stage 202 high.
`On the other hand, when the fall of the p0_gate signal is
`slow, as might also occur due to variations in PVT condi
`tions, the current (lp) through capacitor 204 is small. This
`in-tum keeps the voltage at the node 222 high and thus one
`of the inputs to the NAND gate becomes high. The other
`input 211 to the voltage of p0_gate is low. This makes the
`output drive voltage p2_gate produced at the output port 220
`low, since both of the inputs to the NAND gate, within the
`logic gate stage 202, are high.
`The NMOS PVT compensator circuit 118 is shown in
`FIG. 2b. The NMOS PVT compensator circuit 118 coop
`eratively functions with the compensator circuit 116 to
`ameliorate the effects of PVT variations in l/O circuits, such
`as the I/O circuit 100 shown in FIG. 1.
`The compensator circuit 118 includes an inverter/delay
`stage 230, a logic gate stage 232, and a capacitor (Cfbn) 234.
`The capacitors of the present invention can be implemented
`in many ways including MOS capacitors, Metal-Oxide
`Metal capacitors etc. In the NMOS circuit 118, the inverter/
`delay stage 230 is also implemented using an inverter, as in
`the case of the inverter/delay stage 200 above. The inverter/
`delay stage 230 respectively includes PMOS and NMOS
`active devices 235 and 236.
`Gates of the active devices 235 and 236 combine to form
`a ?rst input port 233 to the NMOS PVT compensator circuit
`118. The ?rst input port 233 is con?gured to receive the
`input signal n0 _gate. An inverter/delay stage 230 output port
`is formed of a source and a drain of the active devices 235
`and 236 respectively. The output port of the inverter/delay
`stage 230 is coupled to an input port 239 of the logic gate
`stage 232 of the compensator circuit 118.
`The logic gate stage 232 is implemented using a NOR
`gate, which is in-tum formed using active devices 237, 238,
`240, and 242. A connection point of the source of the active
`device 238, the drain of the active device 236, and the drain
`of the active device 242 forms an output port 244 of the
`compensator circuit 118 from it NOR gate that is con?gured
`to output a signal n2_gate. A connection point between gates
`of the active devices 240 and 242 and a ?rst end of the
`capacitor 234 forms a node 246. An optional resistor 248
`may also be connected between the node 246 and the power
`supply providing the voltage VSSC. The other end of the
`capacitor 234 forms a second input port 250 to the compen
`
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`US 7,268,595 B2
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`5
`sator circuit 118. The second circuit input port 224 is also
`con?gured to receive the input signal n0_gate.
`Avoltage at the node 246 depends on PVT conditions and
`thus the signal n2_gate also depends on PVT conditions.
`When the voltage of the 102 pad is pulled loW, the voltage
`n0 _gate is correspondingly pulled high. When the rise of
`n0 _gate signal is fast, the current [ln:Cfbn*dV(n0-gate)/dt]
`through the capacitor 234 is large. This quickly increases the
`voltage at node 246. Since the voltage at the node 246
`quickly increases, the input 246 to the NOR gate becomes
`high. Correspondingly, the output voltage n2_gate of the
`NOR gate becomes loW. When the rise of the n0_gate signal
`is sloW, the current (In) through capacitor 234 is small. This
`keeps the voltage at the node 246 loW and so the associated
`input to the NOR gate becomes loW. The other input 239 to
`the NOR gate is loW since it is the inverse of voltage of
`n0 _gate and voltage of n0_gate is high. This makes the
`output voltage n2_gate of the NOR gate high since both the
`inputs are loW.
`Another exemplary transistor level implementation of the
`compensator circuit, including circuit portions 300 and 302,
`is illustrated in FIGS. 3A and 3B. This implementation
`requires pre-driver signals (P) and (N) inputs in addition to
`p0 _gate and n0_gate input signal. A PMOS compensator
`circuit 300 is shoWn in FIG. 3A.
`In the circuit 300 of FIG. 3A, a capacitor (Cfbp30) 328
`senses the rate of change of the pre-driver voltage VP of the
`signal (P). When the pre-driver voltage VP quickly increases
`With time [high rising dVP/dt], a current [I31] ?oWs across
`the capacitor 328 depending on the dVp/dt and the particular
`value of the capacitors [I30:Cfbp30*dVp/dt]. The increase
`of I30 reduces the current (I32) through PMOS transistor
`324. Using a current mirror With multiplication, this reduc
`tion in current (I32) is multiplied to the required level and
`the resulting current reduces the gate drive of NMOS 312
`and simultaneously increases the gate drive of PMOS 314.
`This results in control of the gate-drive p2 _gate applied to a
`sub-section (?ngers) of the PMOS driver 106. The current
`mirror includes PMOS transistors 320 and 324.
`The ratio of the effective Width/length (W/ L) of the device
`320 to 324, is Kp, also knoWn as the current multiplication
`factor. When the reduction in the current (I32) occurs
`through the device 324, the reduction in the current (I33)
`through the device 320 is Kp*132. A resistor 326 is used to
`set the steady-state bias voltage of node 316 to VDDO. The
`current ?oWing through NMOS 318 is equal to the current
`that ?oWs through PMOS transistor 320. The ratio of effec
`tive W/L of NMOS 312 to NMOS 318 is Kn, the current
`multiplication factor. When the reduction in current 133
`occurs through nmos 318, the reduction in current (I34)
`through PMOS 314 is Kn*I33 :Kn’FKP*I32. The current
`?oW through the PMOS compensator circuit 300 is shoWn in
`FIG. 3C.
`When the dVP/dt is small, the PMOS ?ngers 106 and 106
`are enabled through their respective gate drive signals
`p0 _gate and p2_gate. When the dVP/dt gets larger, the
`current through capacitor 328 increases, Which in-turn
`increases the voltage of the node 322. Consequently, the
`voltage of node 316 is also loWered, resulting in the voltage
`of the p2_gate going higher and disabling a portion of the
`PMOS ?nger 106. Thus, the total current supplied from the
`PMOS ?ngers 104 and 106 is kept relatively constant and
`the rate of rise of the pad-voltage (rising SleW-rate) associ
`ated With the pad 102 is kept relatively constant. In short,
`When the current supplied by portion of PMOS MPd0
`becomes higher, a portion of the PMOS 106 is disabled by
`the PVT compensation circuit 300 to keep the total current
`supplied by the PMOS ?ngers 104 and 106 constant across
`varying PVT conditions.
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`6
`A similar circuit 302 is used in the driver NMOS section,
`as shoWn in FIG. 3B. When a pre-driver voltage n increases
`sloWly With time, the rising magnitude of dVn/dt is small, the
`node 347 remains at a high-voltage, Which causes the node
`341 to remain at a loW-voltage. This occurrence leads to the
`voltage of the n2 _gate going high and all of the NMOS
`?ngers 108 and 110 are enabled through their respective gate
`n0_gate and n2_gate drive signals. When the dVn/dt gets
`larger in magnitude, a current 135 through a capacitor 352
`increases Which reduces a current I36 through NMOS 348.
`This reduces the current through NMOS 346 (Kn2*I36),
`Which in-tum reduces the current through PMOS 344, thus
`increasing the voltage of node 341, resulting in the voltage
`of n2_gate going loWer. Consequently, a portion of the
`NMOS ?nger 110 is disabled. Thus the total current supplied
`from the NMOS 108 and 110 is relatively constant and hence
`the rate of fall of the pad-voltage (falling SleW-rate) is kept
`relatively constant. A current ?oW through the NMOS com
`pensator circuit 302 is shoWn in FIG. 3D.
`Still other exemplary transistor level circuits 400 and 402
`of the compensator circuits of the present invention are
`shoWn in FIGS. 4A and 4B. The embodiment shoWn in
`FIGS. 4A and 4B is a variation of the embodiment of FIGS.
`3A and 3B respectively, Wherein a current source is used to
`provide a Wider analog control over the voltage of the
`p2_gate and n2 _gate. In FIG. 4A, a bias_p gate is a
`controlled voltage referenced to the supply voltage VDDO. In
`the simplest case, bias_p is tied to VSSC. In FIG. 4B, bias_n
`is a controlled voltage referenced to VSSC. In the simplest
`case, bias_n is tied to VDDO.
`The foregoing description of the preferred embodiments
`provide an illustration and description, but is not intended to
`be exhaustive or to limit the invention to the precise form
`disclosed. Modi?cations and variations are possible consis
`tent With the above teachings, or may be acquired from
`practice of the invention.
`
`What is claimed is:
`1. A circuit comprising:
`?rst and second active devices, a junction formed of ?rst
`nodes of the ?rst and second devices forming a ?rst
`input port and a junction formed of respective second
`and third nodes of the ?rst and second devices forming
`a ?rst output port;
`third, fourth, and ?fth active devices, a gate of the third
`device being coupled to the ?rst output port, a source
`of the third device being connected to a drain of the
`fourth device, and a drain of the third device being
`connected to a source of the ?fth device, the drain of the
`third device and the source of the ?fth device forming
`an output port;
`Wherein a gate of the ?fth device forms a second input
`Port;
`sixth, seventh, and eighth active devices, a gate of the
`sixth device being connected to a gate of the fourth
`device, a drain of the sixth device being connected to
`a source of the seventh device, the gate and drain of the
`sixth device being connected together;
`Wherein a gate of the seventh device is connected to a gate
`of the eight device, the gate and a source of the eighth
`device being connected together; and
`a charge storing device having a ?rst end forming a third
`input port and a second end connected to the source of
`the eighth device.
`2. The circuit of claim 1, further comprising an impedance
`device having a ?rst end coupled to the second end of the
`charge storing device.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 14
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`US 7,268,595 B2
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`3. The circuit of claim 2, wherein the active devices
`include transistors.
`4. The circuit of claim 3, Wherein the ?rst nodes are gates,
`the second nodes are sources, and the third nodes are drains.
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`5. The circuit of claim 4, Wherein the charge storing
`device is a capacitor.
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1005 Page 15
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