1916
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27, NO. 12,DECEMBER
`
`1992
`
`Design Techniques for High-Speed, High-Resolution
`Comparators
`
`Behzad Razavi, Member, IEEE, and Bruce A. Wooley, Fellow, IEEE
`
`Abstract—This paper describes
`for the
`precision techniques
`design of comparators
`used in high-performance
`analog-to-dig-
`ital converters
`employing parallel conversion stages. Following
`a review of conventional
`offset cancellation
`techniques,
`circuit
`designs achieving
`12-b resolution in both BiCMOS and CMOS
`5-V technologies
`are presented. The BiCMOS comparator
`con-
`sists of a preamplifier
`followed by two regenerative
`stages and
`achieves an offset of 200 pV at a 1O-MHZ clock rate while dis-
`sipating 1.7 mW.
`In the CMOS comparator
`offset cancellation
`is used in both a single-stage
`preamplifier
`and a subsequent
`latch to achieve an offset of
`less than 300 pV at comparison
`rates as high as 10 MHz, with a power dissipation
`of 1.8 m W.
`
`I. INTRODUCTION
`
`IN high-speed analog-to-digital
`
`comparator
`converters,
`influence on the overall perfor-
`design has a crucial
`mance that can be achieved. Converter architectures
`that
`incorporate
`a large number of comparators
`in parallel
`to
`obtain a high throughput
`rate impose stringent constraints
`on the delay,
`resolution, power dissipation,
`input voltage
`range,
`input impedance,
`and area of those circuits. More-
`over,
`the relatively large device mismatch
`and limited
`voltage range that accompany the integration of compar-
`ator circuits in low-voltage
`scaled VLSI technologies
`se-
`verely compromise
`the precision that can be obtained.
`This paper
`introduces
`a number of comparator design
`techniques
`for use in parallel A/D converters
`that are im-
`plemented in BiCMOS and CMOS VLSI
`technologies.
`The suggested methods are intended to provide improved
`resolution and speed while maintaining low power dissi-
`pation,
`a small
`input capacitance,
`and low complexity.
`The techniques are presented within the context of prac-
`tical designs for both a BiCMOS and a CMOS comparator
`with 12-b resolution at 1O-MHZ comparison
`rates. The
`BiCMOS comparator
`employs
`a low-gain
`preamplifier
`followed by two regenerative
`amplifiers to achieve an off-
`set of 200 pV at clock rates as high as 10 MHz.
`In the
`CMOS comparator, offset cancellation is used in both the
`preamplifier and the subsequent
`latch to achieve an offset
`of less than 300 pV at 10 MHz.
`
`Manuscript received March 4, 1992; revised July 13, 1992. This work
`was supported by the Army Research Office under Contract DAAL03-91 -
`G-0088.
`B. Razavi was with the Center for Integrated Systems, Stanford Univer-
`sity, Stanford, CA 94305. He is now with AT&T Bell Laboratories, Holm-
`del, NJ 07733.
`B. A. Wooley is with the Center for Integrated Systems, Stanford Uni-
`versity, Stanford, CA 94305.
`IEEE Log Number 9204135.
`
`The next section of this paper reviews some of the con-
`ventional approaches
`to offset cancellation
`and identifies
`their
`fundamental
`trade-offs
`and limitations.
`The Bi-
`CMOS comparator
`is then described in Section III, and
`the design of the CMOS comparator
`is presented in Sec-
`tion IV. The experimental
`results obtained for both cir-
`cuits are summarized in Section V.
`
`II. OFFSET CANCELLATION TECHNIQUES
`A. Circuit Topologies
`in CMOS and
`The analog sampling capability inherent
`BiCMOS technologies provides a means whereby offsets
`can be periodically
`sensed,
`stored,
`and then subtracted
`from the input
`[1]. Of
`the various offset cancellation
`methods,
`two of the most common approaches, based on
`input offset storage (10S) and output offset storage (00 S),
`are considered herein. Fig. 1(a) and (b) illustrates
`these
`two approaches as applied to a fully differential
`compar-
`ator. Each of these topcdogies comprises a preamplifier,
`offset storage capacitors,
`and a latch. With 10S,
`the can-
`cellation is performed by closing a unity-gain loop around
`the preamplifier
`and storing the offset on the input cou-
`pling capacitors. With 00S,
`the offset
`is cancelled by
`shorting the preamplifier
`inputs and storing the amplified
`offset on the output coupling capacitors. A comparison of
`these two approaches
`reveals their respective merits and
`drawbacks.
`the residual
`In the comparator with 10S,
`offset (i. e.,
`the offset after calibration)
`is
`
`input-referred
`
`Vos1
`Vos = ——
`l+AO
`
`; AQ ~ VosL
`C
`AO
`
`(1)
`
`where Vos 1 and A. are the input offset and gain of the
`preamplifier,
`respectively, AQ is the mismatch in charge
`injection from switches ~ 5 and S6 onto capacitors C 1 and
`C2, and Vos~ is the latch offset.
`In the comparator
`em-
`ploying 00S,
`the residual offset is
`
`vo~’—+—
`
`AQ
`AOC
`
`vo~~
`A. “
`
`(2)
`
`Equations (1) and (2) show that, for similar preamplifiers,
`the residual offset obtainable using 00S can be smaller
`than that for 10S.
`In fact, unless sufficient statistical data
`for Vos,, AQ, and Vos~are available, 10S requires the use
`of quite large values for A. and C to guarantee a low Vos.
`
`0018-9200/92$03
`
`.0001992
`
`IEEE
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 1
`
`

`

`RAZAVI AND WOOLEY:
`
`DESIGN TECHNIQUES
`
`FOR HIGH-SPEED, HIGH-RESOLUTION COMPARATORS
`
`1917
`
`...-++-‘Wt
`+i2H=-
`
`-Jd24a
`
`(a)
`
`*
`
`+
`
`(b)
`Fig. 1. Comparator offset cancellation techniques: (a)input offset storage,
`and (b) output offset storage.
`
`Since the value of the input coupling capacitors with
`10S is governed by charge injection, kT/ C noise, and at-
`tenuation considerations,
`the input capacitance of this to-
`pology is usually higher
`than that of the 00S configura-
`tion. During offset cancellation,
`the input capacitance of
`the 10S circuit
`is equal
`to the offset storage capacitor,
`while in the comparison mode it is approximately the sum
`of the input capacitance of the preamplifier
`and the para-
`sitic capacitances
`of the offset storage capacitor. These
`parasitic capacitances
`are typically as large as 0.1 to 0.2
`pF for input storage capacitors
`in the range of 0.5 to 1
`pF, whereas
`the preamplifier
`input capacitance
`can be
`maintained below 30 fF. For this reason 00S is generally
`preferable
`in flash stages, where many comparators
`are
`connected in parallel. Of course,
`the dc coupling at the
`input of an 00S
`comparator
`limits
`the common-mode
`range. Also,
`in applications where a large differential
`ref-
`erence voltage must be stored in the comparator
`[2],
`the
`preamplifier of the 00S topology must be designed for a
`low gain so that it does not saturate at its output.
`While 10S is accomplished by means of a closed feed-
`back loop, which forces the preamplifier
`into its active
`region, 00S is normally an open-loop operation that re-
`quires tight control of the amplifier gain. Therefore, 00S
`is typically implemented
`using a single-stage
`amplifier
`with a gain of less than 10 to ensure operation in the active
`region under extreme variations
`in device matching and
`supply voltage.
`the pream-
`In conventional CMOS comparator designs,
`plifier is typically followed by a standard dynamic CMOS
`latch. As shown in the following subsection,
`this latch has
`a potentially large input offset and therefore requires the
`use of a high-gain preamplifier
`in order to achieve a low
`offset. Consequently,
`in high-resolution
`applications
`a
`single stage of 00S cannot be used, while a single-stage
`high-gain preamplifier with 10S suffers from a long delay.
`The above considerations
`have led to the use of multi-
`stage calibration
`techniques
`in high-resolution
`applica-
`
`.
`
`..+-+
`
`Fig. 2. Multistage offset cancellation.
`
`comparator
`a typical multistage
`tions. Fig. 2 illustrates
`topology that,
`in effect, utilizes both 10S and 00S when
`it is clocked sequentially [2], [3]. The overall gain of the
`circuit
`is chosen so that an input of 0.5 LSB overcomes
`the offset of the latch (50 to 100 mV), and the number of
`stages is then selected to provide the smallest delay [2].
`In the configuration of Fig. 2 a large latch offset
`is ac-
`commodated
`through the use of multiple
`preamplifier
`stages, each with offset cancellation. Alternatively,
`the
`offset of the latch can be reduced so as to relax the gain
`required of the preamplifier. This can be accomplished
`through the use of either devices with inherently low off-
`sets or offset cancellation in the latch.
`
`in a Dynamic CMOS Latch
`B. Design Constraints
`In order to synchronize
`the operation of a comparator
`with other parts of a system, as well as provide the gain
`needed to generate logic levels at the output, a regenera-
`tive amplifier
`is normally used as the final comparator
`stage. Fig. 3 shows a dynamic CMOS latch similar to that
`used in [4] to amplify small differences
`to CMOS levels.
`In this circuit, when @ is low, M5 is off, S 1 and S2 are
`on, and the latch senses the inputs Vi., and Vi.2. When @
`goes high, S 1 and S2 turn off to isolate nodes X and Y
`from input
`terminals
`and M5 turns on to initiate regen-
`eration.
`and estimate a lower
`In order to simplify calculations
`bound for the offset of the latch in Fig. 3, only the mis-
`matches between M 1 and M2 and between S 1 and S 2 are
`considered here.
`In practice,
`other errors
`such as mis-
`matches between M3 and M4 further
`increase the offset.
`Considering only the M 1, M2 and S 1, S2 mismatches,
`the input offset of the latch can be expressed as
`
`‘os~=Av~~+i($”:)(vGs
`‘TH)+%
`
`(3)
`
`where AV~~and V~~are the standard deviation and mean
`of the threshold voltage, AW/ W and AL/L are relative
`dimension mismatches, VG~– V~~ represents
`the initial
`gate-source
`overdrive, AQ is the charge injection mis-
`match between S 1 and S2, and CDis the total capacitance
`at X or Y (assumed equal on both sides). For optimistic
`values of AVTH= 5 mV, AW/W = AL/L = 0.05, VGs
`– V~H= 1 V, AQ = 0.5 fC, and CD = 100 fF,
`the latch
`offset voltage is approximately
`60 mV, with its major
`component arising from the second term in (3). This term
`can be reduced by increasing W and L and/or decreasing
`VGs– V~H,i.e., decreasing the initial drain current of M 1
`and M2. However,
`these remedies can degrade the speed
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 2
`
`

`

`1918
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27, NO. 12,DECEMBER
`
`1992
`
`‘3E=F’VD”
`‘in’’TbdT’vin2
`
`Q. J
`
`M511_/
`
`111. A SELF-CALIBRATING
`BiCMOS
`COMPARATOR
`the fundamental
`As discussed in Section II,
`limitations
`of CMOS comparators
`stem from the large offset of their
`latch, and the consequent gain required of the preampli-
`fier. The BiCMOS comparator described in this section
`employs a latch that consists of devices with inherently
`low offset to ease the performance
`required of the pream-
`plifier. This is accomplished through the use of a bipolar
`latch interposed between a preamplifier
`and a CMOS out-
`put latch.
`
`A. Architecture
`and timing of the Bi-
`Fig. 4 shows the architecture
`CMOS comparator. The circuit comprises a preamplifier,
`offset storage capacitors,
`a bipolar
`latch, and a CMOS
`latch. Controlled by clocks @, and *2, the circuit operates
`as follows.
`In the calibration mode, S 1 and S2 are off,
`S3-S6 are on, and the inputs of the preamplifier
`and the
`bipolar latch are grounded. The preamplifier offset is thus
`amplified and stored on C 1 and C2. In this mode,
`the two
`latches
`are also reset.
`In the comparison mode,
`first
`S3-S6 turn off while S 1 and S2 turn on; the input voltage
`V, is thereby sensed and amplified, generating a differen-
`tial voltage at the bipolar latch input. Next,
`the two latches
`are strobed sequentially
`to produce CMOS levels at the
`output. The residual
`input-referred
`offset of this configu-
`ration is determined by the bipolar
`latch offset divided by
`gain. For an emitter-coupled
`bipolar
`the preamplifier
`latch,
`the latch offset voltage can be approximated
`as
`
`‘7)
`‘o+%++)
`relative dimension
`represent
`where AW/ W and AL/L
`the two devices.
`of
`mismatches
`between
`the emitters
`Comparison of (3) and (7) indicates that, assuming equal
`dimension mismatches
`for bipolar and MOS transistors,
`Vos~ can be substantially less than VosMbecause kT/q =
`26 mV (at
`room temperature) whereas VG~ – V~H =
`0.5-1 V. The lower offset of the bipolar
`latch permits a
`smaller gain in the preamplifier,
`resulting in a correspond-
`ingly faster response.
`the output
`In order
`to generate 5-V CMOS levels at
`from a 200-KV input,
`the comparator must provide
`an
`equivalent gain of 250001, a constraint
`that demands care-
`ful gain allocation among the three stages.
`In this design,
`the preamplifier has a gain of 20, while each of the two
`latches exhibits an equivalent gain of several
`thousand.
`As described in following subsections,
`these latches have
`a finite maximum gain because they steer a finite amount
`of charge.
`
`B. BiCMOS Preampli)er
`is shown in Fig. 5.
`The preamplifier
`circuit
`It com-
`prises source followers M 1 and M2,
`the differential pair
`Q 1 and Q2,
`and emitter
`followers Q3 and Q4. The
`preamplifier gain is stabilized against variations
`in tem-
`perature by using bias currents proportional
`to absolute
`
`:
`Fig. 3. Dynamic CMOS latch.
`
`of the latch by increasing the regeneration
`7R. Since
`
`time constant
`
`~m
`
`(4)
`
`of M 1 and M2,
`transconductance
`where g~ is the initial
`the delay–offset product of this latch assumes the follow-
`ing form:
`
`form if CD is as-
`This relationship reduces to a simpler
`sumed to only include the gate–source capacitance of M 1
`or A42, i.e.,
`if CD = (2/3) WLCOX.Then, substituting for
`CD and g~ gives
`
`I
`
`where Z~is the initial drain current of M 1 and M2, which
`is determined by the dimensions of M5 and the high level
`of @. Note from (6) that although increasing L decreases
`its overall
`impact
`is to increase all of the three
`AL/L,
`terms,
`thus raising the delay–offset product.
`Increasing W
`diminishes
`the last
`two terms but slowly raises the first
`term; since the second term contributes most, a W of 5 to
`10 times minimum size should be used. From (6) it also
`follows that increasing Z~only slightly improves the trade-
`off. These observations
`indicate that, unless mismatch ef-
`fects in a process are well characterized,
`a simple CMOS
`latch design will not reliably attain offsets less than sev-
`eral tens of millivolts.
`the latch in Fig. 3
`In addition to a large input offset,
`generates a great deal of kickback noise at its inputs when
`it is reset. This noise is largely differential because the
`two sides of the latch begin from different supply rails and
`swing in opposite directions
`toward their input common-
`mode voltage. As a result,
`the input
`levels are severely
`disturbed and may take a long time to recover
`if the pre-
`ceding circuit does not have a low output
`impedance.
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 3
`
`

`

`RAZAVI AND WOOLEY:
`
`DESIGN TECHNIQUES
`
`FOR HIGH-SPEED, HIGH-RESOLUTION
`
`COMPARATORS
`
`1919
`
`to establish a bias across capacitors C 1 and C2 in Fig. 4,
`which are simply large NMOS transistors
`in this imple-
`mentation.
`
`“$$=+E==””’
`= =
`
`@l
`
`l S1-S20FF
`l S2-S6ON
`l LATCHES RESET
`
`l S1-S20N
`l S2-S60FF
`. LATCHES RESET
`
`C. Bipolar Latch
`A combined circuit diagram of the bipolar and CMOS
`latches is shown in Fig. 6. The bipolar
`latch consists of
`cross-coupled transistors Q 5 and Q 6 and a charge-pump-
`ing circuit, M 11, M 12, and C 3. The coupling capacitors
`C 1 and C2 act both as offset-storage
`elements and load
`devices
`for the bipolar
`latch. During calibration,
`*~ is
`low, grounding the nodes X 1 and Y1, and 02 is high,
`discharging C3 to V~~. During comparison, @l goes high
`and, after the preamplifier has sensed the input and a dif-
`ferential voltage is developed at X 1 and Y1, @zgoes’low,
`turning M 12 on and transferring
`charge through the bi-
`polar pair.
`In a fashion similar
`to that described in [6],
`the voltage difference between nodes X 1 and Y1 is re-
`generatively
`amplified until C3 charges up and the tail
`current of the pair falls to zero. This operation, which can
`be viewed as charge sharing between C3 and the combi-
`nation of C 1 and C2, occurs quickly because of
`the
`positive
`feedback
`around Q 5 and Q 6 and the large
`transconductance
`of these devices. With an initial voltage
`difference of 1 mV between nodes X 1 and Y1, the latch
`produces a differential voltage of several hundred milli-
`volts in less than 5 ns.
`than cur-
`rather
`Since the bipolar
`latch steers charge,
`current-
`rent,
`it has two advantages
`over conventional
`steering bipolar
`latches: 1) it draws no input current dur-
`ing calibration and can therefore be directly coupled to
`C 1 and C2 without
`input bias current cancellation,
`and
`2) it has zero static power dissipation. Also,
`in this ap-
`plication the preamplifier
`need only attenuate
`the input
`offset resulting from the V~~mismatch of the two bipolar
`transistors Q 5 and Q 6,
`rather
`than the larger VG~mis-
`match of two MOS devices as would be necessary if a
`CMOS latch were used.
`latch intro-
`The charge-sharing
`nature of the bipolar
`duces a relationship between gain and delay that differs
`from that for current-steering circuits.
`In the latter the gain
`can approach infinity if sufficient
`time is permitted for re-
`generation, while the former has a finite gain because of
`the limited charge available for regeneration. The Appen-
`dix presents
`an analysis
`of
`transient
`response
`of
`the
`charge-steering
`latch to better illustrate this behavior.
`
`“’~:x%%zl=?
`
`Fig.4. BiCMOScomparator bIockdiagram and timing.
`
`@l,
`
`($),0
`
`12($
`
`Fig. 5. BiCMOS preamplifier.
`
`of
`temperature. By virtue of the large transconductance
`the bipolar
`transistors,
`the differential
`amplifier achieves
`a bandwidth of more than 100 MHz with a power dissi-
`pation of only 0.5 mW.
`is
`An important
`issue in the design of the preamplifier
`the input noise. The flicker noise of MOS devices is quite
`substantial;
`as a consequence,
`large transistors must be
`used at the input unless
`this noise is reduced by offset
`cancellation.
`If the comparator offset is cancelled on every
`cycle,
`the time interval between offset cancellation
`and
`comparison does not exceed a few tens of nanoseconds.
`Hence, only those flicker noise components
`that change
`appreciably in this time interval will be significant. Due
`to the 1/~ dependence of flicker noise,
`these components
`have very small magnitudes and thus are negligible. As a
`result,
`the source-follower
`dimensions
`are dictated only
`by thermal noise requirements.
`Neglecting flicker noise,
`the preamplifier
`noise power density is [5]
`
`input-referred
`
`$=’’’(k)“k’(’rb’’’sw+k)
`‘8’
`
`and base re-
`and rb are the transconductance
`where gmBJT’
`resistance of
`sistance of Q 1 and Q 2, Rsw is the channel
`input switches, and g~Mos is the transconductance
`of M 1
`and M2.
`In this equation the first
`term represents
`shot
`noise in the bipolar pair, while the second term embodies
`the various
`sources of
`thermal noise. For
`this design
`
`~
`
`= 130 I.LVfor a bandwidth of 100 MHz.
`Emitter
`followers Q 3 and Q4 buffer
`the outputs and,
`together with D 1 and D 2, shift
`the output voltage down
`
`D. CMOS Latch
`in-
`is a CMOS latch,
`The last stage of the comparator
`cluded in Fig. 6,
`that
`is used to generate CMOS levels
`from the output of the bipolar
`latch.
`It consists of sense
`transistors M3 and M4, cross-coupled
`devices M5-M 8,
`reset transistors M9 and M 10, and a CMOS clock delay
`inverter G 1. The operation of this latch is based on charge
`sharing between C 1 and the capacitance at the node X2,
`and between C2 and the capacitance
`at
`the node Y2.
`However, C 1 and C2 are not significantly discharged by
`activation of the latch because they are much larger
`than
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 4
`
`

`

`,,,,-———————~+.
`[ “\~~
`----
`-6L:~
`
`-’J=,:,,,,,,l,,,,lM,,
`
`05
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`Fig. 7. Bipolar latch output waveforms (@l and 0, amplitudes not to scale).
`
`Time (nsec)
`
`..-
`
`.=--
`
`---
`
`..........
`\,
`:\
`..”L-- —--
`
`A“
`
`.-. .-..>.;
`
`Vxz
`—
`V“*
`(D1
`---
`.
`.02
`.. ___------
`1
`
`.-
`
`/
`
`o
`
`-1
`
`-5
`
`/
`
`LbLuLlu~
`10
`05
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`Time (nssc)
`
`Fig.8. CMOS latch output waveforms (01 and @2amplitudes not to scale).
`
`the
`5 V) are reduced in these figures. Fig. 7 depicts
`waveforms
`at nodes X 1 and Y1. When 4 I goes high at
`t = 2 ns,
`the preamplifier
`senses the analog inputs ( K.l
`and Vi~2in Fig, 5) and amplifies their difference,
`thus gen-
`erating a differential voltage at X 1 and Y1. At t = 22 ns,
`@2goes low to strobe the bipolar
`latch,
`thereby regener-
`atively amplifying the difference between Vx ~and Vyl.
`Fig. 8 shows the waveforms at the outputs of the CMOS
`latch. As explained previously,
`the CMOS latch is acti-
`vated by a delayed version of @z. The output nodes X2
`and Y2 are initially discharged to V~~. Shortly after +2
`goes low, charge is transferred from nodes Xl and Y1 to
`nodes X2 and Y2. If, for example, Vx 1 < Vyl, then more
`charge is transferred
`to Y2 than X2, and Y2 goes high
`while X2 is regeneratively
`pulled back to V~~.
`The degradation in the high level at Xl and Y1, which
`also appears as the high level of nodes X2 and Y2,
`is
`proportional
`to the ratio of the parasitic
`at X2 and Y2 to
`the coupling capacitors C 1 and C2. For the minimum ge-
`ometry devices used in the latch,
`this degradation is ap-
`proximately 0.8 V.
`
`IV. A SELF-CALIBRATING
`of su-
`the potential
`offer
`While BiCMOS
`technologies
`circuits,
`and
`analog
`digital
`perior
`performance
`in both
`lack the passive
`that
`components
`many
`such technologies
`
`COMPARATOR
`
`CMOS
`
`Vo,
`
`x2
`
`Y2
`
`V02
`
`-+-t
`
`‘z”-::
`
`Fig. 6. Combined circuit of bipolar and CMOS latches.
`
`the voltages at
`at X2 and Y2. As a result,
`the parasitic
`X2 and Y2 closely approach the supply rails.
`The CMOS latch operates as follows.
`In the calibration
`mode, when 02 is high,
`ikf3 and M4 are off, and M9 and
`M 10 discharge X2 and Y2 to V~~. In the comparison
`mode, *2 goes low to strobe the bipolar
`latch and turn off
`M9 and M 10. Then,
`following a delay controlled by C3,
`transistors M3 and M4 turn on, coupling the voltage dif-
`ference between X 1 and Y1 to the sources of M5 and M6
`and initiating regeneration
`at nodes X2 and Y2. The re-
`generation continues until either X2 or Y2 reach the volt-
`age at X 1 or Y1, while the other returns to V~~. Designed
`with short-channel
`devices for a fast response,
`this latch
`may have an input offset as high as 50 mV and thus must
`be strobed only after the bipolar latch has generated a suf-
`ficient voltage difference between X 1 and Y1. This is en-
`sured by setting the switching point of G 1 above – 3 V,
`so that its output does not go low until C3 has charged up
`by at least 2 V. Because C3 is approximately one-fifth the
`size of C 1 and C2, a 2-V change in its voltage corre-
`sponds to a potential difference of at least 200 mV be-
`tween X 1 and Y1.
`Another
`issue in the design of the CMOS latch is the
`disturbance it may cause at the sensitive nodes X 1 and Y1
`before the bipolar latch is strobed.
`In this circuit,
`the only
`disturbance arises from the clock and charge feedthrough
`of M9 and M 10 as they turn off, and this is negligible
`because of the weak capacitive path from X2 and Y2 to
`Xl and Y1.
`In order to prevent degradation of the X 1 and Y1 com-
`mon-mode voltage, M3 and M4, which remain on as long
`as +2 is low, are followed by cross-coupled
`devices M5
`and M6. For example, when X2 is low and Y2 is high
`M5 turns off,
`isolating X 1 from M7, which would
`otherwise discharge X 1 to one PMOS threshold voltage
`above VEE.
`
`E. Simulation Results
`for the
`Figs. 7 and 8 show the simulated waveforms
`two latches. For clarity,
`the amplitudes of @l and @2(=
`
`1920
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 27, NO. 12,DECEMBER
`
`1992
`
`-0.2
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`-0.6
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`
`:\
`____
`...........-.:
`j \,
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`i
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`
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`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 5
`
`

`

`RAZAVI AND WOOLEY:
`
`DESIGN TECHNIQUES
`
`FOR HIGH-SPEED, HIGH-RESOLUTION COMPARATORS
`
`1921
`
`the
`for analog design. On the other hand,
`are essential
`of CMOS technology
`in system design has
`prevalence
`supported the incorporation
`of such components
`in many
`CMOS processes.
`in a fully
`obtainable
`To improve
`the performance
`CMOS comparator,
`offset cancellation
`can be applied to
`both the preamplifier
`and the latch. The CMOS compar-
`ator described
`in this section employs
`a topology that
`achieves complete offset cancellation for both its pream-
`plifier and latch,
`thereby making it possible to achieve
`12-b precision at comparison
`rates as high as 10 MHz
`when implemented in a 1-~m technology.
`
`A. Architecture
`
`Fig. 9 is a simplified block diagram of the CMOS com-
`parator.
`It consists of two transconductance
`amplifiers,
`G~l and G~z, sharing the same output nodes,
`load resis-
`tors R~ ~and R~2, and capacitors C 1 and C2 in a positive
`feedback
`loop around G~2.
`In the offset-cancellation
`mode,
`the inputs of G~l and G~2 are grounded and their
`offsets are amplified and stored on C 1 and C2.
`In the
`comparison mode,
`the inputs are released from ground and
`the input voltage is sensed. This voltage is amplified by
`G~l to establish an imbalance
`at the output nodes A and
`B, and hence at the inputs of G~z, initiating regeneration
`around G,,,2.
`can be viewed as
`of this comparator
`The calibration
`output offset storage applied to both Gn I and G~2, result-
`ing in complete cancellation of their offsets. This topol-
`ogy utilizes the offset-cancelled
`amplifier G~2 for regen-
`eration, whereas
`a
`conventional
`00S
`configuration
`incorporates
`an explicit
`latch that can suffer from large
`input offsets. Thus, neglecting second-order
`effects such
`as mismatch in charge injection from S 5 and S 6, the pro-
`posed topology achieves zero residual offset while retain-
`ing the advantages of 00S.
`the block diagram of
`Owing to several complications,
`Fig. 9 is not practical
`if implemented directly as shown.
`First,
`the feedback capacitors and their parasitic
`load the
`output nodes,
`reducing the speed. Second, because of the
`finite on-resistance
`of S5 and S6,
`the positive feedback
`loop around G~2 is not completely broken in calibration
`mode, making the circuit prone to oscillation. More im-
`portantly, when S5 and S6 turn off to end the calibration,
`any mismatch in their charge injection can trigger a false
`regeneration around G~z. Since the feedback is designed
`for a fast response,
`this regeneration may not be overrid-
`den by small voltages at the input, hence causing a large
`overall
`input-referred
`offset for the comparator.
`Fig. 10
`illustrates
`a modified comparator
`configuration
`that cir-
`cumvents these problems.
`In this circuit, buffers B 1 and
`B2 isolate nodes A and B from the feedback capacitors,
`while switches S7–S 10 disable the feedback loop when
`required. Regeneration begins only after the input voltage
`has been sensed and amplified.
`It should be noted that the
`offsets of B 1 and B2 are also stored on C 1 and C2.
`
`+
`
`1
`
`4cy
`
`Fig.9. CMOS comparator simplified block diagram.
`
`=
`
`S3T
`
`34.
`
`Y
`
`V’”
`~
`
`SI
`
`S2
`
`Gml
`-+
`
`==RLI
`
`R ,.
`
`A
`
`B
`
`B1
`
`c
`II
`
`1
`S9(
`
`a’
`s:
`
`S1o
`
`Q1
`
`l S1,S2,S9,S1OOFF
`l S3-S6 ON
`
`o S1, S2, S5, S6 ON
`l S3, S4, S7-S1OOFF
`
`02
`
`0 S1,S2,s9,S1OON
`c S3-S6OFF
`
`Fig. 10. Modified CMOS comparator block diagram and timing.
`
`B. Circuit Details
`of the topology in Fig. 10 is
`A CMOS implementation
`shown in Fig. 11. In this circuit, differential pairs M 1,
`i142 and M3, M4 constitute amplifiers G~l and G,,,2, re-
`spectively, with source followers M9 and M 10 serving as
`the buffers B 1 and B 2. Transistors M7 and M 8 operate
`as active loads, while M 5 and M6 set the output common-
`mode voltage and control
`the gain [2]. The additional cur-
`rents supplied by M7 and M 8 both decrease the voltage
`drop across M5 and M6 and increase the available gain,
`two important advantages when the circuit must operate
`from a single 5-V supply. Moreover, by boosting the cur-
`rents that charge and discharge nodes A and B, the push–
`pull operation of M3 with M7 and M4 with M 8 improves
`the large-signal
`response in two ways: it increases the out-
`put voltage swing and enhances
`the speed. This can be
`seen by noting that if, for example, node E goes high and
`node F goes low,
`the current
`in M7 is reduced,
`thus al-
`lowing M3 to more rapidly discharge node A to a lower
`voltage, while the current
`in M 8 is increased,
`thereby
`pulling node B more quickly to a higher voltage.
`Since the comparator of Fig. 11 includes calibration of
`both the preamplifier
`and the latch,
`its residual offset
`is
`due primarily to mismatches
`among switches S5-S 10.
`Because of mismatches
`in their dimensions and threshold
`voltages,
`two nominally
`identical MOS devices
`carry
`slightly different charges
`in their
`inversion layers. This
`difference results in charge injection mismatch when the
`two switches
`turn off and charge absorption mismatch
`when they turn on. In the comparator
`circuit, both types
`charge
`injection mismatch
`from
`of mismatch
`exist:
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1008 Page 6
`
`

`

`1922
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL 27, NO
`
`12,DECEMBER
`
`1992
`
`and
`S5-S 8 when they turn off to end the calibration,
`charge absorption mismatch from S 9–S 10 when they turn
`on to establish a positive feedback loop around Gn2.
`Because S5 and S6 discharge their respective nodes to
`the same potential,
`their charge injection mismatch can
`be cancelled by an auxiliary switch placed between nodes
`E and F that turns off a few nanoseconds
`after S5 and S6,
`thereby equalizing the voltages at E and F [6]. With the
`same principle applied to S7 and S 8, the charge absorp-
`tion mismatch between S9 and S 10 becomes the only sig-
`nificant contribution
`to the offset. This offset manifests
`itself when S9 and S 10 turn on, absorbing charge from
`C 1 and C2 into their channels. The charge absorption
`mismatch creates an offset voltage between the gates of
`A43 and M4 that is multiplied by the gain of the M3 and
`M4 pair when it appears at nodes A and B and is divided
`by the gain of the M 1 and M2 pair when referred to the
`main input. The resulting input-referred
`offset is
`
`v~~ “
`
`AQ g.zsd + gm78
`
`y
`
`g,?112
`
`(9)
`
`where AQ is the channel-charge mismatch of S9 and S 10
`when they are on, C = C 1 = C2, and g~34, gfl,j’g,and
`g~12 are the transconductance
`values of differential pairs
`M3-M4, M7-M8,
`and M 1-M2,
`respectively. This equa-
`tion indicates
`that,
`for a given AQ, Vo~ can be reduced
`by: 1) increasing C, which increases the recovery and re-
`generation delays, as well as the area; 2) decreasing gn~q
`+ g~Tg, which is accomplished
`by decreasing 12 and not
`only degrades the regeneration
`speed but also lowers the
`output
`swing; and 3) increasing
`g~l z, which either
`in-
`creases the input capacitance (if M 1 and M2 are widened)
`or limits the input and output swings (if Z1 is increased).
`As a compromise among these trade-offs, C = 0.5 pF and
`
`4+ 14
`
`:
`
`a
`
`v~,
`v
`*JJW
`s,
`hi
`
`01
`.L
`
`‘3
`
`@l F1
`1
`
`34
`
`k
`‘2
`
`v~~
`V,”*
`
`IM1 M2
`
`+ 11
`+
`
`Fig. 11. CMOS comparator circuit diagram.
`
`“3“ EE7V”D
`
`Fig. 12. CMOS comparator output amplifier.
`
`delayed phase of *2 is used to properly time the regen-
`eration. A simpler approach is to employ a nonregenera-
`tive amplifier,
`such as thle one shown in Fig. 12. Since
`the outputs X and Y of the comparator
`track the positive
`supply voltage by I~G~GI + ~Gs9 and I~GS5 [ + vGS10, re-
`spectively,
`the amplifier
`inputs cannot
`simply be refer-
`enced to ground because, under worst-case
`conditions of
`supply and process variations,
`the amplifier may not pro-
`vide rail-to-rail
`swings at its output. By replicating the X
`and Y common-mode
`voltage at the source of M 17, the
`circuit
`in Fig. 12 generates pull-up currents
`in M 13 and
`M 14 that, during reset, are twice the pull-down currents
`in M 11 and M 12 if the latter two are driven from X and
`Y. In this case, V., and V02 closely approach the supply
`rails. Since a single bias network, M 15–M 18, can be used
`for an array of comparators,
`the equivalent power dissi-
`pation of the output amplifier
`remains below 0.5 mW.
`
`C. Simulation Results
`are
`for the CMOS comparator
`Simulated waveforms
`shown in Figs. 13 and 14., wherein the amplitudes of @l
`and ‘$2 ( = 5 V) have been reduced for clarity. Fig. 13
`depicts the waveforms at nodes X and Y. At t = 2 ns, @l
`goes low and the preamplifier
`senses the analog inputs
`(~.l
`and V1.2in Fig. 11), amplifying their difference so
`as to produce a larger differential voltage at nodes X and
`Y. At t = 6 ns, @2goes low to close the positive feedback
`
`gm 12 = Q ( gm34 + gm78)
`design.
`used
`in
`this
`were
`to 00S and 10S
`in contrast
`Equation (9) indicates that,
`configurations,
`the circuit
`in Fig. 11 imposes no con-
`straint between the preamplifier voltage gain and the re-
`sidual offset,
`thus allowing a better optimization
`of the
`load devices for speed and input range.
`in
`Since the flicker noise at the input of the comparator
`Fig. 11 is removed by periodic offset cancellation,
`only
`thermal noise needs to be considered.
`If the noise contri-
`butions of source followers M9 and M 10 and capacitors
`C 1 and C2 are neglected,
`the total