IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 54, NO. 7, JULY 2007
`
`601
`
`Slew-Rate-Controlled Output Driver Having Constant
`Transition Time Over Process, Voltage, Temperature,
`and Output Load Variations
`
`Soon-Kyun Shin, Wang Yu, Young-Hyun Jun, Jae-Whui Kim, Bai-Sun Kong, and Chil-Gee Lee
`
`Abstract—A slew-rate-controlled output driver having a con-
`stant transition time irrespective of environmental variations is
`described in this brief. The proposed output driver employs a
`capacitive feedback between the output and input of the driver
`to allow its transition time independent of process, voltage, tem-
`perature and output load variations. The proposed output driver
`was designed and fabricated using a 0.13- m CMOS process.
`According to our experimental results, the normalized variation
`on transition time of the proposed output driver due to PVT
`variations was improved by 74%–80% as compared to the con-
`ventional output driver. The comparison result also indicates that
`the normalized variation on transition time due to output load
`change from 10 to 100 pF (10 times variation) in typical process,
`voltage and temperature corners was improved by up to 66%.
`Index Terms—Capacitive feedback, constant transition time,
`output driver, slew-rate control.
`
`I. INTRODUCTION
`
`P ROVIDING higher data processing rate and interface
`
`speed is becoming ever more important in proportion to
`the evolution of multimedia environment. Recent high-per-
`formance interfaces like USB and Serial ATA require their
`output drivers to provide a minimum variation of rise and
`fall times over process, voltage, and temperature (PVT) and
`output load variations. For example, the USB interface requires
`high-speed differential signals having matched rise and fall
`times to guarantee the specification of crossover voltage, which
`also determines the margin of setup and hold times. For these
`interfaces, the rise and fall times should be low enough to
`satisfy speed performance. However, low rise and fall times
`can cause side effects such as crosstalk, ringing, reflection, and
`ground and power bounces (di/dt noise) [1] due to the switching
`current traveling through the bonding wire and package pins.
`A signal with fast transition edges has non-negligible high-fre-
`quency components that can cause transmission line effect and
`crosstalk to adjacent lines, causing a line impedance change and
`
`Manuscript received July 29, 2006; revised October 30, 2006. This work was
`supported in part by Korea Science and Engineering Foundation (R01-2006-
`000-11296-0), and IC Design Education Center. This paper was recommended
`by Associate Editor E. Alarcon.
`S.-K. Shin was with the School of Information and Communication Engi-
`neering, Sungkyunkwan University, Gyunggi-do 440-746, Korea. He is now
`with the Semiconductor Business, Samsung Electronics, Gyunggi-do 446-711,
`Korea.
`W. Yu, Y.-H. Jun, and J.-W. Kim are with Semiconductor Business, Samsung
`Electronics, Gyunggi-do 446-711, Korea.
`B.-S. Kong and C.-G. Lee are with the School of Information and Commu-
`nication Engineering, Sungkyunkwan University, Gyunggi-do 440-746, Korea
`(e-mail: bskong@skku.edu).
`Digital Object Identifier 10.1109/TCSII.2007.895314
`
`Fig. 1. Conventional output driver.
`
`a skew on the data. To solve these problems, a longer transition
`time is preferred as far as the specification is satisfied.
`Several studies on controlling the slew rate of an output
`driver have focused on various methods using analog and
`digital schemes. An analog scheme employed a compensa-
`tion device relying on a known external resistor to generate
`a slew-rate compensation voltage [2]. However, this scheme
`tends to be sensitive to noise when the voltage travels a long dis-
`tance. A digital scheme used the calibration of output driver’s
`impedance by selecting an optimal number of transistors over
`PVT variation, but it shows a discrete impedance change [3]. A
`capacitive feedback scheme was also used, in which the slew
`rate was well controlled for various output load conditions,
`but the scheme still had a relatively large slew-rate change due
`to variation over PVT conditions [4]. Frequency-based com-
`pensation schemes provided excellent slew-rate compensation
`without the external resistor, but they need a phase-locked loop
`(PLL) for bias block [5], [6]. A current control scheme using
`proper bias voltages for pre-driver and main driver was also
`used for achieving a constant slew rate, but this approach shows
`a dependency according to output load variation [7]. Fig. 1
`shows a conventional output driver [8] which adopts the method
`of adding delay in each of the output transistors to increase
`transition time and reduce the amount of fast switching current.
`But, the circuit has the drawback of inability to compensate the
`PVT variations.
`This brief proposes a novel output driver having the char-
`acteristic of very low variation on transition time over PVT
`and output load variations [9]. Section II describes the struc-
`ture and operation of the proposed output driver. Section III
`presents simulation and experimental results to assess the per-
`formance of the proposed driver. Finally, we draw our conclu-
`sions in Section IV.
`
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`
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`602
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`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRES BRIEFS, VOL. 54, N0. 7, JULY 2007
`
`MD1
`
`VDAD
`
`PAD
`
`M02
`
`
`
`Control Logic
`
`Tri-Srate
`
`Fig. 2. Block diagram of proposed output driver.
`
`M3
`
`I'M:
`
`Voltage
`
`Roleronee
`
`Pig. 3. Current bias generator.
`
`11. PROPOSED OUTPUT DRIVER
`
`Fig. 2 shows the block diagram of the proposed output driver
`composed of a current bias generator, a tri-state control logic,
`pre-drivers, and main drivers. It has two main drivers to support
`differential signaling and generates four reference currents in
`the bias current generator to be fed into the pre-drivers and main
`drivers. Fig. 3 shows the bias current generator for obtaining the
`bias current for the output driver. Bias current I131AS generated
`in this block is represented as
`
` VREF
`IBIAS = R1
`
`(1)
`
`where Vmgp is the reference voltage generated from the voltage
`generator. As explained later, the amount of this bias current
`determines the slew rate of the main driver to provide constant
`rising and falling transition times of the output driver. For this to
`be achieved, VREF is made to be independent of temperature and
`process conditions to provide a uniform transition time irrespec-
`tive of these variations. The reference voltage is also made to
`be proportional to the supply voltage to allow a constant transi-
`tion time irrespective of variation on voltage swing. To adapt the
`transition time for different specifications of other applications
`and to provide an independency of transition time on resistor
`variation, R1 can be trimmed or implemented off-chip. Fig. 4
`shows the proposed output driver consisting of a pre-driver and
`a main driver. The pre-driver has constant current sources, [I
`and I2, and transistors, M1, M2, M3, and M4, to control the op-
`eration of main driver transistors, MD] and MD2. These main
`driver transistors are large for efficient driving of heavy capac-
`itive output load. Feedka capacitor Cf connects the output
`node to one of the two gate terminals of the main driver tran-
`sistors using switches 81 and $2. This capacitor provides a re-
`quired amount of current to detemrine the V235 of the driver tran-
`sistor to allow the circuit to have a proper slew rate to provide a
`constant transition time during transition period.
`
`
`
`Fig. 5. Simulation result of internal node.
`
`For a rising transition of PAD, M3, and M4 are turned OH
`and on, respectively, with switch 82 off, allowing MD2 to be
`completely off. M1 and M2 are turned off and on, respectively,
`
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`

`

`SHIN et al.: SLEW-RATE-CONTROLLB) OUTPUT DRIVER
`
`603
`
`
`
`Fig. 6. Simulation results for output waveforms over PVT variations. (Each figure contains a collection of waveforms obtained at slow, typical, fast process corners
`with the temperature of —.3 3 ° C and — 1 2 3 ° C.): The conventional driver with the supply voltage of (a) 3.0 V, (b) 3.3 V, and (c) 3.6 V. The proposed driver with
`the supply voltage of (d) 3.0 V, (e) 3.3 V, and (f) 3.6 V.
`
`with S] on. Then, PG begins to fall from Vm) by the current sink
`of I1 . When PG reaches the voltage level down to “VDD'VIP,”
`where VTP is the threshold voltage of pMOS transistor, MDl
`turns on and PAD begins to rise. At this time, current '1'.(,1 through
`Cf begins to flow according to
`
`32 on. Then, NG begins to rise from the ground by the current
`source of 12. After NG reaches the voltage of “l/ZrN” which is
`the threshold voltage of nMOS transistor, MD2 turns on and
`PAD begins to fall. At this time, current ‘icg through Cf begins
`to flow according to
`
`—.
`-
`1C1 : (if
`
`
`({‘UPAD
`(it
`
`(2)
`
`‘i-c: = Cf
`
`
`If? ’I’AD
`(it
`
`(3)
`
`When the slew rate of the output is such that id becomes
`equal to 11, PG holds its voltage since the sinking and sourcing
`currents are identical, allowing a constant rise time of the
`output until the end of the transition. When ‘17,,1 happens to be
`larger (smaller) than I 1 due to higher (lower) rise time at the
`output, possibly caused by variations on process, temperature
`and output load, PG rises (falls) to decrease (increase) the
`output slew rate until the output provides a target rise time. If
`there is a change on the supply voltage, I1 follows the change
`proportionally and adjust the voltage level of PG to make the
`rise time constant irrespective of the variation on voltage swing.
`After the completion of the transition, PG goes to the ground
`and turns MDl fully on.
`The falling procedure of the output driver is similar to the
`rising one. That is, when PAD falls, M1 is on and M2 is off
`with 81 off, letting MDl off. M3 goes on and M4 goes off with
`
`When id; is equal to 12, NC holds its voltage as the sinking
`and sourcing currents are identical, allowing a constant fall time
`of the output until the end of the transition. When 'ipg happens
`to be different from 12 due to variations on process, voltage,
`temperature and output load, the voltage level of NC is adjusted
`by the same procedure as above to make the fall time constant.
`After the completion of the transition, NG goes to VDD and turns
`MD2 fully on.
`By combining (l) and (3), the slew rate SR of the output of
`the proposed driver can be written as
`
`—
`SR —
`
`
`d’UPAD
`ice
`—
`—
`(ll-
`Cf
`
`k“ [BIAS
`k- vamp
`— — —
`Cf
`Rle
`
`4
`( )
`
`where k is the proportionality factor between 113145 and I-_>.
`Then, the transition time than of the output, which is measured
`
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`

`

`604
`
`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRIBS BRIEi'S, VOL. 54, N0. 7, JULY 2007
`
`Fig. 7. Simulation results with the output load ranging from 10 to 100 pF. (a) Main driver output and (b) the pre-driver output for the conventional driver. (c) Main
`driver output and (d) predriver output for proposed driver.
`
`601
`
`
`Driver
`
`between 10% and 90% of overall voltage swing, can be repre-
`sented as
`
`
`. l/rswiw
`, m“ = .
`t.
`0 8 SR
`
`,
`
`1[DD
`-
`1' —.
`= .’
`,
`0 5121(ka imp
`
`5
`( )
`
`As shown in (5), because VREF follows the variation on VDD
`and is not influenced by other variations as mentioned earlier, a
`proper selection of CI whose Size is sufficiently larger than the
`parasitic capacitance and a proper trimming of R1 to provide
`a target transition time allow uniform transition times of the
`output regardless of environmental variations.
`
`III. SIMULATION AND MEASUREMENT RESULTS
`
`To verify the performance, the proposed output driver was
`designed and fabricated using a 0.13-/1.m CMOS process tech-
`nology. Nominal threshold voltages of p- and n-type transistors
`in this technology are 0.52 and 0.55 V, respectively. Fig. 5 de-
`picts the simulated waveforms for the operation of the proposed
`output driver, which was obtained using typical process parame-
`ters at the temperature of 25 °C with the supply voltage of 3.3 V
`using the load capacitance of 50 pF. As Shown in the figure,
`nodes NG and PG temporarily stay in the middle during the tran-
`sition period. Fig. 6 compares the simulation results for output
`transitions of the conventional and proposed output drivers for
`several different PVT comers. The supply voltage for these sim-
`ulations was varied from 3 to 3.6 V with temperature ranging
`from —55 to 125 °C at typical, fast and slow process comers.
`As shown in this figure, the proposed driver significantly im-
`proves the uniforrnity of transition time regardless of PVT varia-
`tions as compared to the conventional driver. Fig. 7 summarizes
`the simulation results for the output transition waveforms of the
`conventional and proposed drivers for different output load con-
`ditions. The output capacitive load value was varied ten times
`
`Level Shifter
`
`Current Bias
`
`Control Lo ‘c
`
`Pie-Driver
`
`.
`
`P'Q-Drlvot
`
`Output
`
`Fig. 8. Microphotograph of the test chip.
`
`from 10 to 100 pF with typical process parameters and supply
`voltage at room temperature. As shown in the figure, the voltage
`levels of PG and NG for the proposed output driver are adjusted
`in proportion to the amount of output load to provide a reduced
`variation of output transition time for a wide range of output
`loads. Fig. 8 Shows the microphotograph of test chip, whose size
`iS 280 X 225 pm2 including PAD, and Fig. 9 depicts the mea-
`sured waveforms, Showing almost the same rise and fall times
`for each of the output nodes. Table I summarizes the variation of
`transition time due to PVT variations, while Table H compares
`the variation due to output load variation. The fastest (slowest)
`rise and fall times of each driver were obtained when the supply
`voltage is 3.6 V (3.0 V) at the temperature of —55°C (125 °C),
`at fast (Slow) process comer. The term variation in each table
`refers to the difference between the slowest and fastest rise (fall)
`times of each driver, and the normalized variation was obtained
`
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`
`

`

`SHIN et al.: SLEW-RATE-CONTROLLED OUTPUT DRIVER
`
`605
`
`variation due to PVT variation as compared to that of the con-
`ventional driver. The normalized variation on transition time
`due to output load variation is also reduced by 52%–66% for
`the proposed driver as compared to the conventional driver.
`
`IV. CONCLUSION
`In this brief, a slew rate-controlled output driver using ca-
`pacitor feedback was proposed. The output driver shows a very
`low variation of transition time over PVT variations and over
`a wide range of capacitive output load. The test results show
`that the proposed output driver is well suited for applications re-
`quiring constant transition time. The proposed output driver was
`successfully applied to the design of an interface for USB that
`requires a uniform transition time regardless of environmental
`variations.
`
`REFERENCES
`[1] G. A. Katopis, “Delta-I noise specification for a high-performance
`computing machine,” Proc. IEEE, vol. 73, no. 9, pp. 1405–1415, Sep.
`1985.
`[2] R. Senthinathan, G. Tubbs, and M. Schuelein, “Negative feedback
`influence on simultaneous switching CMOS outputs,” in Proc. IEEE
`Custom Integr. Circuits Conf., May 1988, pp. 5.4.1–4.
`[3] T. J. Gabara and S. C. Knauer, “Digitally adjustable resistors in CMOS
`for high-performance applications,” IEEE J. Solid-State Circuits, vol.
`27, no. 8, pp. 1176–1185, Aug. 1992.
`[4] F. Garcia, P. Coll, and D. Auvergne, “Design of a slew-rate-controlled
`output driver,” in Proc. ASIC Conf., 1998, pp. 147–150.
`[5] T. Shirotory and K. Nogamir, “PLL based impedance control output
`buffer,” in Proc. Symp. VLSI Circuits, 1991, pp. 49–50.
`[6] S.-K. Shin, S.-M. Jung, J.-H. Soo, M.-L. Ko, and J.-W. Kim, “A slew-
`rate-controlled output driver using PLL as compensation circuit,” IEEE
`J. Solid-State Circuits, vol. 38, no. 7, pp. 1227–1233, Jul. 2003.
`[7] S.-W. Choi and H.-J. Park, “A PVT-insensitive CMOS output driver
`with constant slew rate,” in Proc. IEEE Asia-Pacific Conf. Advanced
`Syst. Integr. Circuits, Aug. 2004, pp. 116–119.
`[8] R. Senthinathan and J. L. Prince, “Application specific output drivers
`to reduce SSN,” in Simultaneous Switching Noise of CMOS Devices
`and Systems. Boston, MA: Kluwer Academic, 1994, ch. 7, p. 113.
`[9] S.-K. Shin, W. Yu, B.-S. Kong, C.-G. Lee, Y.-H. Jun, and J.-W. Kim,
`“A slew rate-controlled output driver having a constant transition time
`over the variations of process, voltage and temperature,” in Proc. IEEE
`Custom Integr. Circuits Conf. (CICC), Sep. 2005, pp. 231–234.
`
`Fig. 9. Measured waveforms at room temperature with 50-pF output load and
`3.3-V supply voltage.
`
`TABLE I
`SUMMARY OF TRANSITION TIME OVER PVT VARIATIONS
`
`TABLE II
`SUMMARY OF TRANSITION TIME OVER THE VARIATION OF OUTPUT LOAD
`RANGING FROM 10 TO 100 PF AT A TYPICAL PVT CONDITION
`
`by dividing the variation by nominal rise (fall) time of each
`driver. As shown in Table I, the proposed output driver achieves
`74%–80% improvements in terms of normalized transition time
`
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`