`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`_____________________________________
`
`Case No. IPR2020-01219
`Patent No. 8,487,659
`____________________________________
`PATENT OWNER’S RESPONSE PURSUANT TO
`37 C.F.R. § 42.107
`
`
`
`
`
`
`
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`TABLE OF CONTENTS
`
`2. 
`
`Page
`Introduction ...................................................................................................... 1 
`I. 
`The ’659 Patent ................................................................................................ 4 
`II. 
`III.  The ’659 Patent Prosecution history ................................................................ 9 
`IV.  Claim Construction ........................................................................................ 10 
`V.  Yoshioka fails to anticipate or render obvious the challenged claims
`(Grounds 1-5) ................................................................................................. 10 
`A.  Yoshioka Is Not Prior Art ................................................................... 11 
`1. 
`The ’659 Invention Was Conceived Prior to Yoshioka’s
`Publication Date ........................................................................ 12 
`The Inventor Exercised Diligence From Prior to Yoshioka’s
`Publication Date to Actual Reduction to Practice of a Chip
`Incorporating the Invention ....................................................... 34 
`B.  Yoshioka .............................................................................................. 40 
`1. 
`Yoshioka Overview .................................................................. 41 
`C.  Yoshioka Fails to Teach an “Adaptive Delay Device . . . Configured
`to Respond Inversely to the Response of Other Circuit Components
`Forming the [SAR ADC]” (Claims 5-8 - Grounds 1 and 4) ............... 47 
`1. 
`Yoshioka Does Not Expressly Teach Responding Inversely to
`the Response of Other Circuit Components ............................. 49 
`Yoshioka Does Not Inherently Teach Responding Inversely to
`the Response of Other Circuit Components ............................. 52 
`Patent Owner’s Responses to Issues Raised by the Board in its
`Decision on Institution .............................................................. 55 
`D.  Yoshioka Fails to Teach a Circuit in Which “Delays Between the
`State Change of the Input Signal and the Generated Output Voltage
`Vary Inversely in Response to PVT Effects on Other Components of
`the Integrated Circuit” (Claims 9 and 10 - Grounds 1 and 2) ............. 58 
`
`2. 
`
`3. 
`
`
`
`- i -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`2. 
`
`3. 
`
`E.  Yoshioka in Combination with AAPA Fails to Teach or Disclose a
`“Delay Element Having a Circuit Structure to Adaptively Increase Or
`Decrease Delay Propagation of the First Control Signal In a Manner
`That Counteracts PVT Effects Present in Other Components of the
`Comparator” (Claims 1-4 - Grounds 3 and 5) ..................................... 58 
`1. 
`The Combination Fails to Teach or Suggest the Elements of
`Claim 1 ...................................................................................... 58 
`The Petition Fails to Establish a Motivation to Combine
`Yoshioka with AAPA ............................................................... 59 
`VI.  Ajit fails to anticipate or render obvious the challenged claims (grounds 6
`and 7) ............................................................................................................. 62 
`A.  Ajit ....................................................................................................... 63 
`B.  Ajit Fails to Teach a Circuit in Which “Delays Between the State
`Change of the Input Signal and the Generated Output Voltage Vary
`Inversely in Response to PVT Effects on Other Components of the
`Integrated Circuit” (Claim 9 to 11 - Ground 6) .................................. 64 
`1. 
`Ajit Does Not Adjust a Delay as Required by the Claims ........ 65 
`2. 
`Petitioner’s Argument Is Based on Inherency, But Petitioner
`Fails to Establish Ajit Necessarily Operates As Alleged .......... 67 
`Petitioner’s Expert Declaration Is Unsupported, Fails to
`Identify Key Underlying Assumptions, and Is Entitled to No
`Weight ....................................................................................... 68 
`Petitioner’s Sketches Are Critically Flawed and Show No
`Delay When Corrected .............................................................. 74 
`Accurate Simulations Show that Ajit Does Not Inherently
`Adjust Delay Inversely In Response to PVT Effects on Other
`Components .............................................................................. 80 
`C.  Ajit in Combination with AAPA Fails to Teach or Disclose the
`Elements of Claims 1 and 5 (Ground 7) .............................................. 86 
`1. 
`Ajit Fails to Teach or Disclose the Elements of Claim 1 ......... 86 
`2. 
`The Petition Fails to Establish a Motivation to Combine Ajit
`with AAPA ................................................................................ 87 
`
`4. 
`
`5. 
`
`
`
`- ii -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`D.  Ajit in Combination with AAPA Fails to Teach or Disclose the
`Elements of Claim 5 (Ground 7) ......................................................... 89 
`VII.  Conclusion ..................................................................................................... 90 
`
`
`
`
`- iii -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`Patent Owner Analog Devices, Inc. (“Analog”) submits the following Patent
`
`Owner’s Response (“POR”) to the Petition filed by Xilinx, Inc. and Xilinx Asia
`
`Pacific Pte. Ltd. (“Petitioner”) requesting inter partes review of claims 1–11 of
`
`U.S. Patent No. 8,487,659. Ex. 1001 (“the ’659 patent”).
`
`I.
`
`INTRODUCTION
`The ’659 patent discloses a novel, non-obvious delay circuit that adjusts its
`
`own timing adaptively to vary inversely in response to process, voltage, and
`
`temperature (“PVT”) effects on components other than the delay circuit. As the
`
`Patent Office recognized in granting the patent, this was a significant improvement
`
`over earlier PVT compensation techniques that sought to keep the delay of the
`
`delay circuit constant despite the effect of PVT variations on the circuit itself (to
`
`act as if unaffected by PVT).
`
`Petitioner’s primary reference, Yoshioka (Ex. 1004), describes a successive
`
`approximation (SAR) analog to digital converter (ADC) that includes an internal
`
`clock generator, having a delay controller, that monitors and counteracts the effects
`
`of PVT on the delay controller itself. Petitioner’s reliance on Yoshioka fails for
`
`two separate and independent reasons. First, Yoshioka is not prior art to the ‘659
`
`patent. Instead, Analog’s internal records confirm that the ’659 invention was
`
`conceived before Yoshioka’s publication and diligently reduced to practice. Ex.
`
`2044, ¶ 21.
`
`
`
`- 1 -
`
`

`

` Second, Yoshioka lacks the critical feature of the challenged claims that
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`secured their allowance—a delay element that adjusts its delay inversely in
`
`response to the PVT effects on components other than the delay element. Instead,
`
`Yoshioka explicitly states that the delay, Td, generated by the alleged delay
`
`element itself “has a large PVT variation,” and that Yoshioka’s alleged delay
`
`element monitors and adjusts for the PVT effects on Td itself. Yoshioka never
`
`describes how PVT effects would impact the other components of Yoshioka’s
`
`system, or adjusting Td in response to such PVT effects. Moreover, Petitioner’s
`
`allegation that Yoshioka adjusts the delay Td inversely to the PVT effects on other
`
`circuits is pure speculation – Petitioner’s own expert admits that he has performed
`
`no analysis or simulation of Yoshioka’s comparator circuit and that he has no
`
`opinion regarding whether the delay through Yoshioka’s comparator circuit would
`
`rise or fall in response to PVT effects. Petitioner has therefore provided no
`
`evidence and has no basis to allege that Yoshioka’s delay controller would
`
`adaptively increase or decrease its delay inversely to, or in a manner that
`
`counteracts, the PVT effects on other components of the system. Indeed, as
`
`explained below, given the purpose and position of Yoshioka’s clock generator
`
`relative to other circuits in the SAR ADC, adjusting the delay inversely in response
`
`to PVT effects on the other components would actually have the opposite effect of
`
`the ’659 patent, reducing the performance of Yoshioka’s system, thus
`
`
`
`- 2 -
`
`

`

`demonstrating that Yoshioka is not reasonably understood as implicitly or
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`inherently practicing or suggesting the invention. Ex. 2044, ¶ 35.
`
`Petitioner’s second reference, Ajit (Ex. 1005), fares no better. Ajit teaches a
`
`timing delay circuit that seeks to adapt the slew-rate (the change in voltage relative
`
`to time) of an output signal, to counteract the PVT effects on an input signal. Ajit
`
`does not teach or suggest adapting the delay through the circuit at all, much less
`
`inversely to the PVT effects on components other than a delay circuit. In fact,
`
`detailed simulations of Ajit’s circuit show that it does not inherently adapt a delay
`
`inversely to PVT effects on other circuits even as a side effect of its adjustments to
`
`the slew rate. Ex. 2044, ¶ 72.
`
`Lacking any express disclosure in Ajit even remotely suggesting adaptive
`
`delay as claimed, the Petitioner relies upon its expert’s conclusory assertions about
`
`Ajit’s operation. However, Petitioner’s conclusions are based on imprecise and
`
`incorrect waveforms “sketched” by its expert, who fails to provide the factual
`
`underpinnings and substantiation of the sketches. Given these deficiencies, the
`
`declaration is entitled to no weight. See, e.g., Patent Trial and Appeal Board
`
`Consolidated Trial Practice Guide 36 (Nov. 2019). Moreover, Patent Owner
`
`demonstrates through equations and simulations that Petitioner’s sketched
`
`waveforms include a critical error that lies at the root of Petitioner’s incorrect
`
`conclusion that Ajit adapts the circuit delay inversely to the PVT effects on other
`
`
`
`- 3 -
`
`

`

`components. Once corrected, Petitioner’s sketches would actually show that Ajit
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`does not adapt the delay inversely as required by the claims. Ex. 2044, ¶ 72.
`
`II. THE ’659 PATENT
`The ’659 patent relates to a delay circuit that improves performance by
`
`adaptively responding to process, voltage, and temperature variations experienced
`
`by adjacent circuitry. See Ex. 1001, 1:5-8, 1:61-2:5. As the ’659 patent explains,
`
`the operating speed of digital logic and switches varies in response to variations in
`
`the supply voltage or temperature, or fabrication process variations across different
`
`manufacturing lots of integrated chips. Id., 1:40-46. The ’659 patent teaches that
`
`one can improve the overall performance of a circuit, such as a comparator, by
`
`causing the delay element of the circuit to respond inversely with respect to the
`
`PVT impacts on other elements of the circuit. Id., 1:61-2:5; Ex. 2044, ¶ 11.
`
`Figure 1 of the patent provides an illustration of a prior art comparator. Ex.
`
`1001, 2:9-10.
`
`
`
`- 4 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`
`
`Preamplifier 123 (orange) receives an input signal “IN”, e.g., the signal
`
`difference between an analog input signal and a digital-to-analog converter
`
`(“DAC”) output. That signal is amplified and sent to latch 127 (green). Typically,
`
`preamplifier 123 will require a certain amount of time to amplify its input. See id.,
`
`1:24-37. To provide preamplifier 123 with sufficient time to amplify its input
`
`signal before it is latched, the comparator implements delay 125 (yellow). Id.,
`
`1:24-34. A RESET signal, which initiates the preamplification operation, is input
`
`simultaneously into preamplifier 123 and delay 125. Id. The corresponding
`
`delayed RESET signal, DEL_RESET, is provided to latch 127, which causes latch
`
`
`
`- 5 -
`
`

`

`127 to latch the output of preamplifier 123 and allow the comparator to compare
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`the amplified output of preamplifier 123 to the reference voltage. Id; Ex. 2044, ¶
`
`13.
`
`The overall time to complete a comparison operation is the sum of the delays
`
`through the preamplifier and the latch. And, like many circuits, the speed of each
`
`of these components is dictated by the operating speed of their individual circuit
`
`elements (e.g., transistors and capacitors), which may vary in response to PVT
`
`conditions. Ex. 2044, ¶ 14.
`
`In the prior art, an increase in voltage or decrease in temperature may cause
`
`the speed of all three components to increase. Such increased speed could reduce
`
`the time in which the comparison is done. However, this would not improve the
`
`performance of the comparator because when the comparator is part of a larger
`
`system with a fixed sampling rate, the fixed sampling rate locks the overall
`
`performance at a predefined rate regardless of the speed of the individual
`
`components. Ex.1001, 1:47-2:5; Ex. 2044, ¶ 15.
`
`Inventor Ronald Kapusta realized that, if PVT effects cause the preamplifier
`
`and latch components of the comparator to operate faster, one could
`
`advantageously exploit this situation to improve performance. In particular, he
`
`realized that when the preamplifier and latch operate faster, one could increase the
`
`delay between the preamplifier and latch, to provide additional time for the
`
`
`
`- 6 -
`
`

`

`preamplifier to amplify its input signal. Giving additional time to the preamplifier
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`improves performance, e.g., increases the signal-to-noise ratio or allows the circuit
`
`to reduce its power requirements. See Ex. 1001, 1:61-2:5. He accordingly
`
`invented an adaptive delay element that modifies the delay inversely to the PVT
`
`effects on other components—the preamplifier and latch components of the
`
`comparator. Mr. Kapusta’s approach exploits the benefit of the increased speed
`
`arising from PVT effects by obtaining higher performance in the form of improved
`
`accuracy. Ex. 2044, ¶ 16.
`
`Figure 3 of the ’659 patent provides an example of the invention, showing a
`
`comparator that includes a preamplifier 310, latch 320, and adaptive (as opposed
`
`to fixed) delay element 330 (depicted in more detail as comprising elements 331,
`
`333, 335, and 337). Ex. 2044, ¶ 17.
`
`
`
`- 7 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`
`
`If the preamplifier and/or latch circuit(s) speed up because of PVT effects,
`
`the adaptive delay circuit (yellow) varies inversely and slows down. Ex. 1001,
`
`1:61-2:5. As the patent explains, adapting the delay inversely provides the
`
`preamplifier more time to operate, which improves the signal-to-noise ratio and
`
`accuracy of an ADC employing such a comparator. Id. Rather than merely
`
`compensating for PVT effects, such as a delay element that provides a fixed delay
`
`
`
`- 8 -
`
`

`

`regardless of PVT effects on the delay element, the ’659 patent’s approach
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`provides an adaptive delay that responds inversely to the effect PVT has on
`
`components other than the delay circuit (in the example in Figure 3, the
`
`preamplifier 310 and latch 320). Id.; see also id., 2:29-39. This approach results
`
`in a delay that varies and, unlike the prior art approaches, does not remain constant.
`
`Ex. 2044, ¶ 18.
`
`This counter-intuitive and innovative concept is reflected in each of the
`
`independent claims. For example, claim 1 recites a delay element that is designed
`
`to “adaptively increase or decrease delay propagation of the first control signal in a
`
`manner that counteracts PVT effects present in other components of the
`
`comparator.” Likewise, claim 5 recites an adaptive delay that is designed to
`
`“respond inversely to the response of other circuit components forming the
`
`successive approximation register analog-to-digital converter, and output the
`
`control signal to the comparator based on the inverse response of the adaptive
`
`delay device.” Furthermore, claim 9 recites a circuit in which “delays between the
`
`state change of the input signal and the generated output voltage vary inversely in
`
`response to PVT effects on other components of the integrated circuit.” Ex. 2044,
`
`¶ 19.
`
`III. THE ’659 PATENT PROSECUTION HISTORY
`
`
`
`- 9 -
`
`

`

`The innovative concepts introduced in the ’659 patent were acknowledged
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`by the Patent Office during the prosecution of the patent. The Patent Office
`
`initially cited U.S. Patent No. 8,063,675 to Igarashi (Ex. 2003) against present
`
`claims 1, 5, and 9 of the ’659 patent. Non-Final Rejection, dated November 20,
`
`2012, p. 3 (Ex. 1003, 67).
`
`Patentee successfully distinguished Igarashi, explaining that it “provided a
`
`delay circuit that has a delay time period independent of a power supply voltage . .
`
`. .” Ex. 2003, 1:66-2:4. In response, the Patent Office issued a Notice of
`
`Allowance. See Notice of Allowance, dated March 18, 2013, p. 2 (Ex. 1003, 105).
`
`IV. CLAIM CONSTRUCTION
`Petitioner has not proposed any claim constructions. Patent Owner agrees
`
`that the terms of the challenged claims can be understood based on their plain and
`
`ordinary meanings.
`
`V. YOSHIOKA FAILS TO ANTICIPATE OR RENDER OBVIOUS THE
`CHALLENGED CLAIMS (GROUNDS 1-5)
`Petitioner has not and cannot meet its burden of establishing that the
`
`Yoshioka grounds invalidate the claims for two separate and independent reasons.
`
`First, Yoshioka is not prior art to the ’659 patent because, as demonstrated below,
`
`the inventor of the ’659 patent, Ronald Kapusta, conceived of the invention prior to
`
`Yoshioka’s publication date and diligently reduced it to practice. Second, even
`
`assuming, arguendo, that Yoshioka were prior art, it would not anticipate or render
`- 10 -
`
`
`
`

`

`obvious the challenged claims because it does not teach a critical element of the
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`claim – a delay circuit configured to respond inversely to the response of other
`
`circuits to PVT effects. Yoshioka accordingly does not invalidate any of the
`
`claims challenged in Grounds 1 through 5.
`
`A. Yoshioka Is Not Prior Art
`Yoshioka, entitled “A 10-b 50-MS/s 802-µW SAR ADC With On-Chip
`
`Digital Calibration,” was published on November 9, 2010. Yoshioka is not prior
`
`art because the invention claimed in the ’659 patent was conceived before
`
`Yoshioka’s publication date and diligently reduced to practice from a point in time
`
`prior to Yoshioka’s publication date. Conception is corroborated by the inventor’s
`
`schematics and design review documents, either of which suffices to establish prior
`
`invention and all of which occurred before November 9, 2010. The actual
`
`reduction to practice of the invention was a chip that included the inventive
`
`comparator, which was received by Analog no later than January 13, 2010, and
`
`confirmed to work no later than January 31, 2011. The inventor’s diligence was
`
`reasonable and consistent with normal industry practice. Ex. 2044, ¶¶ 23-34.
`
`As established below, Mr. Kapusta conceived of the claimed invention no
`
`later than October 29, 2010. On July 20, 2010, Mr. Kapusta generated an internal
`
`“Design Review” document showing the exact circuits claimed in the ’659 patent.
`
`Mr. Kapusta then continued to work on reducing his invention to practice, and on
`
`
`
`- 11 -
`
`

`

`October 29, 2010, ten days prior to Yoshioka’s date, he uploaded onto an Analog
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`server the schematics depicting the same circuits previously shown in the Design
`
`Review. On November 9, 2010, Analog generated a corresponding “tapeout” file
`
`containing the chip design, which can be used by chip manufacturers to
`
`manufacture an actual working semiconductor chip. Analog sent the tapeout file to
`
`Taiwan Semiconductor Manufacturing Co. (“TSMC”), a chip manufacturer, on
`
`November 9, 2010, and received chips embodying the invention no later than
`
`January 13, 2010. Analog tested the received chips and, no later than January 31,
`
`2011, confirmed that the comparator circuits embodied on the chips worked as
`
`expected and for their intended purpose. Ex. 2043, ¶¶ 55-64.
`
`1.
`
`The ’659 Invention Was Conceived Prior to Yoshioka’s
`Publication Date
`Mr. Kapusta conceived of the claimed invention before November 9, 2010.
`
`On July 20, 2010, he authored a Design Review document that describes “the main
`
`comparator for the SAR ADC in the Gecko project.” (“Design Review” or “DR”).
`
`Ex. 2006, p. 1. Design Reviews are typically prepared at Analog during chip
`
`design, and are presented to a team of engineers for review. Ex. 2043, ¶ 9. Figure
`
`1 (below) of the Design Review describes the components of a comparator,
`
`including a preamplifier and a latch, exactly as described in the ’659 patent. Ex.
`
`2006, p. 3; Ex. 2044, ¶ 23.
`
`
`
`- 12 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`
`
`The Design Review also describes a timer circuit for generating a control
`
`signal for the latch and explains the operation of the timer circuit, stating:
`
`“Basically, we want the timer circuit to be faster when the conditions are slow (low
`
`supply, slow devices, etc.), since it is in those corners that we get the most benefit
`
`from spending more time with the latch in a high current, fast state.” Ex. 2006, p.
`
`3. The Design Review also includes simulations of the proposed timer circuit,
`
`showing that it works exactly as designed. Below is a chart of the results of the
`
`simulations, showing, e.g., that the circuit performs faster when operating under
`
`lower supply voltages (e.g., green highlight), and slower when operating under
`
`higher supply voltages (e.g., red highlight). Ex. 2044, ¶ 23.
`
`
`
`- 13 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`
`
`Ex. 2006, p. 32.
`
`The comparator performance is exactly the opposite of the response of the
`
`latch to different voltage levels, as shown by Table 6 of the Design Review. Table
`
`6, below, shows the regeneration time constant “tau” of the comparator latch - a
`
`small value of tau results in a fast decision, whereas a large value of tau results in a
`
`slow decision. Table 6 shows that, when the process and temperature are kept
`
`constant, higher supply voltages (e.g., red highlight) result in faster performance
`
`(i.e., lower tau) than lower voltages (e.g., green highlight). This response to
`
`
`
`- 14 -
`
`

`

`changes in voltage is the inverse of how the timer circuits responds. Ex. 2044, ¶¶
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`24-25.
`
`
`
`The Design Review further depicts the exact circuits shown as Figures 4 and
`
`6 of the ’659 patent. Ex. 2006, pp. 10-11; see also Ex. 2044, ¶ 26; Ex. 2043, ¶¶
`
`17, 26. These circuits, shown below side-by-side with corresponding Figures 4
`
`and 61 and shaded to show corresponding circuit elements2, establish that Mr.
`
`Kapusta had conceived of his invention as early as July 20, 2010, the date of the
`
`Design Review. Ex. 2044, ¶ 27.
`
`
`
`
`1 Figure 6 has been modified to show only the circuit components comprising
`
`PTAT Current Source 630.
`
`2 The magenta pair of transistors in Figure 6 of the ’659 patent matches transistors
`
`shown in Figures 8 and 9 of the Design Review.
`
`
`
`- 15 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`Figure 4 of ’659 patent
`
`
`
`Figure 8 of Design Review
`
`
`
`Figure 6 of ’659 patent
`
`Figures 8 and 9 of Design Review
`- 16 -
`
`
`
`
`
`
`
`
`
`
`
`

`

`As explained in the next section, Mr. Kapusta also generated schematics for
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`a circuit embodying his invention using the Cadence ICFB tools, and on October
`
`29, 2010, checked those schematics (the “Schematics”) into Analog’s revision
`
`management system. Both the Design Review and the Schematics establish
`
`conception of the claimed invention prior to Yoshioka’s publication date on
`
`November 9, 2010. The following summary identifies the portions of the Design
`
`Review and Schematics corroborating conception prior to November 9, 2010,
`
`using the same claim limitation numbering convention as the Petition. Ex. 2006;
`
`Ex. 2015; Ex. 2016; Ex. 2017; Ex. 2044, ¶¶ 28-30.
`
`Claim limitation
`
`Design Review (July 20, 2010) and
`
`Schematics (October 29, 2010)
`
`[1pre] A comparator,
`
`DR page 1: “This memo will cover the main
`
`comprising:
`
`comparator for the SAR ADC in the Gecko
`
`project.”
`
`Comparator Schematic:
`
`
`
`- 17 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`[1a] a preamplifier responsive
`
`DR page 3: “There are two pre-amplifiers in
`
`to a first control signal;
`
`front of the regenerative latch.”
`
`
`
`As shown in the diagrams below, both
`
`preamplifers receive a reset (i.e., control)
`
`signal.
`
`Comparator Schematic:
`
`
`
`
`
`- 18 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`[1b] a latch responsive to a
`
`DR page 3: “There are two pre-amplifiers in
`
`second control signal; and
`
`front of the regenerative latch.”
`
`
`
`
`
`The latch receives a qTIMER (i.e., second control)
`
`signal.
`
`DR page 9:
`
`
`
`- 19 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`Comparator Schematic:
`
`
`
`
`
`[1c] a delay element, having
`
`DR page 10: “Basically, we want the timer
`
`an input for the first control
`
`circuit to be faster when the conditions are
`
`signal and an output for the
`
`slow (low supply, slow devices, etc.), since it is
`
`second control signal, the
`
`in those corners that we get the most benefit
`
`delay element having a circuit
`
`from spending more time with the latch in a
`
`structure to adaptively increase
`
`high current, fast state.”
`
`
`
`- 20 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`or decrease delay propagation
`
`DR page 10:
`
`of the first control signal in a
`
`manner that counteracts PVT
`
`effects present in other
`
`components of the comparator.
`
`
`
`Comp_clkgen Schematic: The blue highlighted
`
`portion matches Figure 8 of the Design
`
`Review:
`
`
`
`[2pre] The comparator of claim
`
`See claim 1
`
`1, wherein the delay element
`
`further comprises:
`
`[2a] a capacitive element for
`
`DR page 10:
`
`supplying a threshold voltage
`
`
`
`- 21 -
`
`

`

`to a control input of an
`
`output switch; and
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`Comp_clkgen Schematic:
`
`
`
`
`
`[2b] an intermediate switch
`
`DR page 10:
`
`for selectively delivering a
`
`“There are a few reasons this circuit is a good
`
`current to the capacitive
`
`timer. First, when devices are "slow", they
`
`element, wherein the
`
`typically have large VT, so that the PMOS
`
`capacitive element charges to a
`
`device will shut off sooner. Similarly, if VDD
`
`threshold voltage that actuates
`
`is low, the capacitor also has to be charged less
`
`the output switch which
`
`in order to trigger the PMOS device.”
`
`
`
`- 22 -
`
`

`

`changes an output signal,
`
`wherein a time required to
`
`charge the capacitive element
`
`to the threshold voltage varies
`
`in response to circuit
`
`conditions of the comparator.
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`Comp_clkgen Schematic:
`
`
`
`
`
`[3] The comparator of claim 2,
`
`DR page 11:
`
`wherein a current source
`
`“[I]CORNER has positive temperature
`
`provides the current to the
`
`dependence, i.e. the temperature effect on
`
`capacitive element, and the
`
`VDSAT is stronger than its effect on VT, so that
`
`current is proportional to the
`
`the voltage across the resistor increases with
`
`temperature of circuit
`
`increasing temperature”
`
`components of the comparator.
`
`DR page 10:
`
`
`
`- 23 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`The current source is split between two
`
`Schematics, for different portions of the
`
`comp_clkgen circuit.
`
`
`
`
`
`
`
`
`
`- 24 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`[4pre] The comparator of claim
`
`See claim 3
`
`3, wherein the current source
`
`comprises:
`
`[4a] a first pair of transistors
`
`DR page 11:
`
`configured as a current
`
`mirror;
`
`Comp_clkgen Schematic:
`
`
`
`
`
`[4b] a second pair of
`
`The two transistors in the pair are depicted in
`
`transistors with commonly
`
`separate diagrams in the Design Review. The
`
`connected control inputs
`
`first transistor is the ICORNER current source in
`
`connected to a drain terminal
`
`Figure 8, and the second transistor is the
`
`highlighted transistor in Figure 9.
`
`
`
`- 25 -
`
`

`

`of one transistor of the first
`
`DR page 10:
`
`pair of transistors; and
`
`IPR2020-01219
`Patent Owner’s Response
`
`
`DR page 11:
`
`
`
`
`
`The two transistors in the pair are depicted in
`
`separate diagrams in the schematics for
`
`comp_clkgen. Both highlighted transistors
`
`have gates coupled to the control signal vps3,
`
`
`
`- 26 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`which is connected to the drain of one of the
`
`transistors in the first pair of transistors:
`
`Comp_clkgen Schematic:
`
`
`
`
`
`
`
`[4c] a single transistor with a
`
`DR page 11:
`
`control input connected to a
`
`terminal of a resistive
`
`element.
`
`
`
`- 27 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`Comp_clkgen Schematic:
`
`[5pre] A successive
`
`See [1pre]
`
`
`
`approximation register analog-
`
`to-digital converter on an
`
`integrated circuit chip
`
`configured with a plurality of
`
`on-chip circuit components,
`
`comprising:
`
`[5a] a comparator for
`
`See [1pre]
`
`determining whether an input
`
`signal is representative of a
`
`digital high or low signal; and
`
`[5b] an adaptive delay device
`
`See [1c]
`
`having an input for receiving a
`
`control signal and an output
`
`
`
`- 28 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`connected to the comparator,
`
`wherein the adaptive delay
`
`device is configured to respond
`
`inversely to the response of
`
`other circuit components
`
`forming the successive
`
`approximation register analog-
`
`to-digital converter, and output
`
`the control signal to the
`
`comparator based on the
`
`inverse response of the
`
`adaptive delay device.
`
`[6pre] The successive
`
`See claim 5
`
`approximation register analog-
`
`to-digital converter of claim 5,
`
`wherein the adaptive delay
`
`device further comprises:
`
`[6a] a capacitive element for
`
`See [2a]
`
`supplying a threshold voltage
`
`
`
`- 29 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`to a control input of an output
`
`switch; and
`
`an intermediate switch for
`
`See [2b]
`
`selectively delivering a current
`
`to the capacitive element,
`
`wherein the capacitive element
`
`charges to a threshold voltage
`
`that actuates the output switch
`
`which changes an output
`
`signal, wherein the time
`
`required to charge the
`
`capacitive element to the
`
`threshold voltage is responsive
`
`to circuit conditions of the
`
`converter.
`
`[7] The successive
`
`See claim 3
`
`approximation register analog-
`
`to-digital converter of claim 6,
`
`wherein the current is
`
`
`
`- 30 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`proportional to the temperature
`
`of circuit components of the
`
`converter, and provided by a
`
`current source.
`
`8. The successive
`
`See claim 7
`
`approximation register analog-
`
`to-digital converter of claim 7,
`
`wherein the current source
`
`comprises:
`
`a first pair of transistors
`
`See [4a]
`
`configured as a current mirror;
`
`a second pair of transistors
`
`See claim 4
`
`with commonly connected
`
`control inputs connected to a
`
`drain terminal of one transistor
`
`of the first pair of transistors;
`
`and
`
`
`
`- 31 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`a single transistor with a
`
`See [4c]
`
`control input connected to a
`
`terminal of a resistive element.
`
`9. A method of controlling
`
`See [1c]
`
`PVT effects in a circuit system,
`
`comprising:
`
`responsive to a state change in
`
`See [2a]
`
`an input signal, charging a
`
`capacitive element with
`
`reference to a first supply
`
`voltage; and
`
`when the capacitive element's
`
`See [2b]
`
`output voltage reaches a
`
`voltage threshold, generating
`
`an output voltage;
`
`wherein the method is
`
`See [2b]
`
`performed in an integrated
`
`circuit, and delays between the
`
`state change of the input signal
`
`
`
`- 32 -
`
`

`

`IPR2020-01219
`Patent Owner’s Response
`
`
`and the generated output
`
`voltage vary inversely in
`
`response to PVT effects on
`
`other components of the
`
`integrated circuit.
`
`[10] The method of claim 9,
`
`See claim 9.
`
`wherein the vo