(12) United States Patent
`Fiscus
`
`USOO6628558B2
`(10) Patent No.:
`US 6,628,558 B2
`(45) Date of Patent:
`Sep. 30, 2003
`
`(54) PROPORTIONAL TO TEMPERATURE
`VOLTAGE GENERATOR
`
`(75) Inventor: Timothy E. Fiscus, South Burlington,
`VT (US)
`
`(73) Assignee: Cypress Semiconductor Corp., San
`Jose, CA (US)
`-
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`c:
`(*) Notice:
`
`(21) Appl. No.: 09/885,897
`(22) Filed:
`Jun. 20, 2001
`(65)
`Prior Publication Data
`
`(56)
`
`
`
`
`
`5,495.452 A 2/1996 Cha ........................... 365/222
`5,646,518 A 7/1997 Lakshmikumar et al. ... 323/316
`5,774,013 A 6/1998 Groe .......................... 327/543
`5,898,343 A 4/1999 Morgan ....................... 33 1/57
`5,963,103 A 10/1999 Blodgett ...................... 33 1/75
`6,016,051. A 1/2000 Can ........................... 323/315
`6,134,167 A 10/2000 Atkinson .................... 365/222
`6,181,121 B1
`1/2001 Kirkland et al. ............ 323/313
`6,181,191 B1
`1/2001 Paschal ...................... 327/513
`6,191,660 B1
`2/2001 Mar et al. ................... 33 1/111
`6,198.356 B1
`3/2001 Visocchi et al. .............. 331/34
`6,222,399 B1
`4/2001 Imbornone et al. ......... 327/143
`6,359.809 B1 * 3/2002 Tedrow et al. ......... 365/185.29
`6,404,690 B2
`6/2002 Johnson et al. ............. 365/149
`OTHER PUBLICATIONS
`“Chip Temperature Measurement', IBM Technical Disclo
`Sure Bulletin, Jun. 1985.
`“Temperature Sensor”, IBM Technical Disclosure Bulletin,
`Sep. 1979.
`US 2002/0196692 A1 Dec. 26, 2002
`“Voltage Controlled Oscillator', IBM Technical Disclosure
`7
`g
`(51) Int. Cl.' .................................................. G11C 7700
`Bulletin, Mar. 977.
`ss
`(52) U.S. Cl. .................. 365,222.365/1sooo. 327,512.
`327/513 IETEM SE YES Rese Source',
`echnical Disclosure Bulletin, Sep.
`(58) Field of "753.513,555 is: "Method and Mechanism to Correct for Clock Drift due to
`/512,
`s
`s
`s
`s
`s
`Temperature Change”, IBM Technical Disclosure Bulletin,
`Mar. 1996.
`References Cited
`sk -
`cited by examiner
`U.S. PATENT DOCUMENTS
`4,165,642 A
`8/1979 Lipp ........................... 732 Primary Examiner-Van Thu Nguyen
`4,393,477 A 7/1983 Murotani ...
`... 36.5/222
`(74) Attorney, Agent, or Firm-Christopher P. Maiorana,
`4,450,367 A 5/1984 Whatley ....
`... 307/297
`P.C.; Robert M. Miller
`4,603.291 A 7/1986 Nelson .........
`... 323/315
`ABSTRACT
`(57)
`4,682,306 A 7/1987 Sakurai et al. .
`... 36.5/222
`A biasing circuit comprising a first circuit and a Second
`4,716,551 A 12/1987 Inagaki .........
`... 36.5/222
`ircuit. The first circuit
`b
`f
`dt
`te a first
`4,978,930 A 12/1990 Suter .........
`... 331/176
`circuit. The first circuit may be configured to generate a firs
`5,072,197 A 12/1991 Anderson .................... 33 1/57
`bias Signal and a Second bias Signal. The Second bias Signal
`5,175,512 A 12/1992 Self ............................ 33 1/57
`may be defined by a threshold Voltage and a first resistance.
`5.180995 A 1/1993 Hayashi et al. ............... 33 1/57
`The Second circuit may be configured to generate a third bias
`5,278,796 A
`1/1994 Tillinghast et al.
`... 36.5/211
`Signal in response to the first and the Second bias Signals and
`5,291,071 A 3/1994 Allen et al. .......
`... 307/270
`a Second resistance. The third bias Signal may have a
`RE347,772
`11/1994 Bernard et al.
`... 323/313
`magnitude that is linearly proportional to absolute tempera
`5,375,093 A 12/1994 Hirano .........
`... 36.5/222
`ture (PTAT) and be configured to vary a refresh rate of a
`5.5 A 2/
`Manning al.
`... 36.5/222
`E. A 9. 5 Main et al. .
`- - - 3. memory cell in response to changes in temperature.
`5.440,277A
`8/1995 Ewen et al...
`... 331/176
`5,444.219 A 8/1995 Kelly ......................... 219/505
`
`22 Claims, 3 Drawing Sheets
`
`100
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`8
`WCC
`12
`—-d-
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`:
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`128
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`WBAS
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`108
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`WCC
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 1
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`U.S. Patent
`
`Sep. 30, 2003
`
`Sheet 1 of 3
`
`US 6,628,558 B2
`
`VCC
`
`l/
`
`FIG. 1
`(CONVENTIONAL)
`
`
`
`PTAT
`VOLTAGE
`GENERATOR
`
`REFRESH
`CIRCUIT
`
`MEMORY
`ARRAY
`
`FIG. 4
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 2
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`U.S. Patent
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`Sep. 30, 2003
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`Sheet 2 of 3
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`US 6,628,558 B2
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`– — ·
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 3
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`U.S. Patent
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`Sep. 30, 2003
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`Sheet 3 of 3
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`US 6,628,558 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 4
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`

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`1
`PROPORTIONAL TO TEMPERATURE
`VOLTAGE GENERATOR
`
`US 6,628,558 B2
`
`FIELD OF THE INVENTION
`The present invention relates to a method and/or archi
`tecture for Voltage generators generally and, more
`particularly, to a method and/or architecture for a propor
`tional to absolute temperature (PTAT) voltage generator.
`BACKGROUND OF THE INVENTION
`Data (e.g., a “1” or a “0”) is stored in a 1T memory cell
`as a Voltage level. A “1” is Stored as a high Voltage level
`which can decrease due to leakage. A “0” is Stored as a
`Voltage level of Zero volts which can increase due to
`leakage. The 1T memory cell requires a periodic refresh to
`maintain the Voltage level Stored in the cell. In many
`applications, a memory chip uses a ring Oscillator to control
`when the refreshes occur. The frequency of a signal gener
`ated by a typical ring Oscillator decreases with increasing
`temperature because of CMOS device characteristics.
`However, the memory cell leakage increases with tempera
`ture. AS the temperature increases, refresh using a conven
`tional oscillator can occur less frequently than necessary to
`maintain the Voltage level Stored in the memory cell. Thus,
`the oscillator needs to be designed to Support the high
`temperature refresh rate at the expense of more current.
`Proportional to absolute temperature(PTAT) voltages and
`currents are used in temperature monitoring circuits. The
`monitoring circuits either detect a specific temperature or
`output a Voltage and/or current that increases with tempera
`ture. The temperature monitoring circuits can use a PTAT
`and an inverse PTAT, where the crossing point is a desired
`temperature. A conventional method of generating PTAT
`Voltage is to use a delta Vbe generator circuit.
`Referring to FIG. 1, a block diagram of a circuit 10 is
`shown. The circuit 10 is a delta Vbe generator circuit that
`can generate a PTAT Voltage VREF. The voltage VREF is
`described by the following equation 1:
`
`in . k
`n . k. ln(B). T
`Vref = Vbe1 = 'in'' +1). T
`q. A. Is . R
`i
`
`Eq. 1
`
`where T is the absolute temperature in Kelvin, n is the
`emission coefficient, k is Boltzmann's constant, q is the
`charge of an electron, IS is the theoretical reverse Saturation
`current, A is the Smaller of the areas of diodes 12 and 14, B
`is the ratio of the areas of the diodes 12 and 14, and R is the
`resistance of the resistor 16. The resistance R generally has
`a positive temperature coefficient. The emission coefficient
`n is related to the doping profile and affects the exponential
`behavior of the diodes 12 and 14. The value of n is normally
`approximated to be 1.
`The voltage VREF is proportional to the temperature T,
`ln(T), and 1/R(T). Also, a current I is generated equal to
`Vtln(B)/R which is proportional to temperature since R has
`a positive temperature coefficient and Vt=k*T/q. The volt
`age VREF is generated by using a Voltage across a diode
`with the bandgap current I flowing through the diode. The
`circuit 10 has the following disadvantages: a complex rela
`tionship between temperature and the voltage VREF (i.e.,
`the voltage VREF is a function of T ln(T), and ln(1/R(T));
`the value of the voltage VREF is limited when the bandgap
`current I is also used to generate a PVT compensated
`Voltage, and a larger value for the Voltage VREF requires a
`higher current I.
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`SUMMARY OF THE INVENTION
`The present invention concerns a biasing circuit compris
`ing a first circuit and a Second circuit. The first circuit may
`be configured to generate a first bias Signal and a Second bias
`Signal. The Second bias Signal may be defined by a threshold
`Voltage and a first resistance. The Second circuit may be
`configured to generate a third bias Signal in response to the
`first and the Second bias Signals and a Second resistance. The
`third bias Signal may have a magnitude that is linearly
`proportional to absolute temperature (PTAT) and be config
`ured to vary a refresh rate of a memory cell in response to
`changes in temperature.
`The objects, features and advantages of the present inven
`tion include providing a method and/or architecture for a
`proportional to absolute temperature (PTAT) voltage gen
`erator that may (i) use a bandgap reference with a current
`equal to Vtln(B)/R, (ii) use one additional resistor to form
`a linear PTAT voltage reference, and/or (iii) provide a PTAT
`Voltage reference that may be Scaled by a ratio of resistor
`values.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`These and other objects, features and advantages of the
`present invention will be apparent from the following
`detailed description and the appended claims and drawings
`in which:
`FIG. 1 is a block diagram of a delta Vbe generator circuit;
`FIG. 2 is a block diagram of a preferred embodiment of
`the present invention;
`FIG. 3 is a block diagram of an implementation of the
`present invention; and
`FIG. 4 is a block diagram of a memory device in accor
`dance with a preferred embodiment of the present invention.
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`Referring to FIG. 2, a block diagram of a circuit 100 is
`shown in accordance with a preferred embodiment of the
`present invention. The circuit 100 may be implemented as a
`proportional to temperature Voltage generator circuit. The
`circuit 100 may be configured to generate a first voltage
`Signal (e.g., NCTR) and a Second voltage signal (e.g.,
`PCTR) that may be proportional to absolute temperature
`(PTAT). The circuit 100 may comprise a circuit 102 and a
`circuit 104. The circuit 102 may be implemented as a PTAT
`current source circuit. The circuit 104 may be implemented
`as a PTAT voltage reference circuit. The circuit 102 may be
`configured to generate a temperature dependent reference
`signal (e.g., VREF) and a bias signal (e.g., VBIAS). The
`signal VREF may vary linearly with temperature. The signal
`VREF may be presented to an input 106 of the circuit 104.
`The signal VBIAS may be presented to an input 108 of the
`circuit 104. The circuit 104 may be configured to generate
`the signals NCTR and PCTR in response to the signal VREF
`and the signal VBIAS. The signal PCTR may be a mirror of
`the signal NCTR.
`The circuit 102 may comprise a transistor 110, a transistor
`112, a transistor 114, a transistor 116, a transistor 118, a
`device 120, a device 122, a device 124, and an amplifier 126.
`The transistors 110-114 may be implemented as one or more
`PMOS transistors. The transistors 116 and 118 may be
`implemented as one or more NMOS transistors. However,
`other types and/or polarity of transistors may be imple
`mented accordingly to meet the design criteria of a particular
`application. The devices 120 and 122 may be implemented
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 5
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`US 6,628,558 B2
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`as base-emitter junction devices (e.g., diodes, diode
`connected transistors, etc.). In one example, the devices 120
`and 122 may be implemented as forward biased diodes. The
`device 120 may have an area A. The device 122 generally
`has an area that is B times A, where B is an integer. The
`device 124 may be implemented as a resistive circuit. In one
`example, the device 124 may be implemented as a resistor
`having a predetermined resistance R. The amplifier 126 may
`be implemented as an operational amplifier circuit.
`The transistors 112-118 and the devices 120-124 may be
`configured as a delta Vbe generator circuit. A Source of the
`transistor 110 may be connected to a Supply Voltage (e.g.,
`VCC). A node 128 may be formed by coupling a drain of the
`transistor 110 with a source of the transistor 112 and the
`transistor 114. The signal VBIAS may be presented at the
`node 128. A node 130 may be formed by coupling a gate of
`the transistor 112, a gate and a drain of the transistor 114, and
`a drain of the transistor 118. The signal VREF may be
`presented at the node 130. A node 132 may be formed by
`coupling a drain of the transistor 116, a drain and a gate of
`the transistor 116, and a gate of the transistor 118. A source
`of the transistor 116 may be coupled to a first terminal of the
`device 120. A second terminal of the device 120 may be
`connected to a Voltage Supply ground potential (e.g., VSS).
`A source of the transistor 118 may be coupled to a first
`25
`terminal of the device 124. A second terminal of the device
`124 may be coupled to a first terminal of the device 122. A
`second terminal of the device 122 may be connected to the
`voltage supply ground potential VSS. The first terminals of
`the devices 120 and 122 may be connected, in one example,
`to anodes of the devices 120 and 122. The second terminal
`of the devices 120 and 122 may be connected, in one
`example, to cathodes of the devices 120 and 122.
`A first input (e.g., a non-inverting input) of the amplifier
`126 may be coupled to the node 130. A second input (e.g.,
`an inverting input) of the amplifier 126 may be coupled to
`the node 132. An output of the amplifier 126 may be coupled
`to a gate of the transistor 110. The amplifier 126 generally
`forces a current (e.g., I) through the transistors 112 and 116
`to be the same as a current through the transistorS 114 and
`118. The current I may be described by the following
`equation 2:
`
`Wbe1 = Wibe) + i. R
`
`= AVbe n : Vt. ln(B)
`R
`R
`
`Eq. 2
`
`The circuit 104 may comprise a transistor 140, a device
`142, a transistor 144, a transistor 146, a transistor 148, and
`a transistor 150. The transistors 140, 148 and 150 may be
`implemented as one or more PMOS transistors. The tran
`sistors 144 and 146 may be implemented as one or more
`NMOS transistors. However, other types and polarity tran
`Sistors may be implemented accordingly to meet the design
`criteria of a particular application. The device 142 may be
`implemented as a resistive circuit. In one example, the
`device 142 may be implemented as a resistor having a
`predetermined resistance R1.
`The signal VBIAS may be presented to a source of the
`transistor 140. The signal VREF may be presented to a gate
`of the transistor 140. A drain of the transistor 140 may be
`coupled to a first terminal of the device 142. The signal
`NCTR may be presented at the drain of the transistor 140.
`A second terminal of the device 142 may be connected to the
`voltage supply ground potential VSS. The transistor 140 will
`generally pass a current equal to the current I in response to
`the signals. VREF and VBIAS. By passing the current I
`(where I=n-Vtln(B)/R, n is the emission coefficient, B is
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`the ratio of diode areas of the devices 120 and 122, R is a
`predetermined resistance, and Vt is a thermal voltage)
`through the resistance R1, a Voltage may be generated, as
`shown by the following equation 3:
`
`... Wit. ln(B
`in Viln(B)
`
`.k. In(B) R1
`in kiln(B). R1
`
`Ed. 3
`C
`
`When the current I is passed through the device 142, the
`Signal NCTR may be generated having a Voltage level equal
`to ln(B) times Vt times R1/R. The voltage level of the signal
`NCTR is generally proportional to absolute temperature and
`may be scaled by selecting the ratio R1/R.
`The signal NCTR may be presented to a gate of the
`transistor 144. A source of the transistor 144 and a gate of
`the transistor 148 may be connected to the Voltage Supply
`ground potential VSS. A drain of the transistor 144 may be
`connected to a Source of the transistor 146. A gate of the
`transistor 146 may be connected to the Supply voltage VCC.
`A drain of the transistor 146 may be connected to a drain of
`the transistor 148. A source of the transistor 150 may be
`connected to the Supply voltage VCC. A node 152 may be
`formed by connecting a source of the transistor 148 with a
`drain and a gate of the transistor 150. The signal PCTR may
`be presented at the node 152. The signal PCTR may be a
`mirror of the signal NCTR.
`Referring to FIG. 3, a block diagram of a circuit 200 is
`shown illustrating a Voltage controlled oscillator in accor
`dance with a preferred embodiment of the present invention.
`The circuit 200 may be implemented, in one example, as a
`refresh oscillator of a dynamic memory device. The circuit
`200 may have an input 202 that may receive the signal
`PCTR, and an input 204 that may receive the signal NCTR.
`The circuit 200 may comprise a number of inverting ampli
`fier (delay) stages 206a–206n. In one example, the stages
`206a-206n may form a current starved inverter ring oscil
`lator. The signals PCTR and NCTR may be implemented as
`load bias voltages for the delay stages 206a-206n. The
`circuit 200 may be configured to generate a signal (e.g.,
`RFRSH) having a frequency that is proportional to tempera
`ture. The signal RFRSH may be used to control a refresh of
`a memory. For example, the signal RFRSH may be used to
`change a refresh rate of the memory in response to a
`temperature change.
`The circuit 200 may be implemented as a refresh oscil
`lator of a dynamic memory device. Since the leakage of the
`memory cells increase with increasing temperature, a PTAT
`Voltage-controlled oscillator in accordance with the present
`invention may be used to refresh the memory cell more
`frequently as the temperature increases. The present inven
`tion may provide temperature dependent refreshing and also
`may be used in any application requiring a temperature
`monitor.
`Referring to FIG. 4, a block diagram of a memory device
`210 is shown. The memory device 210 is generally shown
`implemented in accordance with the present invention. The
`memory device 210 may comprise the circuit 100, the circuit
`200, and an array of memory cells 212. The circuit 100 may
`be configured to control the refresh circuit 200. The refresh
`circuit 200 may be configured to control refresh operations
`on the memory cells of the array 212. For example, The
`circuit 100 may be configured to alter the rate at which the
`circuit 200 refreshes the memory array 212 depending upon
`temperature.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof, it will be understood by those skilled in the art that
`various changes in form and details may be made without
`departing from the Spirit and Scope of the invention. For
`example, any circuit that generates a current equal to a
`
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`constant times Vt/R may be used to generate the PTAT
`voltage reference NCTR.
`What is claimed is:
`1. A biasing circuit comprising:
`a first circuit configured to generate a first bias Signal and
`a Second bias Signal, wherein Said Second bias Signal is
`defined by a threshold Voltage and a first resistance, and
`a Second circuit configured to generate a third bias Signal
`in response to Said first and Second bias Signals and a
`Second resistance, wherein Said third bias Signal has a
`magnitude that (i) is linearly proportional to absolute
`temperature (PTAT), (ii) is determined by a ratio of said
`Second resistance to said first resistance and (iii) is
`configured to vary a refresh rate of a memory cell in
`response to changes in temperature.
`2. The biasing circuit according to claim 1, wherein Said
`biasing circuit comprises a proportional to temperature
`Voltage generator.
`3. The biasing circuit according to claim 1, wherein Said
`first circuit comprises:
`a first current Source configured to generate a first pro
`portional to absolute temperature (PTAT) current, said
`first PTAT current defined by a threshold voltage;
`a Second current Source configured to generate a Second
`PTAT current in response to said first PTAT current,
`said second PTAT current defined by a threshold
`Voltage, a ratio of diode areas and Said first resistance;
`and
`a control circuit configured to equalize said first PTAT
`current and said second PTAT current.
`4. The biasing circuit according to claim 1, wherein Said
`Second circuit comprises:
`a current Source configured to generate a PTAT current
`that varies linearly with temperature.
`5. The biasing circuit according to claim 1, wherein Said
`Second bias Signal comprises a bandgap reference Voltage.
`6. The biasing circuit according to claim 1, wherein Said
`first circuit comprises:
`a first current mirror comprising a plurality of PMOS
`40
`transistors,
`a second current mirror comprising a plurality of NMOS
`transistors, said Second current mirror coupled to Said
`first current mirror;
`a first diode coupled directly to Said Second current
`mirror; and
`a Second diode coupled through a resistor to Said Second
`current mirror.
`7. The biasing circuit according to claim 1, wherein Said
`Second circuit further comprises a Voltage mirror configured
`to generate a fourth bias Signal in response to Said third bias
`Signal.
`8. The biasing circuit according to claim 3, wherein Said
`control circuit comprises:
`an operational amplifier coupled to Said first current
`Source and Said Second current Source and configured to
`equalize said first PTAT current and said second PTAT
`Current.
`9. A circuit for generating temperature Sensitive biasing in
`response to a proportional to absolute temperature (PTAT)
`Voltage reference comprising:
`a first circuit configured to generate a first bias Signal and
`a Second bias Signal, wherein Said Second bias Signal is
`defined by a threshold Voltage and a first resistance, and
`a Second circuit configured to generate one or more third
`bias Signals in response to Said first and Second bias
`Signals and a Second resistance,
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`wherein Said one or more third bias Signals
`(a) have a magnitude that (i) is linearly proportional to
`absolute temperature (PTAT) and (ii) is determined
`by a ratio of Said Second resistance to Said first
`resistance, and
`(b) vary a refresh rate of a memory cell with tempera
`ture.
`10. The circuit according to claim 9, wherein said one or
`more third bias Signals provide load bias Voltages to a
`plurality of delay Stages of a Voltage controlled Oscillator.
`11. The circuit according to claim 10, wherein said
`Voltage controlled Oscillator is configured to generate a
`Signal having a frequency that varies with temperature.
`12. The circuit according to claim 11, wherein Said
`frequency varies linearly with temperature.
`13. The circuit according to claim 11, wherein said
`frequency variation is proportional to absolute temperature.
`14. A method for controlling a refresh rate of a memory
`using a proportional to absolute temperature (PTAT) voltage
`reference comprising the Steps of
`(A) generating a first bias Signal;
`(B) generating a second bias signal, wherein said Second
`bias Signal is defined by a threshold Voltage and a first
`resistance, and
`(C) generating a third bias signal in response to said first
`and Second bias Signals and a Second resistance,
`wherein said third bias signal has a magnitude that (i)
`is linearly proportional to absolute temperature (PTAT),
`(ii) is determined by a ratio of Said Second resistance to
`Said first resistance and (iii) is configured to vary a
`refresh rate of a memory cell with temperature.
`15. The method according to claim 14, wherein step A
`comprises the Sub-steps of:
`generating a first PTAT current;
`generating a Second PTAT current; and
`adjusting Said first bias Signal to equalize Said first and
`Second PTAT currents.
`16. The method according to claim 14, wherein the step
`C comprises the Sub-Steps of:
`generating a PTAT current in response to Said first bias
`Signal and Said Second bias Signal; and
`passing Said PTAT current through said Second resistance.
`17. The method according to claim 14, further comprising
`the step of:
`presenting Said third bias Signal to a memory circuit to
`control a refresh rate.
`18. The method according to claim 17, wherein said
`presenting Step comprises the Sub-Step of:
`generating a signal having a frequency that increases
`linearly with temperature.
`19. The method according to claim 18, wherein said
`increase is proportional to absolute temperature.
`20. A biasing circuit comprising:
`a first circuit configured to generate a first bias Signal and
`a bandgap reference Voltage; and
`a Second circuit configured to generate a Second bias
`Signal in response to Said first bias Signal, Said bandgap
`reference Voltage and a resistance, wherein Said Second
`bias Signal has a magnitude that (i) is linearly propor
`tional to absolute temperature (PTAT) and (ii) is con
`figured to vary a refresh rate of a memory cell in
`response to changes in temperature.
`21. A biasing circuit comprising:
`a first circuit configured to generate a first bias Signal and
`a Second bias Signal, wherein Said Second bias Signal is
`defined by a threshold Voltage and a first resistance,
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 7
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`a voltage mirror configured to generate a fourth bias
`a Second circuit configured to generate a third bias Signal
`Signal in response to Said third bias Signal.
`in response to Said first and Second bias Signals and a
`22. The biasing circuit according to claim 21, wherein a
`resistance, wherein Said third bias Signal has a magni-
`magnitude of Said third bias Signal is determined by a ratio
`tude that (i) is linearly proportional to absolute tem-
`perature (PTAT) and (ii) is configured to vary a refresh 5 of said second resistance to said first resistance.
`rate of a memory cell in response to changes in tem
`perature; and
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`k
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`US 6,628,558 B2
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1006 Page 8
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