ANALOG
`DEVICES
`Data Sheet
`
`FEATURES
`
`Single 3V supply operation (23V to 3.6V)
`SNR = 70.4 dBc to Nyquist
`SFDR = 87.8 dBc to Nyquist
`Low power: 366 mW
`Differential input with 500 MHz bandwidth
`On-chip reference and sample-and-hold
`DNL = ±0.4 LSB
`Flexible analog input: 1 V p-p to 2 V p-p range
`Offset binary or twos complement data format
`Clock duty cycle stabilizer
`
`APPLICATIONS
`
`High end medical imaging equipment
`IF sampling in communications receivers
`WCDMA, CDMA-One, CDMA-2000
`Battery-powered instruments
`Hand-held scopemeters
`Low cost digital oscilloscopes
`DTV subsystems
`
`GENERAL DESCRIPTION
`
`The AD9236 is a monolithic, single 3 V supply, 12-bit, 80 MSPS
`analog-to-digital converter featuring a high performance sample-
`and-hold amplifier (SHA) and voltage reference. The AD9236
`uses a multistage differential pipelined architecture with output
`error correction logic to provide 12-bit accuracy at 80 MSPS
`and guarantee no missing codes over the full operating
`temperature range.
`
`The wide bandwidth, truly differential SHA allows a variety of
`user-selectable input ranges and common modes, including
`single-ended applications. It is suitable for multiplexed systems
`that switch full-scale voltage levels in successive channels and
`for sampling single-channel inputs at frequencies well beyond
`the Nyquist rate. Combined with power and cost savings over
`previously available analog-to-digital converters, the AD9236 is
`suitable for applications in communications, imaging, and
`medical ultrasound.
`
`A single-ended clock input is used to control all internal
`conversion cycles. A duty cycle stabilizer (DCS) compensates
`for wide variations in the clock duty cycle while maintaining
`excellent overall ADC performance. The digital output data is
`
`12-Bit, 80 MSPS, 3 V AID Converter
`A09236
`
`FUNCTIONAL BLOCK DIAGRAM
`
`AVOD
`
`ORVOD
`
`AD9236
`
`8-STAGE
`1/2-BIT PIPELINE
`
`At
`
`SHA
`
`-
`
`MDACI
`c
`
` HNo
`
`VREF
`
`SENSE 0 t
`
`REF
`SELECT
`
`CORRECTION LOGIC
`
`OTR
`
`12
`OUTPUT BUFFERS
`
`DII (MISS)
`
`DO (LSB)
`
`B.5V
`
`CLOCK
`DUTY CYCLE
`STABILIZER
`
`MODE
`SELECT
`
`AGND
`
`CIA
`
`0
`PDWN MODE DGND
`
`Figure 7.
`
`presented in straight binary or twos complement formats. An
`out-of-range (OTR) signal indicates an overflow condition that
`can be used with the most significant bit to determine low or
`high overflow. Fabricated on an advanced CMOS process, the
`AD9236 is available in a 28-lead TSSOP and a 32-lead LFCSP
`and is specified over the industrial temperature range
`(-40°C to +85°C).
`
`PRODUCT HIGHLIGHTS
`
`1. The AD9236 operates from a single 3 V power supply and
`features a separate digital output driver supply to
`accommodate 2.5 V and 3.3 V logic families.
`
`2. Operating at 80 MSPS, the AD9236 consumes a low 366 mW
`
`3. The patented SHA input maintains excellent performance for
`input frequencies up to 100 MHz, and can be configured for
`single-ended or differential operation.
`
`4. The AD9236 is pin compatible with the AD9215, AD9235,
`and AD9245. This allows a simplified migration from 10 bits
`to 14 bits and 20 MSPS to 80 MSPS.
`
`5. The DCS maintains overall ADC performance over a wide
`range of clock pulse widths.
`
`6. The OTR output bit indicates when the signal is beyond the
`selected input range.
`
`Exhibit
`1014
`
`Document Feedback
`Rev. C
`information furnished by Analog Dets is beNeved to be accurate and reliable. Honer, no
`re,poedbilityisassumed byMgDSeskanyflfdng.nntofpatentsorother
`rghteofthiSpardesthatmayiesuIttvmftsute.S,sifisalionsaiIcttodiangewithoutno6callo
`liaise is granted by Implication or othente izider any patent or patent rights of AnaIg D.A.
`Trademarks and registered trademarks are the property of their respective owilen.
`
`One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
`Tel: 781.329.4700
`©2013 Analog Devices, Inc. All rights reserved.
`Technical Support
`www.analog.com
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 1
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
` 10
`
` 11
`
`14
`
`14
`
` 15
`
`16
`
`16
`
`17
`
`17
`
` 18
`
`18
`
`33
`
`34
`
` 15
`
`17
`22
`28
`29
`32
`33
`
`AD9236
`
`TABLE OF CONTENTS
`Features
`
`Applications
`
`General Description
`
`Functional Block Diagram
`
`Product Highlights
`
`Revision History
`
`DC Specifications
`
`AC Specifications
`
`Digital Specifications
`
`Switching Specifications
`
`Absolute Maximum Ratings
`
`Thermal Resistance
`
`ESD Caution
`
`Terminology
`
`Pin Configurations and Function Descriptions
`
`1
`
`1
`
`Equivalent Circuits
`
`Typical Performance Characteristics
`
` 1
`
`Theory of Operation
`
`Analog Input and Reference Overview
`
`Clock Input Considerations
`
`Power Dissipation and Standby Mode
`
`Digital Outputs
`
`Timing
`
`Voltage Reference
`
`Operational Mode Selection
`
`Evaluation Board
`
`Outline Dimensions
`
`Ordering Guide
`
`1
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`7
`
`7
`
`8
`
`9
`
`10/03—Rev. 0 to Rev. A
`Changes to Figure 30
`
`Changes to Figure 33
`
`Changes to Figure 40
`
`Changes to Figure 49
`
`Changes to Figure 50
`
`Changes to Table 11
`Changes to Ordering Guide
`
`REVISION HISTORY
`
`2/13—Rev. B to Rev. C
`Changed CP-32-2 Package to CP-32-7 Package
`Changes to Figure 4
`Updated Outline Dimensions
`Changes to Ordering Guide
`
`Universal
`9
`33
`34
`
`1/06—Rev. A to Rev. B
`15
`Changes to Figure 29
`16
`Changes to Equation in Jitter Considerations Section
`Changes to Internal Reference Connection Section, Figure 34,
`and Table 10
`17
`Changes to Figure 35
`18
`Changes to Figure 38
`20
`Changes to Figure 39
`21
`Changes to Figure 48
`27
`Changes to Figure 49
`28
`Changes to Figure 50
`29
`Changes to Table 12
`32
`Updated Outline Dimensions
`33
`Changes to Ordering Guide
`34
`
`Rev. C I Page of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 2
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`DC SPECIFICATIONS
`AVDD = 3 V, DRVDD = 2.5 V. sample rate = 80 MSPS, 2 vp-p differential input, 1.0 V external reference, unless otherwise noted.
`
`Table 1.
`
`Parameter
`RESOLUTION
`ACCURACY
`No Missing Codes
`Offset Error'
`Gain Error
`Gain Error'
`Differential Nonlinearity (DNL)'
`Integral Nonlinearity (INL)'
`TEMPERATURE DRIFT
`Offset Error'
`Gain Error
`Gain Error'
`INTERNAL VOLTAGE REFERENCE
`Output Voltage Error (1 V)
`Load Regulation @1.0 mA
`Output Voltage Error (0.5 V)
`Load Regulation @0.5 mA
`INPUT REFERRED NOISE
`VREF = 0.5 V
`VREF = 1.0 V
`ANALOG INPUT
`Input Span, VREF=0.SV
`Input Span, VREF= 1.OV
`Input Capacitance
`REFERENCE INPUT RESISTANCE
`POWER SUPPLIES
`Supply Voltage
`AVDD
`DRVDD
`Supply Current
`IAVDD 4
`IDRVDD4
`PSRR
`POWER CONSUMPTION
`Low Frequency Input4
`Standby Power
`
`Temp
`Full
`
`Test Level
`VI
`
`Min
`12
`
`AD9236BRUIAD9236BCP
`Typ
`Max
`
`Full
`Full
`25°C
`Full
`Full
`Full
`
`Full
`Full
`Full
`
`Full
`25°C
`25°C
`25°C
`
`25°C
`25°C
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`
`Full
`25°C
`25°C
`
`25°C
`25°C
`
`VI
`VI
`V
`VI
`VI
`VI
`
`V
`V
`V
`
`VI
`V
`V
`V
`
`V
`V
`
`IV
`IV
`V
`V
`
`IV
`IV
`
`VI
`V
`V
`
`V
`V
`
`±1.30
`
`±4.34
`±0.65
`±1.20
`
`±35
`
`3.6
`3.6
`
`137
`
`Guaranteed
`±0.30
`±0.10
`±0.30
`±0.40
`±0.35
`
`±6
`±12
`±18
`
`±2
`0.8
`±1
`0.1
`
`0.55
`0.28
`
`1
`2
`7
`7
`
`2.7
`2.25
`
`3.0
`2.5
`
`122
`8
`±0.01
`
`366
`1.0
`
`Unit
`Bits
`
`% FSR
`% FSR
`% FSR
`LSB
`LSB
`
`ppm/°C
`ppm/°C
`ppm/°C
`
`mV
`mV
`mV
`mV
`
`LSB rms
`LSB rms
`
`Vp-p
`Vp-p
`pF
`kU
`
`V
`V
`
`mA
`mA
`% FSR
`
`mW
`mW
`
`1 with a 1.oV internal reference.
`'Measured at low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
`'Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
`4Measured at AC Specifications conditions without output drivers.
`with a dc input CLK pin inactive (that is, set to AVDD or AGND).
`
`Rev. C I Page 3 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 3
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`AD9236
`
`Data Sheet
`
`AC SPECIFICATIONS
`AVDD = 3 V, DRVDD = 2.5 V. sample rate = 80 MSPS, 2 vp-p differential input, 1.0 V external reference, AIN = -0.5 dBFS, DCS off,
`unless otherwise noted.
`
`Table 2.
`
`Parameter
`SIGNAL-TO-NOISE-RATIO (SNR)
`fIN = 2.4 MHz
`
`fIN=40MHz
`fIN = 70 MHz
`
`fIN= 100 MHz
`SIGNAL-TO-NOISE AND DISTORTION (SINAD)
`fIN = 2.4 MHz
`
`fIN = 40 MHz
`fIN = 70 MHz
`
`fIN= 100 MHz
`
`EFFECTIVE NUMBER OF BITS (ENOB)
`fIN = 2.4 MHz
`
`fIN=40MHz
`fIN = 70 MHz
`
`fIN = 100 MHz
`WORST SECOND OR THIRD
`fIN = 2.4 MHz
`
`fIN = 40 MHz
`fIN = 70 MHz
`
`fIN= 100 MHz
`SPURIOUS FREE DYNAMIC RANGE (SFDR)
`fIN = 2.4 MHz
`
`fIN = 40 MHz
`fIN = 70 MHz
`
`flN= 100 MHz
`
`Temp
`
`Test Level
`
`AD9236BRUIAD9236BCP
`Min
`Typ
`Max
`
`Unit
`
`68.6
`
`67.8
`
`68.4
`
`67.4
`
`11.1
`
`10.9
`
`75.6
`
`73.2
`
`70.9
`70.4
`
`70.1
`69.0
`
`70.8
`70.2
`
`69.8
`68.0
`
`11.5
`11.4
`
`11.3
`11.0
`
`-91.3
`-87.8
`
`-81.4
`-76.4
`
`91.3
`87.8
`
`81.4
`76.4
`
`-75.6
`
`-73.2
`
`dB
`dB
`dB
`dB
`dB
`dB
`
`dB
`dB
`dB
`dB
`dB
`dB
`
`Bits
`Bits
`Bits
`Bits
`Bits
`Bits
`
`dBc
`dBc
`dBc
`dBc
`dBc
`dBc
`
`dBc
`dBc
`dBc
`dBc
`dBc
`dBc
`
`Full
`25°C
`25°C
`Full
`25°C
`25°C
`
`Full
`25°C
`25°C
`Full
`25°C
`25°C
`
`Full
`25°C
`25°C
`Full
`25°C
`25°C
`
`Full
`25°C
`25°C
`Full
`25°C
`25°C
`
`Full
`25°C
`25°C
`Full
`25°C
`25°C
`
`VI
`V
`V
`IV
`V
`V
`
`VI
`V
`V
`IV
`V
`V
`
`VI
`V
`V
`IV
`V
`V
`
`VI
`V
`V
`VI
`V
`V
`
`VI
`V
`V
`IV
`V
`V
`
`Rev. C I Page of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 4
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`DIGITAL SPECIFICATIONS
`AVDD = 3 V, DRVDD = 2.5 V. 1.0 V external reference, unless otherwise noted.
`
`Table 3.
`
`Parameter
`LOGIC INPUTS (CLK, PDWN)
`High Level Input Voltage
`Low Level Input Voltage
`High Level Input Current
`Low Level Input Current
`Input Capacitance
`DIGITAL OUTPUTS (DO-D1 1, OTR)'
`DRVDD = 3.3V
`High Level Output Voltage (IOH = 50 MA)
`High Level Output Voltage (IOH = 0.5 mA)
`Low Level Output Voltage (IOH = 1.6 mA)
`Low Level Output Voltage (IOH = 50 pA)
`DRVDD = 2.5V
`High Level Output Voltage (IOH = 50 pA)
`High Level Output Voltage (IOH = 0.5 mA)
`Low Level Output Voltage (IOH = 1.6 mA)
`Low Level Output Voltage (IOH = 50 pA)
`
`1 Output voltage levels measured with 5 pF load on each output.
`
`Temp
`
`Test Level
`
`AD9236BRU/AD9236BCP
`Min
`Typ
`Max
`
`Unit
`
`Full
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`
`IV
`IV
`IV
`IV
`V
`
`IV
`IV
`IV
`IV
`
`IV
`IV
`IV
`IV
`
`2
`
`2.0
`
`-10
`-10
`
`3.29
`3.25
`
`2.49
`2.45
`
`as
`+10
`+10
`
`0.2
`0.05
`
`0.2
`0.05
`
`V
`V
`pA
`pA
`pF
`
`V
`V
`V
`V
`
`V
`V
`V
`V
`
`Rev. C I Page of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 5
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`A09236
`
`SWITCHING SPECIFICATIONS
`AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
`
`Data Sheet
`
`Table 4.
`
`Parameter
`CLOCK INPUT PARAMETERS
`Maximum Conversion Rate
`Minimum Conversion Rate
`CLK Period
`CLK Pulse Width High'
`CLK Pulse Width Low'
`DATA OUTPUT PARAMETERS
`Output Propagation Delay (tpo) 2
`Pipeline Delay (Latency)
`Aperture Delay (tA)
`Aperture Uncertainty (Jitter, ti)
`Wake-UpTime3
`OUT OF RANGE RECOVERYTIME
`
`Temp
`
`Test Level
`
`Min
`
`AD9236BRUIAD9236BCP
`Typ
`Max
`
`Full
`Full
`Full
`Full
`Full
`
`Full
`Full
`Full
`Full
`Full
`Full
`
`VI
`V
`V
`V
`V
`
`V
`V
`V
`V
`V
`V
`
`80
`
`12.5
`4.0
`4.0
`
`1
`
`3.5
`7
`1.0
`0.3
`7
`2
`
`Unit
`
`MSPS
`MSPS
`ns
`ns
`ns
`
`ns
`Cycles
`ns
`ps rms
`ms
`Cycles
`
`with duty cycle stabilizer (Dcs) enabled.
`* output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
`time is dependant on the value of the decoupling capacitors; typical values shown with 0.1 p and 10 iF capacitors on REFT and REFB.
`
`N
`
`N+I
`
`N
`
`N—I
`
`ANALOG
`
`INPUT
`
`N'S
`
`N+6
`
`CLK
`
`DATA
`
`OUT
`
`tpo = 6.Ons MAX
`
`-=--
`
`2.Ons MIN
`
`02066-0-002
`
`Figure 2 Timing Diagram
`
`Table S. Explanation of Test Levels
`Test Level
`Definitions
`100% production tested.
`100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.
`Sample tested only.
`Parameter is guaranteed by design and characterization testing.
`Parameter is a typical value only.
`100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.
`
`II
`Ill
`IV
`V
`VI
`
`Rev. C I Page 6 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 6
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`ABSOLUTE MAXIMUM RATINGS
`
`AD9236
`
`Table 6.
`
`With
`Respect to
`
`Parameter
`ELECTRICAL
`AGND
`AVDD
`DGND
`DRVDD
`DGND
`AGND
`DRVDD
`AVDD
`DGND
`D0toD11
`AGND
`CLK, MODE
`AGND
`VIN+,VIN-
`AGND
`VREF
`AGND
`SENSE
`AGND
`REFT,REFB
`AGND
`PDWN
`ENVIRONMENTAL
`Storage Temperature
`Operating Temperature Range
`Lead Temperature
`(Soldering 10 sec)
`Junction Temperature
`
`Min Max
`
`Unit
`
`OJA is specified for the worst-case conditions on a 4-layer board
`in still air, in accordance with EIA/JESD51-1.
`
`THERMAL RESISTANCE
`
`V
`+3.9
`-0.3
`V
`+3.9
`-0.3
`V
`+0.3
`-0.3
`V
`-3.9 +3.9
`-0.3 DRVDD+0.3 V
`-0.3 AVOID +0.3
`V
`-0.3 AVDD +0.3
`V
`-0.3 AVDD +0.3
`V
`-0.3 AVOID +0.3
`V
`-0.3 AVOID +0.3
`V
`-0.3 AVDD +0.3
`V
`
`+125
`-65
`-40 +85
`300
`
`150
`
`Table 7.
`Package Type
`
`RU-28
`CP-32-7
`
`GM
`67.7
`32.5
`
`Gic
`
`32.71
`
`Unit
`
`°C/W
`°C/W
`
`Airflow increases heat dissipation effectively, reducing OJA. In
`addition, more metal directly in contact with the package leads
`from metal traces, through holes, ground, and power planes
`reduces the OA. It is recommended that the exposed paddle be
`soldered to the ground plane for the LFCSP package. There is
`an increased reliability of the solder joints, and maximum
`thermal capability of the package is achieved with the exposed
`paddle soldered to the customer board.
`
`Stresses above those listed under Absolute Maximum Ratings
`may cause permanent damage to the device. This is a stress
`rating only and functional operation of the device at these or
`any other conditions above those indicated in the operational
`section of this specification is not implied. Exposure to absolute
`maximum rating conditions for extended periods may affect
`device reliability.
`
`ESD CAUTION
`ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
`human body and test equipment and can discharge without detection. Although this product features
`proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
`electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
`degradation or loss of functionality.
`
`WARNING!
`
`ESD SENSITIVE DEVICE
`
`Rev. C I Page 7 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 7
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`AD9236
`
`Data Sheet
`
`TERMINOLOGY
`Analog Bandwidth (Full Power Bandwidth)
`The analog input frequency at which the spectral power of the
`fundamental frequency (as determined by the FFT analysis) is
`reduced by 3 dB.
`
`Aperture Delay (tA)
`The delay between the 50% point of the rising edge of the clock
`and the instant at which the analog input is sampled.
`
`Aperture Uncertainty (Jitter, Ill
`The sample-to-sample variation in aperture delay.
`
`Integral Nonlinearity (INL)
`The deviation of each individual code from a line drawn from
`negative full scale through positive full scale. The point used as
`negative full scale occurs ½ LSB before the first code transition.
`Positive full scale is defined as a level 1½ LSB beyond the last
`code transition. The deviation is measured from the middle of
`each particular code to the true straight line.
`
`Differential Nonlinearity (DNL, No Missing Codes)
`An ideal ADC exhibits code transitions that are exactly 1 LSB
`apart. DNL is the deviation from this ideal value. Guaranteed
`no missing codes to 12-bit resolution indicates that all 4096
`codes must be present over all operating ranges.
`
`Offset Error
`The major carry transition should occur for an analog value
`½ LSB below VIN+ = VIN—. Offset error is defined as the deviation
`of the actual transition from that point.
`
`Gain Error
`The first code transition should occur at an analog value
`½ LSB above negative full scale. The last transition should occur
`at an analog value 1½ LSB below positive full scale. Gain error
`is the deviation of the actual difference between first and last
`code transitions and the ideal difference between first and last
`code transitions.
`
`Temperature Drift
`The temperature drift for offset error and gain error specifies
`the maximum change from the initial (25°C) value to the value
`at TMIN or
`
`Power Supply Rejection Ratio
`The change in full scale from the value with the supply at the
`minimum limit to the value with the supply at its maximum limit.
`
`Total Harmonic Distortion (THD)'
`The ratio of the rms input signal amplitude to the rms value of
`the sum of the first six harmonic components.
`
`Signal-to-Noise and Distortion (SINAD)'
`The ratio of the rms input signal amplitude to the rms value of
`the sum of all other spectral components below the Nyquist
`frequency, including harmonics but excluding dc.
`
`Effective Number of Bits (ENOB)
`The effective number of bits for a sine wave input at a given
`input frequency can be calculated directly from its measured
`SINAD using the following formula
`
`ENOB - (SINAD -1.76)
`6.02
`
`Signal-to-Noise Ratio (SNR)'
`The ratio of the rms input signal amplitude to the rms value of
`the sum of all other spectral components below the Nyquist
`frequency, excluding the first six harmonics and dc.
`
`Spurious Free Dynamic Range (SFDR)'
`The difference in dB between the rms input signal amplitude
`and the peak spurious signal. The peak spurious component
`mayor may not be a harmonic.
`
`Two-Tone SFDR'
`The ratio of the rms value of either input tone to the rms value
`of the peak spurious component. The peak spurious component
`mayor may not be an IMD product.
`
`Clock Pulse Width and Duty Cycle
`Pulse width high is the minimum amount of time that the clock
`pulse should be left in the Logic 1 state to achieve rated
`performance. Pulse width low is the minimum time the clock
`pulse should be left in the low state. At a given clock rate, these
`specifications define an acceptable clock duty cycle.
`
`Minimum Conversion Rate
`The clock rate at which the SNR of the lowest analog signal
`frequency drops by no more than 3 dB below the guaranteed limit.
`
`Maximum Conversion Rate
`The clock rate at which parametric testing is performed.
`
`Output Propagation Delay (tPD)
`The delay between the clock rising edge and the time when all
`bits are within valid logic levels.
`
`Out-of-Range Recovery Time
`The time it takes for the ADC to reacquire the analog input
`after a transition from 10% above positive full scale to 10%
`above negative full scale, or from 10% below negative full scale
`to 10% below positive full scale.
`
`'AC specifications maybe reported in dBc (degrades as signal levels are
`lowered) or in dBFS (always related back to converter full scale).
`
`Rev. C I Page of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 8
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
`
`OTR
`
`MODE
`
`SENSE
`
`VREF
`
`REFB
`
`REFT
`
`AVDD
`
`AGND
`
`VIN-
`
`VIN-
`
`AGND
`
`AVDD
`
`CLK
`
`PDWN
`
`Oil (MSS)
`
`DID
`
`09
`
`OS
`
`DRVDD
`
`DGND
`
`07
`
`06
`
`06
`
`04
`
`03
`
`02
`
`Dl
`
`DO (LSB)
`
`03060-0-021
`
`Figure 3.28-Lead TSSOP
`
`DNC I
`CLK 2
`DNC 3
`PDWN 4
`DNC 6
`DNC 6
`(LSB) DO 7
`Dl B
`
`00 00 5
`I + ZOU..ia.
`>oo>iuw
`
`.1 LI LI
`
`(
`AD9236
`TOP VIEW
`(Not to Scale)
`
`P
`
`0) 0,-Nm4.n ID
`
`1.1 1, fl lb ID I. 0°
`000000 z0
`0>
`
`24 VREF
`23 SENSE
`22 MODE
`21 OTR
`20 DII (MSB)
`19 DID
`18 09
`17 05
`
`NOTES
`1. DNC = DO NOT CONNECT.
`2 I IS RECOMMENDED THAT THE EXPOSED PADDLE BE
`SOLDERED TO THE GROUND PLANE FOR THE LFCSP. THERE
`'SAN INCREASED RELIABILITY OF THE SOLDER JOINTS, AND
`THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS
`ACHIEVED WITH THE EXPOSED PADDLE SOLDERED TO THE
`CUSTOMER BOARD.
`03060-0-021
`Figure 4.32-Lead LFCSP
`
`Mnemonic
`
`Description
`
`Table 8. Pin Function Desciptions-28-Lead TSSOP
`Pin No.
`
`Description
`
`Mnemonic
`
`2
`
`3
`4
`5
`6
`7, 12
`8,11
`9
`10
`13
`14
`15to22,
`25 to 28
`23
`24
`
`OTR
`MODE
`
`SENSE
`VREF
`REFB
`REFT
`AVDD
`AGND
`VIN+
`VIN-
`CLK
`PDWN
`DO (LSB) to
`DI (MSB)
`DGND
`DRVDD
`
`Out-of-Range Indicator
`Data Format Select and DCS
`Mode Selection
`Reference Mode Selection
`Voltage Reference Input/Output
`Differential Reference (-)
`Differential Reference (+)
`Analog Power Supply
`Analog Ground
`Analog Input Pin (+)
`Analog Input Pin (-)
`Clock Input Pin
`Power-Down Function Select
`Data Output Bits
`
`Digital Output Ground
`Digital Output Driver Supply
`
`DNC
`CLK
`PDWN
`DO (LSB) to
`DI (MSB)
`DGND
`DRVDD
`OTR
`MODE
`
`23
`24
`25
`26
`27,32
`28,31
`29
`30
`
`SENSE
`VREF
`REFB
`REFT
`AVDD
`AGND
`VIN+
`VIN-
`EP
`
`Table 9. Pin Function Descriptions-32-Lead LFCSP
`Pin No.
`1,3,5,6
`2
`4
`7 t 14,
`17 to 20
`15
`16
`21
`22
`
`Do Not Connect
`Clock Input Pin
`Power-Down Function Select
`Data Output Bits
`
`Digital Output Ground
`Digital Output Driver Supply
`
`Out -of-Range Indicator
`Data Format Select and DCS Mode
`Selection
`Reference Mode Selection
`Voltage Reference Input/Output
`Differential Reference (-)
`Differential Reference (+)
`Analog Power Supply
`Analog Ground
`Analog Input Pin (+)
`Analog Input Pin (-)
`Exposed Pad. It is recommended
`that the exposed paddle be soldered
`to the ground plane for the LFCSP.
`There is an increased reliability of the
`solderjoints, and the maximum
`thermal capability of the package is
`achieved with the exposed paddle
`soldered to the customer board.
`
`Rev. C I Page 9 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 9
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`AD 9236
`
`EQUIVALENT CIRCUITS
`
`Data Sheet
`
`AVDD
`
`ORVOD
`
`VIN+, yIN-
`
`03600-0-003
`
`Figure 5. Equivalent Analog Input Circuit
`
`Figure?. Equivalent Digital Output Circuit
`
`AVDD
`
`MODE
`
`AVDD
`
`CLK,
`PDWN
`
`03000-0-034
`
`03000-0-000
`
`Figure 6. Equivalent MODE Input Circuit
`
`Figure 8. Equivalent Digital Input Circuit
`
`Rev. C I Page 10 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 10
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`TYPICAL PERFORMANCE CHARACTERISTICS
`AVDD = 3.0 V, DRVDD = 2.5 V, sample rate = 80 MSPS, DCS disabled, TA = 25°C, 2 vp-p differential input, AIN = —0.5 dBFS,
`VREF = 1.0 v external, unless otherwise noted.
`
`AIN = -O.5dBFS
`SNR - 71.0dBc
`
`ENDS = 11.5 BITS
`
`SFDR = 93.6dBc
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`FREQUENCY (MHz)
`
`03000-0-031
`
`100
`
`90
`
`80
`
`0'l
`'S.
`48
`
`0
`z
`
`o 70
`33
`
`60
`
`50
`
`40
`-30
`
`qrnp 'dBFS)
`
`SFDR (dBc)
`
`—
`
`
`
`SNR (dBFS)
`
`SFDR = 90dB
`REFERENCE LINE
`
`SNR (dBc)
`
`-25
`
`-20
`
`-15
`
`-10
`
`-50
`
`INPUT AMPLITUDE (dBFS)
`
`03000-0-040
`
`Figure 9. Single Tone 8KFFT@ 2.5 MHz
`
`Figure 12. Single Tone SNRISFDR vs. InputAmplitude (AIN) @2.5 MHz
`
`AIN =-O.SdBFS
`SNR = 70.6dBc
`ENOB = 11.4 BITS
`SFDR = 87.8dBc
`
`100
`
`90
`
`0'l
`'S.
`0
`c 80
`0
`z
`
`M 70
`33
`
`60
`
`SFDR (dBFS)
`
`SFDR dBc)
`
`SFDR = 90dB
`REFERENCE LINE
`
`SNR (dBFS)
`
`SNR (dBc)
`
`-10
`
`-20
`
`-30
`
`-40
`
`-50
`
`-60
`
`70
`
`-80
`
`100
`
`110
`
`10
`
`AMPLITUDE (dBFS
`
`-10
`
`-20
`
`-30
`
`-40
`
`-50
`
`-60
`
`-70
`
`-80
`
`AMPLITUDE (CJBFS
`
`100
`
`18
`
`4is*id1'nh thtitn
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`FREQUENCY (MHz)
`
`03000-0-032
`
`Figure JO. Single Tone BKFFT@ 39 MHz
`
`2
`00
`
`50
`
`40
`-30
`
`-25
`
`-20
`
`-15
`
`-10
`
`-5
`
`INPUT AMPLITUDE (dBFS)
`
`
`0
`
`03000-0-049
`
`Figure 13. Single Tone SNR/SFDR vs. InputAmplitude (AIN) @39MHz
`
`SNR (01FF)
`
`I
`
`SNR (SE)
`
`SFDR (01FF)
`
`SFDR (SE)
`
`100
`
`90
`
`80
`
`70
`
`60
`
`SNR!SFDR (dBc)
`
`
`AIN = -O.5dBFS
`
`SNR - 70 ldBc
`= 11.3 BITS ENDS
`
`
`= 81.9dBc SFDR
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`FREQUENCY (MHz)
`
`03000-0-033
`
`Figure)). Single Tone BKFFT@ 70MHz
`
`50
`0
`
`20
`
`40
`
`60
`
`80
`
`100
`
`SAMPLE RATE (MSPS)
`
`03000-0-042
`
`Figure 14. SNRISFDR vs. Sample Rate @ 10 MHz
`
`Rev. C I Page 11 o136
`
`-10
`
`20
`
`-30
`
`-40
`
`-50
`
`-60
`
`70
`
`-80
`
`;0
`
`10
`
`AMPLITUDE (dBFS
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 11
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`A09236
`
`Data Sheet
`
`SFDR (dBFS) —
`
`SFDR (dBc)
`
`100
`
`90
`
`80
`
`70
`
`
`
`60
`
` SFDR90dB
`REFERENCE LINE
`
`SNRJSFDR (dBc AND dBFS
`
`AIN = -6.5dBFS
`SNR = 71.3dBFS
`SFDR = 92.5dBc
`
`SNR
`
`SNR (dBc)
`
`-10
`
`20
`
`-30
`
`-40
`
`-50
`
`-60
`
`70
`
`-80
`
`-90
`
`100
`
`I,,,
`
`AMPLITUDE (dBFS)
`
`iu.jn,,LA.iMkJtn1jmjWinnu,
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`FREQUENCY (MHz)
`
`03066-0-036
`
`50
`
`40
`-30
`
`-27
`
`-24
`
`-21
`
`-tB
`
`-15
`
`-12
`
`-9
`
`-6
`
`INPUTAMPLITUDE (dBFS)
`
`03066-0-039
`
`Figure IS. Two-Tone 8KFFT@ 3OMHzand3I MHz
`
`Figure I& Two-Tone SNR/SFDR vs. InputAmplitude @30 MHz and 3/MHz
`
`AIN =-6.SdBFS
`SNR7I.OdBFS -
`SFDR = 79.3dBc
`
`-10
`
`20
`
`-30
`
`-40
`
`-50
`
`
`
`SFDR
`
`SFDR (dBc)
`
`100
`
`90
`
`80
`
`70
`
`SNR (dBFS)
`
`SFDR = 90dB
`REFERENCE LINE
`
`SNR(dBc)
`
`-27
`
`-24
`
`-21
`
`-18
`
`-15
`
`-12
`
`INPUT AMPLITUDE (dBFS)
`
`
`
`03066-0-040
`
`60
`
`50
`
`40
`-30
`
`SNRJSFDR (dBc AND dBFS
`
`.4 LUJ#1!PPftUM
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`FREQUENCY (MHz)
`
`03066-0-037
`
`-60
`
`70
`
`00
`1,0
`
`I,,,
`
`AMPLITUDE (dBFS)
`
`Figure 16. Two-Tone 8KFFT@ 69 MHz and 70 MHz
`
`Figure 19. Two-Tone SNRISFDR vs. Inpu Amplitude @69 MHz and 70 MHz
`
`1.0
`
`0.8
`
`0.6
`
`0.4
`
`0
`d.
`—j
`
`0
`
`10
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`0
`
`—J
`z
`
`0
`
`-08
`
`1.0
`
`1024
`
`2048
`
`CODE
`
`3072
`
`4096
`
`03066-0-03a
`
`1024
`
`2048
`
`CODE
`
`3072
`
`4096
`
`03066-0-04 I
`
`Figure)?. Typical INL
`
`Figure 20. Typical DNL
`
`Rev. C Page 12 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 12
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`72.0
`
`71.5
`
`71.0
`
`70.5
`
`70.0
`Z
`69.5
`
`69.0
`
`68.5
`
`68.0
`0
`
`95
`
`90
`
`85
`
`80
`
`-40t
`
`26
`
`50
`
`76
`
`100
`
`126
`
`INPUT FREQUENCY (MHz)
`
`03000-0-045
`
`100
`
`95
`
`90
`
`85
`
`80
`
`75
`
`70
`0
`
`I;NN
`
`26
`
`50
`
`76
`
`100
`
`126
`
`INPUT FREQUENCY (MHz)
`
`03066-0-047
`
`Figure 21. SNR vs. Input Frequency
`
`Figure 24. SFDR vs. Input Frequency
`
`SFDR (DCS ON)
`
`-
`
`-
`- -
`
`'
`
`SFDR(DCS OFF)
`
`F
`I
`
`I
`I
`
`
`
`'
`S
`
`0
`
`10
`
`20
`
`-30
`
`-90
`
`100
`
`110
`
`120
`0
`
`7.68
`
`16.36
`
`23.04
`
`30.72
`
`FREQUENCY (MHz)
`
`03006-0-001
`
`Figure 25.32K FFT WCDMA Carrier @ F,, =76.8 MHz,
`Sample Rate = 61.44 MSPS
`
`SNR(DCS OFF)
`
`S
`
`\ 5
`
`t
`I
`I
`SNR(DCSON)
`
`S
`
`-
`
`S
`
`I
`
`A
`
`'I
`I
`I
`I
`I
`
`75
`
`70
`
`65
`
`60
`
`SNR/SFDR (dBc)
`
`65
`30
`
`35
`
`40
`
`55
`50
`45
`DUTY CYCLE (%)
`
`60
`
`65
`
`70
`
`03066-0-046
`
`Figure 22. SNRISFDR vs. Clock Duty Cycle
`
`S
`
`20
`
`-30
`
`-40
`
`Is.
`V 50
`
`-60
`
`100
`
`110
`
`120
`
`7.68
`
`15.36
`
`23.04
`
`30.72
`
`FREQUENCY (MHz)
`
`03=6-0-040
`
`Figure 23. 32KFFT CDMA-2000 Carrier@ FIN = 46.08 MHz Sample Rate =
`61.44 MSPS
`
`Rev. C Page 13 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 13
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`AD9236
`
`Data Sheet
`
`Referring to Figure 27, the clock signal alternately switches the
`SHA between sample mode and hold mode. When the SHA is
`switched into sample mode, the signal source must be capable
`of charging the sample capacitors and settling within one-half
`of a clock cycle. A small resistor in series with each input can
`help reduce the peak transient current required from the output
`stage of the driving source. In addition, a small shunt capacitor
`can be placed across the inputs to provide dynamic charging
`currents. This passive network creates a low-pass filter at the
`ADC's input; therefore, the precise values are dependant upon
`the application. In IF undersampling applications, any shunt
`capacitors should be reduced or removed. In combination with the
`driving source impedance, they would limit the input bandwidth.
`
`VIN
`
`YIN
`
`T
`
`5pF
`
`5pF
`
`T
`
`Figure 27. Switched-Capacitor SHA Input
`
`H
`
`For best dynamic performance, the source impedances driving
`VIN+ and VIN- should be matched such that common-mode
`settling errors are symmetrical. These errors are reduced by the
`common-mode rejection of the ADC.
`
`An internal differential reference buffer creates positive and
`negative reference voltages, REFT and REFB, that define the
`span of the ADC core. The output common mode of the
`reference buffer is set to midsupply, and the REFT and REFB
`voltages and span are defined as follows:
`
`REFT= ½(AVDD+ VREF)
`
`REFB = ½(A VDD + VREF)
`
`Span = 2 x (REFT - REFB) = 2 x VREF
`
`It can be seen from the previous equations that the REFT and
`REFB voltages are symmetrical about the midsupply voltage and,
`by definition, the input span is twice the value of the VREF voltage.
`
`The internal voltage reference can be pin strapped to fixed
`values of 0.5 V or 1.0 V, or adjusted within the same range as
`discussed in the Internal Reference Connection section.
`Maximum SNR performance is achieved with the AD9236 set
`to the largest input span of 2 V p-p. The relative SNR degradation is
`3 dB when changing from 2 vp-p mode to i vp-p mode.
`
`THEORY OF OPERATION
`The AD9236 architecture consists of a front-end sample-and-
`hold amplifier (SHA) followed by a pipelined switched capacitor
`ADC. The pipelined ADC is divided into three sections,
`consisting of a 4-bit first stage followed by eight 1.5-bit stages
`and a final 3-bit flash. Each stage provides sufficient overlap to
`correct for flash errors in the preceding stages. The quantized
`outputs from each stage are combined into a final 12-bit result
`in the digital correction logic. The pipelined architecture
`permits the first stage to operate on a new input sample, while
`the remaining stages operate on preceding samples. Sampling
`occurs on the rising edge of the clock.
`
`Each stage of the pipeline, excluding the last, consists of a low
`resolution flash ADC connected to a switched capacitor DAC
`and interstage residue amplifier (MDAC). The residue amplifier
`magnifies the difference between the reconstructed DAC output
`and the flash input for the next stage in the pipeline. One bit of
`redundancy is used in each stage to facilitate digital correction
`of flash errors. The last stage simply consists of a flash ADC.
`
`The input stage contains a differential SHA that can be ac- or
`dc-coupled in differential or single-ended modes. The output-
`staging block aligns the data, carries out the error correction,
`and passes the data to the output buffers. The output buffers are
`powered from a separate supply, allowing adjustment of the
`output voltage swing. During power-down, the output buffers
`go into a high impedance state.
`
`ANALOG INPUT AND REFERENCE OVERVIEW
`
`The analog input to the AD9236 is a differential switched
`capacitor SHA that has been designed for optimum
`performance while processing a differential input signal. The
`SHA input can support a wide common-mode range (VCM)
`and maintain excellent performance, as shown in Figure 26. An
`input common-mode voltage of midsupply minimizes signal-
`dependant errors and provides optimum performance.
`
`SFDR (2.5MHz)
`
`/C
`
`- - - - - -
`
`SFDR (39MHz)
`
`SNR (2.5MHz)
`
`SNR (39MHz)
`
`6
`
`10
`
`15
`
`20
`
`25
`
`30
`
`COMMON-MODE LEVEL (V)
`
`03066-0-016
`
`Figure 26. SNR, SFDR vs. Common-Mode Level
`
`100
`
`95
`
`90
`
`85
`
`80
`
`75
`
`70
`
`65
`
`60
`
`55
`
`SO
`0.5
`
`SNISFDR (dBc
`
`Rev. C I Page 14 of 36
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1014 Page 14
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01219
`
`

`

`Data Sheet
`
`AD9236
`
`The SHA can be driven from a source that keeps the signal
`peaks within the allowable range for the selected reference
`voltage. The minimum and maximum common-mode input
`levels are defined as:
`
`2V p-p
`
`VCMMIN -
`
`VREF
`2
`
`VCM -
`
`(A VDD + VREF)
`2
`
`The minimum common-mode input level allows the AD9236 to
`accommodate ground referenced inputs.
`
`Although optimum performance is achieved with a differential
`input, a single-ended s