UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`v.
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 8,487,659
`
`_______________
`Inter Partes Review No. IPR2020-01219
`____________________________________________________________
`
`SECOND DECLARATION OF DR. DOUGLAS HOLBERG
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`TABLE OF CONTENTS
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`Page
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`2.
`
`V.
`
`INTRODUCTION .......................................................................................... 1
`I.
`EXPERIENCE AND QUALIFICATIONS .................................................... 1
`II.
`III. BASIS FOR OPINION ................................................................................... 1
`IV. YOSHIOKA IS PRIOR ART ......................................................................... 2
`A.
`The Claimed ’659 Invention Was Not Conceived Prior To
`Yoshioka ............................................................................................... 2
`1.
`The Design Review Does Not Disclose the Adaptive
`Delay Device Claimed in the ’659 Patent .................................. 2
`ADI and its declarants’ mapping of ’659 claims to ADI’s
`Design Review is purposely misleading and inconsistent ......... 4
`ADI Fails To Establish Reduction To Practice .................................. 28
`B.
`DR. HANUMOLU MISCHARACTERIZES YOSHIOKA AND
`PETITIONER’S ARGUMENTS .................................................................. 31
`A.
`Yoshioka’s Adaptive Delay Device Does Not Respond to PVT
`Effects on Only Itself .......................................................................... 31
`Petitioner Did Not Make An Inherency Argument ............................ 34
`B.
`Petitioner Established Motivation to Combine .................................. 36
`C.
`VI. DR. HANUMOLU MISCHARACTERIZES AJIT AND
`PETITIONER’S ARGUMENTS .................................................................. 39
`A.
`Dr. Hanumolu’s Waveforms Are Inconsistent With Ajit’s
`Express Disclosures ............................................................................ 40
`B. My Simulations Accurately Convey Ajit’s Teachings ...................... 49
`C.
`Even Dr. Hanumolu’s Simulated Results Show an Inverse
`Response ............................................................................................. 57
`Ajit In Combination With AAPA Teaches Claims 1 And 5 .............. 60
`
`D.
`
`-i-
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`IPR2020-01219
`I.
`INTRODUCTION
`
`1.
`
`My name is Dr. Douglas R. Holberg. I have been retained by
`
`counsel for Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. (“Xilinx” or “Petitioner”)
`
`as a technical expert in connection with the proceeding identified above. I have
`
`been asked to provide my opinions and views on the materials I have reviewed in
`
`relation to the ’659 patent (Ex. 1001), including the declarations of Dr. Pavan
`
`Hanumolu and Mr. Ronald Kapusta (Exs. 2001, 2033, 2044.) I submit this second
`
`declaration in support of Xilinx’s Petition and Reply in this proceeding against
`
`Analog Devices, Inc.’s (“ADI” or “Patent Owner”) ’659 patent.
`
`2.
`
`I am being compensated at my normal rate, plus reimbursement
`
`for expenses, for my analysis. My compensation does not depend on the content of
`
`my opinions or the outcome of this proceeding.
`
`II.
`
`EXPERIENCE AND QUALIFICATIONS
`
`3.
`
`I refer to the description of my background in my previous
`
`declaration (Ex. 1002, ¶¶ 3-13).
`
`III. BASIS FOR OPINION
`
`4.
`
`My opinions and views set forth in this declaration are based on
`
`my education, training, and experience in the relevant field, as well as the material
`
`I reviewed in this case, and the scientific knowledge regarding the same subject
`
`matter that existed prior to the earliest effective filing date of the ’659 patent.
`1
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`5.
`
`I have considered information from various sources in forming
`
`my opinions. Besides drawing from my experience as an electrical engineer in the
`
`electronics field for over 40 years, I also have reviewed the following documents:
`
`(a) the ’659 patent (Ex. 1001), (b) the prosecution file history of the ’659 patent
`
`(Ex. 1003), (c) all prior art references cited herein (including all prior art relied
`
`upon in each ground of the inter partes review petition), and (d) the other
`
`documents and references as cited herein. I also reviewed an initial declaration
`
`and a second declaration prepared by Dr. Pavan Hanumolu (Exs. 2001, 2044) and a
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`declaration prepared by Mr. Ronald Kapusta (Ex. 2043). This declaration is in
`
`response to ADI’s Patent Owner’s Response and its declarants arguments in
`
`support of ADI’s Response.
`
`IV. YOSHIOKA IS PRIOR ART
`
`A.
`
`The Claimed ’659 Invention Was Not Conceived Prior To
`Yoshioka
`The Design Review Does Not Disclose the Adaptive Delay
`1.
`Device Claimed in the ’659 Patent
`
`6.
`
`Dr. Hanumolu incorrectly claims that “the Design Review
`
`describes the components of a comparator, including a preamplifier and a latch,
`
`exactly as described in the ’659 patent.” (Ex. 2044, ¶ 22 (emphasis added).) A
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`simple comparison of the comparators shows that this is false. From the
`
`2
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`IPR2020-01219
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`comparison, the adaptive delay device that counteracts PVT effects, which is the
`
`entire purpose of the ’659 patent, is missing from ADI’s Design Review circuit
`
`(see orange shading below).
`
`’659 Patent, Fig. 3 (Annotated)
`
`ADI Design Review, Fig. 1 (Annotated)
`
`7.
`
`Moreover, the Design Review circuit does not appear anywhere in
`
`the ’659 patent as an embodiment, despite purportedly being reduced to practice on
`
`January 31, 2011 in Gecko_R0—nearly four months before the ’659 patent
`
`application filing date. (See Ex. 2044, ¶ 81.)
`
`3
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`IPR2020-01219
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`8.
`
`As I explain below, the mapping by ADI and its declarants, Dr.
`
`
`
`Hanumolu and Mr. Kapusta, for establishing an earlier conception date does not
`
`work.
`
`2.
`
`ADI and its declarants’ mapping of ’659 claims to ADI’s
`Design Review is purposely misleading and inconsistent
`
`a.
`
`Unlike RESET_DEL in the ’659 Patent, qTIMER does
`not control latching
`
`9.
`
`As shown above, the adaptive delay (e.g., 330 of the ’659 patent)
`
`is entirely missing from ADI’s Design Review (see red arrow). To cover this
`
`deficiency, ADI and its declarants argue that the timer circuit that generates qTIMER
`
`in the regenerative latch is the adaptive delay. But this argument is inconsistent
`
`with the ’659 patent.
`
`10.
`
`In the ’659 patent, RESET is a first control signal that is input into
`
`the adaptive delay (shown in red in Fig. 3 below), and RESET_DEL is the second
`
`control signal that is output (purple). (See Ex. 1001, 3:17-19.) RESET_DEL
`
`controls when the latch (e.g., 320) captures the amplified signal from the
`
`preamplifier (e.g., 310). The ’659 patent clearly teaches that RESET_DEL is
`
`applied to latch and that RESET_DEL holds latch in a known state until
`
`releasing. (See, e.g., Ex. 1001, 1:24-27, 5:34-35.)
`
`
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`4
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`
`
`(Ex. 1001, Fig. 3 (annotated).)
`In ADI’s Design Review, the first control signal “reset” (red) is
`11.
`
`applied to Pre-Amp 1, Pre-Amp 2, and Regen. Latch at the same time (shown in
`
`red below). As shown below, “reset” is connected directly to the latch. For at least
`
`this reason, there is no signal that corresponds to of RESET_DEL in the Design
`
`Review circuit.
`
`
`As shown in Figs. 7 of the Design Review, the regenerative latch
`
`12.
`
`stops being held in a known state and begins the comparator decision phase when
`5
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`qRESET—which is not delayed—opens (i.e., disconnects) the switches highlighted in
`
`
`
`red below.
`
`
`
`13.
`
`Because ADI and its declarants cannot map qRESET to
`
`RESET_DEL in the ’659 patent, he tries to argue that qTIMER is the second control
`
`signal. First, the regenerative latch in Figure 7 of the Design Review is not an
`
`embodiment disclosed in the ’659 patent. The latch disclosed in the ’659 patent
`
`does not include an input for the qTIMER and an input for the qRESET signal. (See,
`
`e.g., Ex. 1001, Figs. 3 and 7.) Second, qTIMER does not control when the amplified
`
`input signal is latched by the regenerative latch because qTIMER does not hold latch
`
`in a known state. In contrast, the RESET_DEL signal in the ’659 patent controls
`
`
`
`6
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`when an amplified signal is latched by the latch. (Ex. 1001, 2:65-67, 5:34-35,
`
`
`
`7:26-28.) Instead, qTIMER simply adds additional current to tip the outputs
`
`according to a direction already initiated (i.e., by qRESET) by the latch inputs (+in
`
`and –in). Regardless of what qTIMER is, there is no latching, regeneration, nor
`
`releasing of latch output unless qRESET disconnects (opens) the switches highlighted
`
`in red in Figure 7 above. In fact, Mr. Kapusta states that qRESET (i.e., not qTIMER) is
`
`the signal that causes latching, regeneration, or releasing of latch output. (Ex.
`
`2006/2035, 10 (“After the reset signal falls, signaling the beginning of the
`
`comparator decision phase….”).) Even if qTIMER is off (i.e., stays zero at all times)
`
`or removed altogether, the latch would nonetheless latch the amplified input signal
`
`or regenerate as dictated by qRESET. For at least these reasons, qTIMER is not
`
`RESET_DEL in the ’659 patent.
`
`14.
`
`Figs. 4 and 6 of the Design Review shows that the pre-amplifiers
`
`(i.e., Pre-Amp 1, Pre-Amp 2) are connected to the same qRESET signal (shown with
`
`red arrows below), meaning the same signal is connected to the pre-amplifiers and
`
`the latch with no delay. There is therefore no “latch responsive to a second control
`
`signal” in the Design Review, as required by claims 1-4 of the ’659 patent. As I
`
`discuss further below, ADI and Dr. Hanumolu appear to be mapping qrst_time in
`
`ADI’s schematics to “RESET_DEL” of the ’659 patent. But the qrst_time signal
`
`does not even connect to the latch.
`
`
`7
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`8
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`b.
`
`ADI and its declarants ignore circuitry in ADI’s
`Design Review when mapping it to the ’659 patent
`
`
`
`15.
`
`The side-by-side comparison by ADI and its declarants shows that
`
`RESET_DEL in the ’659 patent is not qTIMER in ADI’s Design Review. They
`
`ignore circuitry in Figure 8 of its Design Review (see purple-shaded portion
`
`emphasized by red arrow on right).
`
`
`
`(Ex. 2044, 20 (green circular annotations and purple shaded box added).)
`
`16.
`
`As shown with the green-highlighted nodes, RESET_DEL in
`
`Figure 4 of the ’659 maps to the green node immediately to the left of the purple-
`
`shaded portion of Figure 8 of ADI’s Design Review—not to qTIMER. Dr. Hanumolu
`
`admits this. (Ex. 2044, ¶ 26 (“The output signal qrst_time3b [qTIMER] is actually a
`
`delayed version of the output signal qrst_time (orange), which is the signal that
`
`corresponds to the “reset_del” signal in Figure 4 of the ’659 patent (as I show
`
`
`
`9
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`below).”) (emphasis added).) qrst_time (the green node) cannot correspond to the
`
`
`
`RESET_DEL signal, which is connected to a latch according to the ’659 patent,
`
`because it is not connected to a latch. The screenshot of the latch portion of the
`
`comparator schematic in Ex. 2017 shows that qrst_time is not an input to the latch.
`
`(See also Exs. 2014-2016.)
`
`
`ADI’s schematics and Dr. Hanumolu show that the purple-shaded
`
`17.
`
`portion is in fact two inverters followed by a 3-input NOR gate.
`10
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`
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`(Ex. 2044, ¶ 26 (green circular annotation added showing node (“qrst_time,” which
`
`allegedly corresponds to the “RESET_DEL” signal in Figure 4 of the ’659 patent)
`
`and purple annotations added showing two inverters and 3-input NOR gate
`
`following “RESET_DEL”).)
`
`18.
`
`The existence of the inverters and the 3-input NOR gate shows
`
`that ADI’s schematics and Design Review do not correspond with the ’659 patent.
`
`ADI’s schematics and the Design Review do not even correspond with each other.
`
`As shown below, ADI and its declarants claim that “[t]he blue highlighted portion
`
`matches Figure 8 of the Design Review.” However, ADI and its declarants ignore
`
`the second inverter and the 3-input NOR gate (green) between the inverter (red)
`
`and output qrst_time3b (yellow). (See also Ex. 2044, 26-27.)
`
`
`
`11
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`(Response, 21 (blue dotted line added to Figure 8, red, green, and yellow shading
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`added to both Figure 8 and schematics).)
`
`
`
`12
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`19.
`
`ADI and its declarants take different positions on the location of
`
`
`
`qTIMER is in ADI’s schematics. Based on ADI and Dr. Hanumolu’s mapping
`
`(reproduced above), qTIMER is the output of the first inverter (red), which
`
`corresponds to internal signal qrst_timeb in the schematics, and also qrst_time3b.
`
`But it cannot be both because the blue portions correspond to different circuit
`
`nodes.
`
`20.
`
`The only evidence Dr. Hanumolu offers to purportedly show an
`
`inverse response to PVT is Figure 28 of the Design Review, which shows the delay
`
`between qrst (red highlighting below) and qrst_time3b (blue highlighting), not
`
`qrst_timeb.
`
`
`
`13
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`
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`(Ex. 2006/2035, 32 (red, blue highlighting added).)
`
`
`
`21.
`
`The two inverters and 3-input NOR gate following qrst_time—
`
`three separate logic gates that qrst_time must pass through are not a simple delay
`
`between qrst_time and qrst_time3b.
`
`22.
`
`First, qrst_time3b cannot be a simple delay of qrst_time because
`
`they are opposite logic levels. Dr. Hanumolu assumes that the other two inputs
`
`(i.e., qrst, qaz_bb) to the NOR gate are low such that the NOR gate operates as an
`
`inverter. (See Ex. 2044, ¶ 26, FN1 (“This assumes that qrst and qaz_bb are low
`
`prior to the time that the qrst_timebb signal goes low.”). Dr. Hanumolu cites to
`
`nothing to support this assumption, which is also an incorrect assumption. Dr.
`
`Hanumolu’s assumption cannot be true because the purple-shaded portion does not
`
`always function as an inverter, so it cannot be simply replaced by an inverter. For
`
`example, when qrst goes high, the purple-shaded portion no longer functions like
`
`an inverter because qrst causes the output of the NOR gate to go low. There is no
`
`information in Figure 8 of the Design Review to reflect this behavior. Accepting
`
`that Dr. Hanumolu’s assumptions as true, due to inversions through three inverting
`
`gates, when qrst_time is low, qrst_time3b is high.
`
`
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`14
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`
`
`(Ex. 2044, ¶ 26 (red, green, purple annotations added).)
`
`23.
`
`Figure 28 of ADI’s Design Review further confirms that qrst_time
`
`and qrst_time3b are opposite logic levels. As shown in the schematic above, qrst
`
`(red) and qrst_time (orange) have the same logic level (low). When qrst goes from
`
`high to low (red below), qrst_time3b goes from low to high (blue below)—the
`
`signals thus have opposite polarities. ADI and its declarants’ assertion that “the
`
`voltage on the output qTIMER signal matches the voltage on the input qRESET signal”
`
`(see, e.g., Ex. 2044, 40 (mapping to claim 11)) is incorrect and inconsistent with
`
`evidence ADI and its declarants rely upon.
`
`
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`15
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`24.
`
`A simple comparison between the above simulations and
`
`waveforms of the claimed adaptive delay shows this discrepancy (falling (e.g., in
`
`red) to rising (e.g., in blue) in the simulations vs. falling to falling in Fig. 5).
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`
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`16
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`(Ex. 1001, Fig. 5 (cropped to show RESET and RESET_DEL signals).)
`
`
`
`25.
`
`Second, each logic gate (e.g., the two inverters, the NOR gate) has
`
`its own PVT effect that would impact the timer circuit’s overall response to PVT
`
`effects. Dr. Hanumolu acknowledged that the two inverters and NOR gate would
`
`actually respond proportionally to PVT effects. (Ex. 2044, ¶ 26 (“[A] POSITA
`
`would have understood that the two extra inverter delays and the NOR gate delay
`
`between qrst_time and qrst_time3b would actually respond to PVT effects in the
`
`same manner as the latch” such that “timer simulation results (based on
`
`qrst_time3b) actually show less of an inverse response to PVT effects….”)
`
`(emphasis added).) This means that even if the delay between qrst (red in
`
`schematics) and qrst_time (orange) is inverse to PVT effects, the two inverters and
`
`the NOR gate that follow respond proportionally to PVT effects and would impact
`
`the overall delay between qrst (red) and qrst_time3b (blue) because the overall
`
`delay includes a component that is purportedly inverse to PVT effects (i.e., qrst to
`
`qrst_time) and a component that is proportional to PVT effects (i.e., delay through
`
`the two inverters and the NOR gate). ADI and its declarants have not shown that
`
`the overall delay due to PVT effects is inversely proportional. Indeed, it is not, as
`
`discussed in Section IV.A.2.c.
`
`26.
`
`There are additional differences. Capacitor 425 in Figure 4 of the
`
`’659 patent is a fixed capacitor. In contrast, the load capacitor in ADI’s Design
`17
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`Review is tunable (capacitors highlighted in red below). (See Ex. 2006/2035, 23
`
`
`
`(“you might notice that the load capacitor for the charging circuit is
`
`programmable”).) To respond inversely to PVT effects, the Design Review’s
`
`tunable, digitally-controlled capacitor would need to be programmed to implement
`
`background calibration logic. This tunable, digitally-controlled capacitor will
`
`affect the delay of the timer circuit, whereas the adaptive delay of the ’659 patent
`
`does not use a tunable cap to adjust its delay.
`
`27.
`
`The impedance element 430 in Figure 4 of the ’659 patent is a
`
`constant load Z (see, e.g., Ex. 1001, 3:61-62 (“The impedance element 431 and
`
`430 may be a resistor, transistor or some other device that may function as a
`
`current source.”). In contrast, in the Design Review, there is a switched current
`
`source (current sources highlighted in blue below). That is, the current source
`
`would not be always be connected, so the switched current source cannot be a
`
`constant load.
`
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`18
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`28.
`
`As I explained above, I conclude that the differences in the circuit
`
`structures and ADI and its declarants’ unrealistic assumptions show that the
`
`comparator in the Design Review is unrelated to the ’659 patent. I understand
`
`from counsel that to show conception, ADI must show a complete conception of
`
`every element of the claims of the ’659 patent. ADI and its declarants have failed
`
`to do so.
`
`29.
`
`For example, for claim 1, on which claims 2 through 4 depend,
`
`ADI and its declarants fail to map the Design Review circuit to the “latch
`
`responsive to a second control signal,” “a delay element, having an input for the
`
`first control signal and an output for the second control signal,” and “the delay
`
`element having a circuit structure to adaptively increase or decrease delay
`
`propagation of the first control signal in a manner that counteracts PVT effects
`
`present in other components of the comparator.” As I explained above, there is no
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`second control signal, so the claimed latch and delay element do not exist in the
`
`
`
`Design Review circuit. Furthermore, the additional inverters and NOR gate (as I
`
`explained above) and ADI’s simulation data (as explained below) show that the
`
`Design Review timer circuit does not “counteract[] PVT effects.”
`
`30.
`
`As another example, for claims 2 and 5, ADI and its declarants
`
`fail to map the Design Review circuit to “the capacitive element charges to a
`
`threshold voltage that actuates the output switch which changes an output signal.”
`
`Dr. Hanumolu is not able to identify the “output signal” in the Design Review
`
`circuit.
`
`31.
`
`As yet another example, for claim 5, ADI and its declarants fail to
`
`map the Design Review circuit to “an adaptive delay device having an input for
`
`receiving a control signal and an output connected to the comparator,” and “the
`
`adaptive delay device is configured to respond inversely to the response of other
`
`circuit components forming the successive approximation register analog-to-digital
`
`converter.” As I explained above, the Design Review’s pre-amplifiers and latch
`
`are controlled by the same reset signal. Therefore, the Design Review does not
`
`have an adaptive delay device having an output connected to the comparator.
`
`Furthermore, the additional inverters and NOR gate (as I explained above) and
`
`ADI’s simulation data (as explained below) show that the Design Review timer
`
`circuit does not “respond inversely to the response of other circuit components.”
`20
`
`
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`
`32.
`
`As yet another example, for claim 9, ADI and its declarants fail to
`
`
`
`map the Design Review circuit to “delays between the state change of the input
`
`signal and the generated output voltage vary inversely in response to PVT effect on
`
`other components of the integrated circuit.” The additional inverters and NOR
`
`gate (as I explained above) and ADI’s simulation data (as explained below) show
`
`that the Design Review timer circuit does not “vary inversely in response to PVT
`
`effect on other components of the integrated circuit.”
`
`33.
`
`As yet another example, for claim 11, ADI and its declarants fail
`
`to map the Design Review circuit to “the generated output voltage is a same
`
`voltage as the input signal.” As I explained above, qRESET and qTIMER have opposite
`
`transitions.
`
`c.
`
`The circuit in ADI’s Design Review does not respond
`inversely to PVT effects, as required by the claims
`
`34.
`
`Even assuming that the circuit in ADI’s Design Review is related
`
`to that in the ’659 patent (it is not), all claims of the ’659 patent recite an adaptive
`
`delay device that responds inversely to PVT effects. ADI’s own evidence shows
`
`that the comparator in ADI’s Design Review does not respond inversely to PVT
`
`effects.
`
`35.
`
`According to ADI and its declarants, Table 6 of the Design
`
`Review “shows the regeneration time constant ‘tau’ of the comparator latch – a
`
`
`
`21
`
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`IPR2020-01219
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`small value of tau results in a fast decision, whereas a large value of tau results in a
`
`
`
`slow decision.” (Ex. 2044, ¶ 25.) ADI and its declarants rely on the qTIMER “pulse
`
`width” to show that “[t]he comparator performance is exactly the opposite of the
`
`response of the latch” to PVT effects. (Id.) To show an inverse response, a
`
`smaller tau (faster decision) would result in a bigger “pulse width” (longer delay),
`
`whereas a bigger tau (slower decision) would result in a smaller “pulse width”
`
`(shorter delay).
`
`36.
`
`ADI and its declarants appear to define the qTIMER “pulse width”
`
`as the time between falling edge of qrst (red below) and the rising edge of
`
`qrst_time3b (blue below).
`
`
`
`22
`
`
`
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`
`37.
`
`As discussed in detail above, even assuming qrst (red)
`
`corresponds with RESET in the ’659 patent, according to ADI and its declarants’
`
`mapping, qrst_time (orange, emphasized by green circular annotation below)—not
`
`qrst_time3b (blue)—would correspond with RESET_DEL1. Figure 28 is not
`
`illustrating the delay in the ’659 patent’s adaptive delay device because it does not
`
`illustrate qrst_time.
`
`
`
`
`
`38.
`
`But even assuming that the “pulse width” in Figure 28 reflects the
`
`delay of an adaptive delay device (it does not), the response between tau and the
`
`delay is not inverse. ADI and Dr. Hanumolu cherry-pick two corners of the
`
`
`
` 1
`
` But as I discussed, there is no delayed reset signals in the Design Review circuit
`
`corresponding to RESET_DEL of the ’659 patent because the pre-amplifiers and
`
`the latch are connected to the same reset signal.
`
`
`
`23
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`circuit, cases 62 and 64, in Figure 28 of the Design Review to purportedly show an
`
`
`
`inverse relationship between tau and the “pulse width.” But comparing case 63
`
`with case 67 illustrates a proportional, not inverse, relationship.
`
`39.
`
`Case 63 (highlighted yellow below) has the following properties:
`
`ssss, -40C, 1.32V (521ps). (Ex. 2006/2035, 32.) “ssss” indicates a slow process
`
`corner. Typically, a POSITA would understand that the letters represent speed
`
`(slow or fast) as a consequence of NMOS transistor process, PMOS transistor
`
`process, process resistance (e.g., parasitic resistance), and process capacitance
`
`(e.g., parasitic capacitance). Case 67 (green) has same temperature (-40C) and the
`
`same voltage (1.32V) as case 63. The only difference is that case 67 is at a
`
`different process corner (i.e., “ffff,” a fast process corner). (Ex. 2006/2035, 32
`
`(cases 63 and 67 highlighted below).)
`
`
`
`24
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`
`
`
`(Ex. 2006/2035, 32 (yellow, green highlighting added).)
`The corresponding tau values for cases 63 (yellow) and 67 (green)
`40.
`
`are shown in annotated Table 6 of ADI’s Design Review below.
`
`
`
`
`
`
`
`25
`
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`
`41.
`
`Comparing cases 63 and 67, case 63 has a smaller tau (27ps v.
`
`31ps). For an inverse response, the “pulse width” for case 63 should be bigger
`
`than that for case 67 (i.e., longer delay to counteract faster decision). Figure 28 of
`
`the Design Review, however, shows that the “pulse width” for case 63 is smaller
`
`than that for case 67 (521ps v. 712ps). This shows a proportional response
`
`between tau and “pulse width.”
`
`42.
`
`As another example, comparing cases 62 and 63 also shows a
`
`proportional response:
`
`
`
`
`
`
`
`43.
`
`Case 62 has a larger tau than case 63 (42ps v. 27ps). Figure 28 of
`
`the Design Review shows that the “pulse width” for case 62 is larger than that for
`
`case 63 (616ps v. 521ps)—also a proportional response between tau and “pulse
`
`width.” These comparisons are merely examples.
`
`
`
`26
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`
`44.
`
`I compare all of the Design Review data and identify the many
`
`other instances of proportional responses to PVT and not inverse. I start by
`
`comparing the differences in tau between the different cases, as shown in the table
`
`below. “+” indicates a relative increase in tau between two corresponding cases,
`
`and “-” means a relative decrease in tau between two corresponding cases.
`
`Sim
`
`61
`62
`63
`64
`65
`66
`67
`68
`69
`
`Tau(ps)
`36
`40
`27
`51
`35
`42
`31
`55
`39
`
`61
`36
`
`-
`+
`-
`+
`-
`+
`-
`-
`
`62
`40
`
`+
`
`+
`-
`+
`-
`+
`-
`+
`
`63
`27
`
`-
`-
`
`-
`-
`-
`-
`-
`-
`
`64
`51
`
`+
`+
`+
`
`+
`+
`+
`-
`+
`
`65
`35
`
`-
`-
`+
`-
`
`-
`+
`-
`-
`
`66
`42
`
`+
`+
`+
`-
`+
`
`+
`-
`+
`
`67
`31
`
`-
`-
`+
`-
`-
`-
`
`-
`-
`
`68
`55
`
`+
`+
`+
`+
`+
`+
`+
`
`+
`
`69
`39
`
`+
`-
`+
`-
`+
`-
`+
`-
`
`45.
`
`I then compare the differences between the “pulse width” times.
`
`
`
`
`
`“+” indicates a relative increase in “pulse width” times between two corresponding
`
`cases, and “-” means a relative decrease in “pulse width” times between two
`
`corresponding cases.
`
`Sim
`
`Delay(ps)
`450
`616
`521
`302
`311
`714
`712
`280
`271
`
`61
`62
`63
`64
`65
`66
`67
`68
`69
`
`61
`450
`
`-
`-
`+
`+
`-
`-
`+
`+
`
`62
`616
`
`+
`
`+
`+
`+
`-
`-
`+
`+
`
`
`
`63
`521
`
`+
`-
`
`+
`+
`-
`-
`+
`+
`
`27
`
`64
`302
`
`-
`-
`-
`
`-
`-
`-
`+
`+
`
`65
`311
`
`-
`-
`-
`+
`
`-
`-
`+
`+
`
`66
`714
`
`+
`+
`+
`+
`+
`
`+
`+
`+
`
`67
`712
`
`+
`+
`+
`+
`+
`-
`
`+
`+
`
`68
`280
`
`-
`-
`-
`-
`-
`-
`-
`
`+
`
`69
`271
`
`-
`-
`-
`-
`-
`-
`-
`-
`
`
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1018 Page 29
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`IPR2020-01219
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`
`46.
`
`This is summarized in the table below. An “X” indicates that a
`
`
`
`comparison between two corresponding cases shows a proportional response to
`
`PVT effects (i.e., the corresponding tau and “pulse width” time comparisons are
`
`both “+” or “-”). For example, the comparison between case 62 and case 65
`
`shows a proportional response to PVT effects. As shown by the significant amount
`
`of “X’s,” there are many other instances of proportional responses to PVT.
`
`64
`
`61
`
`X
`
`X
`X
`
`62
`X
`
`X
`
`X
`X
`
`63
`
`X
`
`X
`X
`
`65
`X
`X
`
`X
`
`66
`X
`X
`X
`
`X
`
`X
`
`Sim
`61
`62
`63
`64
`65
`66
`67
`68
`69
`
`47.
`
`67
`
`68
`
`X
`
`X
`
`69
`
`X
`
`X
`
`X
`
`X
`
`X
`X
`X
`X
`ADI’s own evidence clearly illustrates that the circuit in ADI’s
`
`
`
`Design Review circuit