W25Q64FW
`
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`
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`
`1.8V 64M-BIT
`SERIAL FLASH MEMORY WITH
`DUAL/QUAD SPI & QPI
`
`
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`
`Publication Release Date: March 25, 2013
` Preliminary - Revision D
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 1
`
`

`

`W25Q64FW
`
`
`
`Table of Contents
`
`1.
`
`2.
`
`3.
`
`GENERAL DESCRIPTIONS ............................................................................................................. 5
`
`FEATURES ....................................................................................................................................... 5
`
`PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 6
`
`3.1
`3.2
`3.3
`3.4
`3.5
`3.6
`3.7
`3.8
`3.9
`
`Pin Configuration SOIC / VSOP 208-mil .............................................................................. 6
`Pad Configuration WSON 6x5-mm / 8x6-mm ...................................................................... 6
`Pin Description SOIC/VSOP 208-mil, WSON 6x5-mm / 8x6-mm ........................................ 6
`Pin Configuration SOIC 300-mil ........................................................................................... 7
`Pin Description SOIC 300-mil ............................................................................................... 7
`Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8
`Ball Description TFBGA 8x6-mm ......................................................................................... 8
`Ball Configuration WLBGA ................................................................................................... 9
`Ball Description WLBGA ...................................................................................................... 9
`
`4.
`
`PIN DESCRIPTIONS ...................................................................................................................... 10
`
`5.
`
`6.
`
`Chip Select (/CS) ................................................................................................................ 10
`4.1
`Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10
`4.2
`4.3 Write Protect (/WP)............................................................................................................. 10
`4.4
`HOLD (/HOLD) ................................................................................................................... 10
`4.5
`Serial Clock (CLK) .............................................................................................................. 10
`4.6
`Reset (/RESET) .................................................................................................................. 10
`
`BLOCK DIAGRAM .......................................................................................................................... 11
`
`FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
`
`6.1
`
`SPI / QPI Operations .......................................................................................................... 12
`6.1.1 Standard SPI Instructions ..................................................................................................... 12
`6.1.2 Dual SPI Instructions ............................................................................................................ 12
`6.1.3 Quad SPI Instructions ........................................................................................................... 13
`6.1.4 QPI Instructions .................................................................................................................... 13
`6.1.5 Hold Function ........................................................................................................................ 13
`6.1.6 Software Reset & Hardware /RESET pin .............................................................................. 14
`
`6.2 Write Protection .................................................................................................................. 15
`6.2.1 Write Protect Features .......................................................................................................... 15
`
`7.
`
`STATUS AND CONFIGURATION REGISTERS ............................................................................ 16
`
`7.1
`
`Status Registers ................................................................................................................. 16
`7.1.1 Erase/Write In Progress (BUSY) – Status Only .................................................................... 16
`7.1.2 Write Enable Latch (WEL) – Status Only .............................................................................. 16
`7.1.3 Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable .................................... 16
`
`
`- 1 -
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 2
`
`

`

`W25Q64FW
`
`
`7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable ........................................... 17
`7.1.5 Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable ........................................... 17
`7.1.6 Complement Protect (CMP) – Volatile/Non-Volatile Writable ................................................ 17
`7.1.7 Status Register Protect (SRP1, SRP0) – Volatile/Non-Volatile Writable ............................... 17
`7.1.8 Erase/Program Suspend Status (SUS) – Status Only .......................................................... 18
`7.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) – Volatile/Non-Volatile OTP Writable ...... 18
`7.1.10 Quad Enable (QE) – Volatile/Non-Volatile Writable ............................................................ 18
`7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable .......................................... 19
`7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ............................. 19
`7.1.13 HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable ................... 19
`7.1.14 Reserved Bits – Non Functional ......................................................................................... 19
`7.1.15 W25Q64FW Status Register Memory Protection (WPS = 0, CMP = 0) .............................. 20
`7.1.16 W25Q64FW Status Register Memory Protection (WPS = 0, CMP = 1) .............................. 21
`7.1.17 W25Q64FW Individual Block Memory Protection (WPS=1) ................................................ 22
`
`8.
`
`INSTRUCTIONS ............................................................................................................................. 23
`
`8.1
`
`8.2
`
`Device ID and Instruction Set Tables ................................................................................. 23
`8.1.1 Manufacturer and Device Identification ................................................................................. 23
`8.1.2
`Instruction Set Table 1 (Standard/Dual/Quad SPI Instructions) ............................................ 24
`8.1.3
`Instruction Set Table 2 (Standard/Dual/Quad SPI Instructions) ............................................ 25
`8.1.4
`Instruction Set Table 3 (QPI Instructions) ............................................................................. 26
`
`Instruction Descriptions ...................................................................................................... 28
`8.2.1 Write Enable (06h) ................................................................................................................ 28
`8.2.2 Write Enable for Volatile Status Register (50h) ..................................................................... 28
`8.2.3 Write Disable (04h) ............................................................................................................... 29
`8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h) ............... 29
`8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ............... 30
`8.2.6 Read Data (03h) ................................................................................................................... 33
`8.2.7 Fast Read (0Bh) ................................................................................................................... 34
`8.2.8 Fast Read Dual Output (3Bh) ............................................................................................... 36
`8.2.9 Fast Read Quad Output (6Bh) .............................................................................................. 37
`8.2.10 Fast Read Dual I/O (BBh) ................................................................................................... 38
`8.2.11 Fast Read Quad I/O (EBh) ................................................................................................. 40
`8.2.12 Word Read Quad I/O (E7h) ................................................................................................ 43
`8.2.13 Octal Word Read Quad I/O (E3h) ....................................................................................... 45
`8.2.14 Set Burst with Wrap (77h) ................................................................................................... 47
`8.2.15 Page Program (02h) ........................................................................................................... 48
`8.2.16 Quad Input Page Program (32h) ......................................................................................... 50
`8.2.17 Sector Erase (20h) .............................................................................................................. 51
`8.2.18 32KB Block Erase (52h)...................................................................................................... 52
`8.2.19 64KB Block Erase (D8h) ..................................................................................................... 53
`
`Publication Release Date: March 25, 2013
`- 2 - Preliminary - Revision D
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 3
`
`

`

`W25Q64FW
`
`
`8.2.20 Chip Erase (C7h / 60h) ....................................................................................................... 54
`8.2.21 Erase / Program Suspend (75h) ......................................................................................... 55
`8.2.22 Erase / Program Resume (7Ah) .......................................................................................... 57
`8.2.23 Power-down (B9h) .............................................................................................................. 58
`8.2.24 Release Power-down / Device ID (ABh) ............................................................................. 59
`8.2.25 Read Manufacturer / Device ID (90h) ................................................................................. 61
`8.2.26 Read Manufacturer / Device ID Dual I/O (92h) ................................................................... 62
`8.2.27 Read Manufacturer / Device ID Quad I/O (94h) .................................................................. 63
`8.2.28 Read Unique ID Number (4Bh) ........................................................................................... 64
`8.2.29 Read JEDEC ID (9Fh) ........................................................................................................ 65
`8.2.30 Erase Security Registers (44h) ........................................................................................... 66
`8.2.31 Program Security Registers (42h) ....................................................................................... 67
`8.2.32 Read Security Registers (48h) ............................................................................................ 68
`8.2.33 Set Read Parameters (C0h) ............................................................................................... 69
`8.2.34 Burst Read with Wrap (0Ch) ............................................................................................... 70
`8.2.35 Enter QPI Mode (38h) ......................................................................................................... 71
`8.2.36 Exit QPI Mode (FFh) ........................................................................................................... 72
`8.2.37
`Individual Block/Sector Lock (36h) ...................................................................................... 73
`8.2.38
`Individual Block/Sector Unlock (39h) .................................................................................. 74
`8.2.39 Read Block/Sector Lock (3Dh) ............................................................................................ 75
`8.2.40 Global Block/Sector Lock (7Eh) .......................................................................................... 76
`8.2.41 Global Block/Sector Unlock (98h) ....................................................................................... 76
`8.2.42 Enable Reset (66h) and Reset Device (99h) ...................................................................... 77
`
`9.
`
`ELECTRICAL CHARACTERISTICS .............................................................................................. 78
`
`Absolute Maximum Ratings ................................................................................................ 78
`9.1
`Operating Ranges .............................................................................................................. 78
`9.2
`Power-up Power-down Timing and Requirements ............................................................ 79
`9.3
`DC Electrical Characteristics .............................................................................................. 80
`9.4
`AC Measurement Conditions ............................................................................................. 81
`9.5
`AC Electrical Characteristics .............................................................................................. 82
`9.6
`AC Electrical Characteristics (cont’d) ................................................................................. 83
`9.7
`Serial Output Timing ........................................................................................................... 84
`9.8
`Serial Input Timing .............................................................................................................. 84
`9.9
`9.10 HOLD Timing ...................................................................................................................... 84
`9.11 WP Timing .......................................................................................................................... 84
`
`10.
`
`PACKAGE SPECIFICATIONS ....................................................................................................... 85
`
`10.1
`10.2
`10.3
`
`8-Pin SOIC 208-mil (Package Code SS) ........................................................................... 85
`8-Pin VSOP 208-mil (Package Code ST) .......................................................................... 86
`8-Pad WSON 6x5-mm (Package Code ZP) ....................................................................... 87
`
`
`- 3 -
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 4
`
`

`

`W25Q64FW
`
`10.4
`10.5
`10.6
`10.7
`10.8
`
`
`8-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 88
`16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 89
`24-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 ball array) ......................................... 90
`24-Ball TFBGA 8x6-mm (Package Code TC, 6x4 ball array) ............................................ 91
`16-Ball WLBGA (Package Code BY) ................................................................................. 92
`
`11.
`
`ORDERING INFORMATION .......................................................................................................... 93
`
`11.1 Valid Part Numbers and Top Side Marking ........................................................................ 94
`
`12.
`
`REVISION HISTORY ...................................................................................................................... 95
`
`
`
`Publication Release Date: March 25, 2013
`- 4 - Preliminary - Revision D
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 5
`
`

`

`W25Q64FW
`
`
`
`1. GENERAL DESCRIPTIONS
`The W25Q64FW (64M-bit) Serial Flash memory provides a storage solution for systems with limited
`space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
`Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI
`(XIP) and storing voice, text and data. The device operates on a single 1.65V to 1.95V power supply with
`current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-
`saving packages.
`The W25Q64FW array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes
`can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
`(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64FW
`has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater
`flexibility in applications that require data and parameter storage. (See Figure 2.)
`The W25Q64FW support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-
`clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI),
`I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
`equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O
`when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform
`standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for
`efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing
`true XIP (execute in place) operation.
`A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
`further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID, a
`64-bit Unique Serial Number and three 256-bytes Security Registers.
`
`2. FEATURES
`
` New Family of SpiFlash Memories
`– W25Q64FW: 64M-bit / 8M-byte
`– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
`– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
`– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
`– QPI: CLK, /CS, IO0, IO1, IO2, IO3
`– Software & Hardware Reset
`
` Highest Performance Serial Flash
`– 104MHz Single, Dual/Quad SPI clocks
`– 208/416MHz equivalent Dual/Quad SPI
`– 50MB/S continuous data transfer rate
`– More than 100,000 erase/program cycles
`– More than 20-year data retention
`
` Efficient “Continuous Read” and QPI Mode
`– Continuous Read with 8/16/32/64-Byte
`Wrap
`– As few as 8 clocks to address memory
`– Quad Peripheral Interface (QPI) reduces
`instruction overhead
`– Allows true XIP (execute in place) operation
`– Outperforms X16 Parallel Flash
`
` Low Power, Wide Temperature Range
`– Single 1.65 to 1.95V supply
`– 4mA active current, <1µA Power-down (typ.)
`– -40°C to +85°C operating range
`
` Flexible Architecture with 4KB sectors
`– Uniform Sector/Block Erase (4K/32K/64K-Byte)
`– Program 1 to 256 byte per programmable page
`– Erase/Program Suspend & Resume
`
` Advanced Security Features
`– Software and Hardware Write-Protect
`– Power Supply Lock-Down and OTP protection
`– Top/Bottom, Complement array protection
`– Individual Block/Sector array protection
`– 64-Bit Unique ID for each device
`– 4X256-Bytes Security Registers with OTP locks
`– Volatile & Non-volatile Status Register Bits
` Space Efficient Packaging
`– 8-pin SOIC/VSOP 208-mil
`– 8-pad WSON 6x5-mm / 8x6-mm
`– 16-pin SOIC 300-mil (additional /RESET pin)
`– 16-ball WLBGA
`– 24-ball TFBGA 8x6-mm
`– Contact Winbond for KGD and other options
`
`
`- 5 -
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 6
`
`

`

`3. PACKAGE TYPES AND PIN CONFIGURATIONS
`
`3.1 Pin Configuration SOIC / VSOP 208-mil
`
`W25Q64FW
`
`
`
`
`Figure 1a. W25Q64FW Pin Assignments, 8-pin SOIC / VSOP 208-mil (Package Code SS, ST)
`
`3.2 Pad Configuration WSON 6x5-mm / 8x6-mm
`
`
`Figure 1b. W25Q64FW Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code ZP, ZE)
`
`
`3.3 Pin Description SOIC/VSOP 208-mil, WSON 6x5-mm / 8x6-mm
`
`PIN NO.
`
`PIN NAME
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`Notes:
`
`/CS
`
`DO (IO1)
`
`/WP (IO2)
`
`GND
`
`DI (IO0)
`
`CLK
`
`/HOLD or /RESET
`(IO3)
`
`I/O
`
`I
`
`I/O
`
`I/O
`
`
`
`I/O
`
`I
`
`I/O
`
`FUNCTION
`
`Chip Select Input
`Data Output (Data Input Output 1)(1)
`Write Protect Input ( Data Input Output 2)(2)
`
`Ground
`Data Input (Data Input Output 0)(1)
`
`Serial Clock Input
`
`Hold or Reset Input (Data Input Output 3)(2)
`
`VCC
`
`
`
`Power Supply
`
` 1. IO0 and IO1 are used for Standard and Dual SPI instructions
` 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
`
`Publication Release Date: March 25, 2013
`- 6 - Preliminary - Revision D
`
`VCC
`
`/HOLD or /RESET
`(IO3)
`
`CLK
`
`DI (IO0)
`
`Top View
`
`8 7 6 5
`
`
`
`1 2 3 4
`
`/CS
`
`DO (IO1)
`
`/WP (IO2)
`
`GND
`
`VCC
`
`/HOLD or /RESET
`(IO3)
`
`CLK
`
`DI (IO0)
`
`Top View
`
`8 7 6 5
`
`
`
`1 2 3 4
`
`/CS
`
`DO (IO1)
`
`/WP (IO2)
`
`GND
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 7
`
`

`

`3.4 Pin Configuration SOIC 300-mil
`
`W25Q64FW
`
`
`
`
`Figure 1c. W25Q64FW Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
`
`3.5 Pin Description SOIC 300-mil
`
`PIN NO.
`
`PIN NAME
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`/HOLD (IO3)
`
`VCC
`
`/RESET
`
`N/C
`
`N/C
`
`N/C
`
`/CS
`
`DO (IO1)
`
`/WP (IO2)
`
`GND
`
`N/C
`
`N/C
`
`N/C
`
`N/C
`
`DI (IO0)
`
`CLK
`
`I/O
`
`I/O
`
`
`
`I
`
`
`
`
`
`
`
`I
`
`I/O
`
`I/O
`
`
`
`
`
`
`
`
`
`
`
`I/O
`
`I
`
`Hold Input (Data Input Output 3)(2)
`
`FUNCTION
`
`Power Supply
`Reset Input(3)
`No Connect
`
`No Connect
`
`No Connect
`
`Chip Select Input
`Data Output (Data Input Output 1)(1)
`Write Protect Input (Data Input Output 2)(2)
`
`Ground
`
`No Connect
`
`No Connect
`
`No Connect
`
`No Connect
`Data Input (Data Input Output 0)(1)
`
`Serial Clock Input
`
`Notes:
`
` 1. IO0 and IO1 are used for Standard and Dual SPI instructions
` 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
`3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin
`can be left floating, if Rest function is not needed.
`
`
`
`
`- 7 -
`
`CLK
`
`DI (IO0)
`
`NC
`
`NC
`
`NC
`
`NC
`
`GND
`
`/WP (IO2)
`
`Top View
`
`16
`
`15
`
`14
`
`13
`
`12
`
`11
`
`10
`
`9
`
`
`
`1 2 3 4
`
`5 6 7 8
`
`/HOLD (IO3)
`
`VCC
`
`/RESET
`
`NC
`
`NC
`
`NC
`
`/CS
`
`DO (IO1)
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 8
`
`

`

`3.6 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
`
`W25Q64FW
`
`
`
`
`Figure 1d. W25Q64FW Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB, TC)
`
`3.7 Ball Description TFBGA 8x6-mm
`
`BALL NO.
`
`PIN NAME
`
`I/O
`
`FUNCTION
`
`B2
`
`B3
`
`B4
`
`C2
`
`C4
`
`D2
`
`D3
`
`D4
`
`CLK
`
`GND
`
`VCC
`
`/CS
`
`/WP (IO2)
`
`DO (IO1)
`
`DI (IO0)
`
`/HOLD or /RESET
`(IO3)
`
`I
`
`
`
`
`
`I
`
`I/O
`
`I/O
`
`I/O
`
`I/O
`
`Serial Clock Input
`
`Ground
`
`Power Supply
`
`Chip Select Input
`Write Protect Input (Data Input Output 2)(2)
`Data Output (Data Input Output 1)(1)
`Data Input (Data Input Output 0)(1)
`
`Hold or Reset Input (Data Input Output 3)(2)
`
`Multiple
`
`NC
`
`
`
`No Connect
`
`Notes:
`
` 1. IO0 and IO1 are used for Standard and Dual SPI instructions
` 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
`
`Publication Release Date: March 25, 2013
`- 8 - Preliminary - Revision D
`
`Top View
`
`Top View
`
`A2
`
`NC
`
`B2
`
`A3
`
`NC
`
`B3
`
`A4
`
`NC
`
`B4
`
`CLK
`
`GND
`
`VCC
`
`C2
`
`/CS
`
`D2
`
`C3
`
`NC
`
`D3
`
`DO(IO1)
`
`DI(IO0)
`
`C4
`
`/WP (IO2)
`
`D4
`
`/HOLD(IO3)
`/RESET
`
`E2
`
`NC
`
`E3
`
`NC
`
`E4
`
`NC
`
`A5
`
`NC
`
`B5
`
`NC
`
`C5
`
`NC
`
`D5
`
`NC
`
`E5
`
`NC
`
`B1
`
`NC
`
`C1
`
`NC
`
`D1
`
`NC
`
`E1
`
`NC
`
`A1
`
`NC
`
`B1
`
`NC
`
`C1
`
`NC
`
`D1
`
`NC
`
`E1
`
`NC
`
`F1
`
`NC
`
`A2
`
`NC
`
`B2
`
`A3
`
`NC
`
`B3
`
`A4
`
`NC
`
`B4
`
`CLK
`
`GND
`
`VCC
`
`C2
`
`/CS
`
`D2
`
`C3
`
`NC
`
`D3
`
`DO(IO1)
`
`DI(IO0)
`
`C4
`
`/WP (IO2)
`
`D4
`/HOLD(IO3)
`/RESET
`
`E2
`
`NC
`
`F2
`
`NC
`
`E3
`
`NC
`
`F3
`
`NC
`
`E4
`
`NC
`
`F4
`
`NC
`
`Package Code TB
`
`Package Code TC
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 9
`
`

`

`3.8 Ball Configuration WLBGA
`
`W25Q64FW
`
`
`
`
`
`Figure 1e. W25Q64FW Ball Assignments, 16-ball WLBGA (Package Code BY)
`
`3.9 Ball Description WLBGA
`
`BALL NO.
`
`PIN NAME
`
`A2
`
`B2
`
`C2
`
`D2
`
`A3
`
`B3
`
`C3
`
`D3
`
`Multiple
`
`Notes:
`
`VCC
`
`/HOLD or /RESET
`(IO3)
`
`CLK
`
`DI (IO0)
`
`/CS
`
`DO (IO1)
`
`/WP (IO2)
`
`GND
`
`NC
`
`I/O
`
`
`
`I/O
`
`I
`
`I/O
`
`I
`
`I/O
`
`I/O
`
`
`
`
`
`Power Supply
`
`FUNCTION
`
`Hold or Reset Input (Data Input Output 3)(2)
`
`Serial Clock Input
`Data Input (Data Input Output 0)(1)
`
`Chip Select Input
`Data Output (Data Input Output 1)(1)
`Write Protect Input (Data Input Output 2)(2)
`
`Ground
`
`No Connect
`
` 1. IO0 and IO1 are used for Standard and Dual SPI instructions
` 2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
`
`
`- 9 -
`
`Top View
`
`A2
`
`VCC
`
`B2
`
`A3
`
`/CS
`
`B3
`
`/HOLD(IO3)
`
`DO(IO1)
`
`C2
`
`C3
`
`CLK
`
`/WP(IO2)
`
`D2
`
`D3
`
`DI(IO0)
`
`GND
`
`A1
`
`NC
`
`B1
`
`NC
`
`C1
`
`NC
`
`D1
`
`NC
`
`A4
`
`NC
`
`B4
`
`NC
`
`C4
`
`NC
`
`D4
`
`NC
`
`Bottom View
`
`A3
`
`/CS
`
`B3
`
`A2
`
`VCC
`
`B2
`
`DO(IO1)
`
`/HOLD(IO3)
`
`C3
`
`C2
`
`/WP(IO2)
`
`CLK
`
`D3
`
`D2
`
`GND
`
`DI(IO0)
`
`A4
`
`NC
`
`B4
`
`NC
`
`C4
`
`NC
`
`D4
`
`NC
`
`A1
`
`NC
`
`B1
`
`NC
`
`C1
`
`NC
`
`D1
`
`NC
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 10
`
`

`

`W25Q64FW
`
`
`
`4. PIN DESCRIPTIONS
`
`4.1 Chip Select (/CS)
`
`The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
`deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
`deselected, the devices power consumption will be at standby levels unless an internal erase, program or
`write status register cycle is in progress. When /CS is brought low the device will be selected, power
`consumption will increase to active levels and instructions can be written to and data read from the device.
`After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
`input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
`57). If needed a pull-up resister on the /CS pin can be used to accomplish this.
`
`4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
`
`The W25Q64FW supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions
`use the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
`rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to
`read data or status from the device on the falling edge of CLK.
`Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or
`data to the device on the rising edge of CLK and read data or status from the device on the falling edge of
`CLK. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
`When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
`
`4.3 Write Protect (/WP)
`
`The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
`conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
`Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
`hardware protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O,
`the /WP pin function is not available since this pin is used for IO2. See Figure 1a-c for the pin
`configuration of Quad I/O operation.
`
`4.4 HOLD (/HOLD)
`
`The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
`while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
`(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
`useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
`QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
`used for IO3. See Figure 1a-c for the pin configuration of Quad I/O operation.
`
`4.5 Serial Clock (CLK)
`
`The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
`Operations")
`
`4.6 Reset (/RESET)
`
`The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
`pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
`When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC
`package, a dedicated /RESET pin is provided and it is independent of QE bit setting.
`
`Publication Release Date: March 25, 2013
`- 10 - Preliminary - Revision D
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 11
`
`

`

`5. BLOCK DIAGRAM
`
`W25Q64FW
`
`
`
`Figure 2. W25Q64FW Serial Flash Memory Block Diagram
`
`
`- 11 -
`
`Security Register 3 - 0
`
`003000h 0030FFh
`002000h 0020FFh
`001000h 0010FFh
`000000h 0000FFh
`
`7FFF00h 7FFFFFh
`• Block 127 (64KB) •
`7F0000h 7F00FFh
`
`• • •
`
`W25Q64FW
`
`40FF00h 40FFFFh
`• Block 64 (64KB) •
`400000h 4000FFh
`
`3FFF00h 3FFFFFh
`• Block 63 (64KB) •
`3F0000h 3F00FFh
`
`• • •
`
`20FF00h 20FFFFh
`• Block 32 (64KB) •
`200000h 2000FFh
`
`1FFF00h 1FFFFFh
`• Block 31 (64KB) •
`1F0000h 1F00FFh
`
`• • •
`
`00FF00h 00FFFFh
`• Block 0 (64KB) •
`000000h 0000FFh
`
`Beginning
`Page Address
`
`Ending
`Page Address
`
`Column Decode
`And 256-Byte Page Buffer
`
`Write Protect Logic and Row Decode
`
`Block Segmentation
`
`xxFF00h xxFFFFh
`• Sector 15 (4KB) •
`xxF000h xxF0FFh
`
`xxEF00h xxEFFFh
`• Sector 14 (4KB) •
`xxE000h xxE0FFh
`
`xxDF00h xxDFFFh
`• Sector 13 (4KB) •
`xxD000h xxD0FFh
`
`• • •
`
`xx2F00h xx2FFFh
`• Sector 2 (4KB) •
`xx2000h xx20FFh
`
`xx1F00h xx1FFFh
`• Sector 1 (4KB) •
`xx1000h xx10FFh
`
`xx0F00h xx0FFFh
`• Sector 0 (4KB) •
`xx0000h xx00FFh
`
`/WP (IO2)
`
`Write Control
`Logic
`
`Status
`Register
`
`SPI
`Command &
`Control Logic
`
`High Voltage
`Generators
`
`Page Address
`Latch / Counter
`
`Data
`
`Byte Address
`Latch / Counter
`
`/HOLD (IO3)
`or /RESET (IO3)
`
`CLK
`
`/CS
`
`DI (IO0)
`
`DO (IO1)
`
`Patent Owner, Bot M8 LLC - Ex. 2037, p. 12
`
`

`

`6. FUNCTIONAL DESCRIPTIONS
`
`6.1 SPI / QPI Operations
`
`W25Q64FW
`
`
`
`Figure 3. W25Q64FW Serial Flash Memory Operation Diagram
`
`
`
`
`6.1.1 Standard SPI Instructions
`The W25Q64FW is accessed through an SPI compatible bus consisting of four signals: Serial Clock
`(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
`use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
`CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
`
`SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
`Mode 3 concerns the normal state