`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`_____________________________________
`
`Case No. IPR2020-01336
`Patent No. 7,012,463
`____________________________________
`PATENT OWNER’S RESPONSE
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`IPR2020-01336
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`TABLE OF CONTENTS
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`I.
`II.
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`Page
`INTRODUCTION ........................................................................................... 3
`THE ’463 PATENT ......................................................................................... 5
`A.
`Common-Mode-Feedback Circuits ....................................................... 5
`B.
`The Claimed Invention .......................................................................... 8
`C.
`The Challenged Claims ....................................................................... 23
`III. THE CITED PRIOR ART ............................................................................. 25
`A. Oliaei ................................................................................................... 25
`B.
`Vittoz ................................................................................................... 31
`IV. PETITIONER HAS NOT ESTABLISHED THAT OLIAEI RENDERS THE
`CHALLENGED CLAIMS OBVIOUS (GROUND 1) ................................. 33
`A. Oliaei Figure 6 Does Not Teach Or Suggest An “Impedance Matching
`Circuit” That Is “Connected to Said Feedback Circuit To Adjust The
`Feedback Signal” Generated In The “Second Operational Mode Of
`That Feedback Circuit,” As Recited In Claim 11 ............................... 36
`Even If Oliaei’s Precharging Capacitors Or SC-CMFB Could Be
`Understood As An Impedance Matching Circuit As Claimed—Which
`They Are Not—The Alleged Impedance Matching Circuit Is Not
`“Coupled To” A Terminal Of The Precharging Capacitor, As Further
`Recited In Claim 11 ............................................................................. 44
`C. Dr. Holberg’s Math Merely Shows That Symmetric CMFB Circuits
`Have Symmetric Properties, Not That One of the CMFB Circuits Is
`Impedance Matching a Particular Node of the Other or Adjusting the
`Feedback Signal Generated by the Other ............................................ 49
`D. Oliaei Does Not Render Claim 1 Obvious .......................................... 50
`E.
`Oliaei Does Not Render The Dependent Claims Obvious .................. 51
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`B.
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`PETITIONER HAS NOT ESTABLISHED THAT OLIAEI IN VIEW OF
`VITTOZ RENDERS THE CHALLENGED CLAIMS OBVIOUS
`(GROUND 2) ................................................................................................. 51
`A.
`The Petition Fails to Establish a Proper Motivation to Combine Oliaei
`and Vittoz ............................................................................................ 53
`The Combination of Oliaei With Vittoz Does Not Render the
`Dependent Claims Obvious ................................................................. 77
`VI. CONCLUSION .............................................................................................. 79
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`V.
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`B.
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`IPR2020-01336
`Patent Owner’s Response
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`Patent Owner Analog Devices, Inc. (“Analog”) submits the following Patent
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`Owner Response (“POR”) to the petition filed by Xilinx, Inc. and Xilinx Asia
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`Pacific Pte. Ltd. (“Petitioner”) requesting inter partes review of claims 1-7, 10-17,
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`and 29 of U.S. Patent No. 7,012,463 (“the ʼ463 patent”).
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`I.
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`INTRODUCTION
`The ’463 patent concerns an improved common-mode feedback circuit that
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`sets a differential amplifier’s common mode to a desired level faster and more
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`accurately than prior solutions. In this way, the improved common-mode feedback
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`circuit more optimally biases the differential amplifier for better performance,
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`yielding a better signal to noise ratio, resolution, and the like.
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`The inventor, Professor David Nairn, discovered that then-conventional
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`common mode feedback circuits significantly varied their common mode level
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`during operation. He found that one cause of this variation was that the system’s
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`common mode error gain significantly depended on parasitic capacitances in the
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`circuit as well as the (relatively small) value of a precharging capacitor (a.k.a. fly
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`capacitor Cfly) within the common mode feedback circuit. To address these issues,
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`Professor Nairn modified the common mode feedback circuit to include an
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`impedance matching circuit that is coupled to that precharging capacitor within
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`the common mode feedback circuit and that adjusts the feedback signal generated
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`by that common mode feedback circuit. This technique reduces the variations and
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`dependencies in the error gain, yielding a more accurate and stable actual common
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`mode. In addition, the impedance matching circuit enables the use of more optimal
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`capacitance values for the precharging and feedback capacitors within the common
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`mode feedback circuit, thereby improving the speed of the circuit in addition to its
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`accuracy.
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`In contrast, Petitioner’s primary reference, Oliaei, proposed the use of a
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`conventional switched capacitor common-mode feedback approach, in the new
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`context of a continuous-time sigma delta modulator. Oliaei devotes just a single
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`short paragraph to each of its two embodiments of a common mode feedback
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`circuit, and provides no hint or suggestion that the feedback circuits are anything
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`other than conventional. In fact, Oliaei’s Figure 5 embodiment mirrors the
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`switched capacitor common mode feedback circuit described in the Johns and
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`Martin textbook cited in the ’463 patent’s Background section. Petitioner does not
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`even attempt to argue that Olaiei’s Figure 5 circuit has an “error correcting circuit”
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`or “impedance matching circuit,” within it or for it, nor could it. And Oliaei itself
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`refers to its Figure 6 “symmetric” embodiment as simply having “2 sets” of the
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`conventional common mode feedback circuit “shown in figure 5.” (Ex. 1007, 6:8-
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`10.)
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`The Petition attempts to remedy these deficiencies by arguing, in the
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`alternative, that a POSITA would be motivated to modify Oliaei in light of Vittoz
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`to reduce the effects of charge injection in Oliaei. However, just as Oliaei neither
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`recites nor teaches the required error correcting or impedance matching circuit,
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`there is no motivation to modify Oliaei to include one. Indeed, as explained below,
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`Oliaei itself explains that its circuit does not suffer from charge injection (i.e.,
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`clock feedthrough), directly conflicting with the Petition’s theory of obviousness.
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`Given these substantial differences, the grounds in the Petition fail to
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`establish that any of the challenged claims are unpatentable.
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`II. THE ’463 PATENT
`The ’463 patent concerns a novel, improved common-mode feedback circuit
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`that quickly and accurately provides a feedback signal to a differential amplifier to
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`reduce variations between the actual and the desired common mode level. (Ex.
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`2002, ¶10.)
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`A. Common-Mode-Feedback Circuits
`An analog circuit can represent a value as a simple signal, such as 4 volts on
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`a circuit output. But many analog circuits, such as differential amplifiers, utilize
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`pairs of signals that are the inverse of each other, known as “differential” signals,
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`to represent values. For example, instead of representing a value by placing volts
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`on a single signal, a differential amplifier could represent the same value using two
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`signals having a difference of 4 volts (such as, e.g., +2 volts and -2 volts, or +7
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`volts and +3 volts). Differential signals can be useful in compensating for certain
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`types of noise that affect each signal within the pair roughly equally. As a result,
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`the difference between two differential signals may remain constant even as their
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`absolute values fluctuate. (Ex. 2002, ¶11.)
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`The “common mode” is the average voltage level of these differential
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`signals. (Ex. 1001, 1:11-19.) In the example where the differential signal is +2
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`and -2 volts, the common mode is 0; or for +7 and +3 volts, it is 5 volts. (Ex.
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`2002, ¶12.)
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`In many applications, it is desirable to maintain the common mode at a pre-
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`determined, desired level. (Ex. 1001, 1:36-67.) In this way, the differential
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`amplifier might enjoy larger signal swings and better signal to noise ratio, and the
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`like. As the Background section of the ’463 patent recognizes, a so-called
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`“common-mode feedback circuit” was used to provide feedback signals to the
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`differential amplifier to try to adjust the common mode to the desired level. (Id.,
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`1:22-40; Ex. 2002, ¶12.)
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`The ’463 patent summarizes the state of art in common-mode-feedback
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`circuits, referring to D. A. Johns and K. Martin, Analog Integrated Circuit Design
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`(1997) (Ex. 1005), among other background references. (Ex. 1001, 1:25-30.)
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`Figure 6.22 of Johns is reproduced below with annotations. (Ex. 2002, ¶13.)
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`(Ex. 1005, Figure 6.22.)1
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`This basic common-mode feedback circuit receives as inputs a pair of
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`differential output voltages (Vout+ and Vout-) from an analog circuit such as a
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`differential amplifier. (Ex. 1005, 8, 12.) The differential output voltages have a
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`measured (or actual) common mode level corresponding to the average of Vout+ and
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`Vout-. (Id.) The circuit is also connected to voltage sources representing the
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`desired common-mode level, in this case ground. (Id.) During operation, the
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`common-mode feedback circuit generates a feedback signal at node Vcntrl based on
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`the difference between the actual common-mode level and the desired common-
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`mode level. (Id.) The feedback signal is provided to the analog circuit to cause it
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`to change the voltages Vout+ and Vout- accordingly. (Id.; Ex. 2002, ¶14)
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`1 All annotation added unless otherwise noted.
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`The feedback signal at node Vcntrl is generated using the switched-capacitor
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`circuitry of the common-mode feedback circuit. (Ex. 1005, 12.) A set of
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`“feedback” capacitors (CC) generate the average of the actual output voltages
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`(Vout+ and Vout-), which corresponds to the actual common mode of the differential
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`circuit at a given point in time. (Id.) A set of “fly” capacitors (CS, gray) are
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`switched in one clock phase (Φ1) to receive the desired common mode, in this
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`case ground. This operation “precharges” those capacitors with the desired
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`common mode value. In a second clock phase (Φ2), the fly capacitors (CS, gray)
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`are coupled to the feedback capacitors (CC) to determine a difference between the
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`actual and desired values to generate the feedback signal at node Vcntrl. (Id.) In
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`conventional implementations, the fly capacitors (CS) “might be between one-
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`quarter and one-tenth the sizes of the [feedback] capacitors [(CC)].” (Id.; Ex.
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`2002, ¶15.)
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`B.
`The Claimed Invention
`Professor Nairn discovered that the performance of conventional common-
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`mode feedback circuits was limited by the variations in the common-mode level
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`that occur when switching between the two clock phases Φ1 and Φ2. (Ex. 1001,
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`1:58-67; 6:27-51.) As the patent explains, the common mode level “can vary due
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`to changes in the common-mode feedback circuit.” (Id., 1:58-59.) Even small
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`errors within the common-mode feedback circuit are “multiplied by the common-
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`mode error gain to provide a common-mode error that varies from one clock phase
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`to the next.” (Id., 1:61-63.) Accordingly, these variations “reduce the available
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`signal range for differential amplifiers.” (Id., 1:63-64.) This is particularly
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`problematic in low-voltage applications where the available signal range is
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`compressed to begin with, such as mobile electronics. (Id., 1:65-67; Ex. 2002,
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`¶16.)
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`Professor Nairn recognized that these variations resulted from the operation
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`of the conventional common-mode feedback circuit, such as Johns, again
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`reproduced below.2
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`2 Figure 6.22 of Johns is used here for clarity, as it concisely shows prior
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`circuitry. The ’463 patent analyzes common-mode variations with reference to
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`corresponding components shown in Figure 2 of the patent, but that figure is more
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`complex and also shows the invention. (See, e.g., Ex. 1001, 6:27-51.)
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`(Ex. 1005, Figure 6.22.) The operation and function of the circuit could be
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`understood by analyzing the dynamic transfer of charge among the various
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`capacitors (i.e., the horizontal flow of charge in the figure above). This would
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`explain how the circuit generates a feedback signal at node Vcntrl. Professor Nairn,
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`however, looked at other aspects of the circuit, including that the total capacitance
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`between the nodes Vout+ and Vout- and the node Vcntrl (i.e., the capacitance seen
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`along vertical path in the figure above) also impacts the performance of the
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`common mode feedback circuit. During the first clock phase Φ1, only the circuitry
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`in blue (including the feedback capacitors CC) is coupled between the nodes
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`Vout+ and Vout- and the node Vcntrl. Thus, the capacitance between those nodes is
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`that of the feedback capacitors CC. The remaining circuitry is excluded because
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`the Φ2 switches are in the off, or open, state, decoupling the other capacitors Cs.
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`(Ex. 2002, ¶¶17-19.)
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`During the second clock phase Φ2, when the Φ2 switches are in the on, or
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`closed, state, fly capacitors CS are now coupled in parallel to the feedback
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`capacitors CC via the additional circuitry in pink. Accordingly, the capacitance of
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`the fly capacitors CS now adds to the total capacitance between the nodes Vout+
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`and Vout- and the node Vcntrl. That is, the fly capacitors CS—and other parasitic
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`capacitances within the pink portion (not shown)—are alternately added and
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`removed from the total capacitance between Vout+ and Vout- and Vcntrl from phase
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`to phase. (Ex. 2002, ¶20.)
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`Figure 2 of the ’463 patent, reproduced below with matching color
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`annotations, depicts corresponding circuit elements that operate in the same
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`manner. (Ex. 2002, ¶21.)
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`(Ex. 1001, Fig. 2.)
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`Professor Nairn determined, through simulations, how the common-mode
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`voltage output would vary between clock phases and would further deviate from
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`the desired common-mode level in a conventional common-mode feedback circuit.
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`These errors are depicted in curve 42 of Figure 4 of the ’463 patent, reproduced
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`below. (Id., 10:10-18, Table 1.)
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`(Ex. 1001, Figure 4.) As this figure demonstrates, the common mode voltage
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`output in curve 42 fluctuates between a high voltage level during clock phase Φ1
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`(dashed red) and a lower voltage during clock phase Φ2 (solid red). As can be seen,
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`the variation in the common mode voltage between the two clock phases (shown by
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`the red arrows on the right) may be significant, and in both clock phases, the common
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`mode level is shifted higher than the desired level of 0.85 volts. (See, e.g., id.,
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`10:19-30, Table 1.) Professor Nairn observed that these variations and offsets
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`“reduce the available signal range for differential amplifiers,” which is particularly
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`concerning in applications that use low supply voltages, such as “low power and
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`portable electronic applications.” (Id., 1:58-68; Ex. 2002, ¶22.)
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`The ’463 patent improves on the earlier common mode feedback circuits
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`(“CMFBs”) by placing an impedance matching circuit, including an additional
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`capacitor, at a specific terminal within the CMFB circuit. (Ex. 1001, 7:32-43.)
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`The ’463 patent thus adjusts the feedback signal produced by a given CMFB
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`circuit by coupling the impedance matching circuit to a terminal within that CMFB
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`circuit. As shown in the embodiment depicted in Figure 2 below, the impedance
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`matching circuit includes a capacitor C1 that is coupled to a terminal Vb of the
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`precharging (a.k.a. fly) capacitors.
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`(Ex. 1001, Figure 2.) The capacitance of capacitor C1 is selected to match the
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`impedance at the feedback terminal (VFB), which is coupled to current sinking
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`portion 11. (Id., 7:52-54.) By coupling this impedance matching capacitor C1
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`to terminal Vb, the capacitor C1 adjusts the feedback signal at terminal VFB
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`generated by the CMFB circuit during the clock phase Φ2. (Ex. 2002, ¶23.)
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`The invention, shown below, thus improves on the earlier common-mode
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`feedback circuit.
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`(Ex. 1001, Figure 2.) During the first clock phase Φ1, only the circuitry along the
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`blue paths is connected between the differential output voltages and the
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`feedback terminal, and during the clock phase Φ2, the additional circuitry along
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`the pink paths (including the capacitor C1) is also connected. The same CMFB
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`circuit generates the feedback signal at VFB during both clock phases, but in the
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`’463 invention, that feedback signal is adjusted in the second clock phase by the
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`impedance matching circuit coupled to a terminal of the precharging (fly)
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`capacitor. (Ex. 2002, ¶24.)
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`Professor Nairn discovered that adjusting the feedback signal with an
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`impedance matching circuit addresses a number of limitations of conventional
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`CMFB circuits. (Ex. 1001, 7:32-9:59.) Among other things, the impedance
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`matching circuit enables the error gain of the CMFB to be constant throughout
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`both phases of the clocking cycle (and indeed at all times), which reduces
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`common-mode variation and enables further performance benefits explained
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`below. (Ex. 1001, 7:61-8:8.) This is expressed mathematically in equation 1. (Id.)
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`(Id.) The left side of equation 1 corresponds to the error gain during clock phase
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`Φ1, and the right side corresponds to the error gain during phase Φ2. (Id.) The
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`equation above shows that including C1 in the circuit allows the error gain in phase
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`Φ1 to be matched to the error gain in phase Φ2 within the same circuit. If C1 were
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`0 (meaning no impedance matching circuit connected), the error gains in phases Φ1
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`and Φ2 could never match, because the numerators would be the same whereas the
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`denominators would be different. (Ex. 2002, ¶25.)
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`Professor Nairn confirmed through simulations that this impedance
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`matching circuit improves the performance of the CMFB circuit. In particular, he
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`confirmed the impedance matching circuit reduces both (a) the variation in the
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`common-mode voltage output between the two clock phases and (b) the deviation
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`of the common-mode voltage output from the desired common-mode level during
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`each clock phase. (Ex. 1001, 10:10-43, Table 1.) These improvements are shown
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`in Figure 4 below.
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`(Ex. 1001, Figure 4.) As discussed above, curve 42 shows the steady state
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`common-mode voltage output from a CMFB circuit without any impedance
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`matching circuitry. Curve 46, indicated by additional highlighting, shows the
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`steady state common-mode voltage output of the same CMFB circuit when it
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`includes the impedance matching capacitor C1. (Ex. 1001, 10:10-43, Table 1.) As
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`the figure thus confirms, the common-mode voltage output in curve 46 varies
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`significantly less than the voltage in curve 42 between the two clock phases, and in
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`both clock phase, the common mode level is closer to the desired level of 0.85
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`volts than curve 42. (Id.; Ex. 2002, ¶26.)
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`Professor Nairn further realized that his impedance matching circuit, by
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`allowing the error gain to stay constant between clock phases regardless of the size
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`of the fly capacitors, allowed him to increase the size of the fly capacitors without
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`a corresponding increase in the phase-to-phase variations in the common-mode
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`level. In particular, Equation 1 of the patent shows that, regardless of the size of
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`the fly capacitors, a value of capacitor C1 can be chosen that ensures the same error
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`gain in both clock phases. (Ex. 1001, 8:9-18, 13:64-67.) Thus, whereas prior art
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`fly capacitors (in circuits without capacitor C1) were typically about 10x smaller
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`than the feedback capacitors to reduce the phase-to-phase error gain variations, the
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`use of capacitor C1 allows larger fly capacitors, which enhances the circuit’s ability
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`to quickly generate an accurate feedback signal. (Id., 8:19-45; see also Ex. 1005,
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`12.) For example, the ’463 patent describes using fly capacitors having
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`capacitance equal to that of the feedback capacitors (i.e., ten times larger relative to
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`the feedback capacitor than prior art fly capacitors). (Id., 8:9-18, 13:64-67.) This
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`results in a faster convergence rate of the CMFB circuit relative to a conventional
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`CMFB circuit, as verified by simulation in Figure 3. (Id., 8:19-65, Figure 3; Ex.
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`2002, ¶27.)
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`(Ex. 1001, Figure 3.) In the figure above, the desired steady state common-mode
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`level of the common-mode feedback circuit is again 0.85 V. (Id., 8:33-45.) Curve
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`52 shows the convergence rate for a conventional common-mode feedback circuit,
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`in which the feedback capacitors are ten times larger than the fly capacitors (as
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`suggested by the Johns textbook). (Id.; see also Ex. 1005, 12.) As reflected in
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`Figure 3, the small size of the fly capacitors limits the amount of charge that can be
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`transferred during each clock cycle, and consequently curve 52 shows that many
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`clock cycles are required before the average common mode voltage approaches the
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`steady-state level. (Id., 8:25-29.) In contrast, curve 54, which reflects the
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`convergence rate of the inventive circuit having larger fly capacitors, shows the
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`faster convergence rate of a CMFB circuit with the ’463 patent’s impedance
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`matching circuit. (Id., 8:46-52; 13:64-67; Ex. 2002, ¶28.)
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`Professor Nairn’s inventive circuit included a number of additional features.
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`In particular, he proposed adding another capacitor C2 and a dummy switch M11
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`(i.e., a switch whose input and output terminals are short-circuited such that the
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`switch does not block the flow of current even when turned off) to terminals
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`adjacent to the impedance matching capacitor C1 to compensate for charge
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`injection errors that might otherwise cause phase-to-phase variation in the
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`feedback signal.3 (See, e.g., id., 3:55-57, 6:59-7:31.)
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`3 “Charge injection errors” are caused by currents flowing through the parasitic
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`capacitances of transistors and by the transfer of charge from the channel of a
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`transistor to other parts of a circuit when the transistor turns on or off. (Ex. 1001,
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`6:59-63; Ex. 2002, ¶29.)
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`(Ex. 1001, Figure 2.) The sizes of capacitor C2 and dummy transistor M11 are
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`selected—in conjunction with impedance matching capacitor C1—to
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`compensate for the injected charge (qgd7, qgs7, qgd10, and qgs10) associated with
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`transistors M7 and M10. (Id., 8:66-9:59; Ex. 2002, ¶29.)
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`The additional improvements from C2 and M11 are shown in Figure 7
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`below.
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`(Ex. 1001, Figure 7.) As in Figure 4, curve 42 again shows the steady state
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`common-mode voltage output from a CMFB circuit without any impedance
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`matching circuitry or charge injection circuitry. Curve 74 shows the steady state
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`common-mode voltage output of a CMFB circuit with impedance matching
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`capacitor C1 along with capacitor C2 and dummy switch M11. (Ex. 1001, 13:10-
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`43, Table 4.) As shown by the arrows to the right of the graph, the common-mode
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`voltage output in curve 74 varies significantly less than curve 42 between the two
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`clock phases, and in both clock phases the common mode level of curve 74 is
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`closer to the desired level of 0.85 volts than curve 42. (Id.) Figure 7
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`demonstrates that capacitor C2 and dummy switch M11 provide additional
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`improvement in accuracy. (Ex. 2002, ¶30.)
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`C. The Challenged Claims
`Independent claim 11 recites:
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`11. An integrated circuit, comprising:
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`a differential amplifier circuit with an output
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`portion and a current sinking portion, said output portion
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`including dual outputs which provide an average output
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`level;
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`a common-mode feedback circuit coupled to said
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`output portion, said feedback circuit providing a desired
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`common-mode level in a first operational mode and
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`generating a feedback signal proportional to the
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`difference between the average output level and the
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`desired common-mode level in a second operational
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`mode, the feedback signal being coupled to said current
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`sinking portion; and
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`an impedance matching circuit connected to said
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`feedback circuit to adjust the feedback signal;
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`wherein the desired common-mode signal is
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`provided to a precharging capacitor in the first
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`operational mode, said precharging capacitor including
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`a terminal coupled to said impedance matching circuit.
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`Independent claims 1 and 11, in relevant part, address similar but not
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`identical subject matter, though using different terminology. Claim 11, for
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`example, recites a circuit with several conventional components, including a
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`differential amplifier and a CMFB circuit, for example as discussed in the
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`Background section. The claim also, unlike any prior art, requires an “impedance
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`matching circuit” (e.g., C1), where a “precharging [a.k.a. fly] capacitor” of the
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`CMFB circuit includes a “terminal coupled to [the] impedance matching circuit.”
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`The impedance matching circuit “is connected to [the CMFB] circuit to adjust the
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`feedback signal” generated by the CMFB circuit. (Ex. 1001, Cl. 11; Ex. 2002,
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`¶¶31-32.)
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`In comparison to claim 11, claim 1 recites a “common-mode circuit,” rather
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`than claim 11’s “differential amplifier.” Claim 1 also refers to a “common mode-
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`corrector circuit” (rather than claim 11’s “common mode feedback circuit”), and an
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`“error correcting circuit” that adjusts the “signal offset level” from the common
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`mode corrector circuit (rather than claim 11’s impedance matching circuit
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`adjusting the feedback signal generated by the common mode feedback circuit).
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`Claim 1 further requires the error correcting circuit to be “connected to [the]
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`common mode corrector circuit to adjust the signal offset level,” whereas claim 11
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`requires the specific connection to the precharging capacitor. (Ex. 1001, Cl. 1, Ex.
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`2002, ¶33.)
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`The dependent claims require the specific circuit arrangements found most
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`effective at addressing the above-identified problems. Dependent claim 12, for
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`example, further covers the embodiment of the ’463 patent where the impedance
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`matching circuit of claim 11 is adapted to also reduce charge injection (e.g., by
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`adding balancing capacitor C2 and dummy switch M11). (Ex. 2002, ¶34.)
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`III. THE CITED PRIOR ART
`A. Oliaei
`As its title suggests, Oliaei discloses techniques for using then-conventional
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`discrete-time (i.e., switched capacitor) CMFB circuitry in a new continuous-time
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`context, namely, continuous-time sigma-delta modulators. (Ex. 1007, Title,
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`Abstract, 5:34-42; Ex. 2002, ¶35.)
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`Oliaei explains that a discrete-time CMFB is one of the “typical approaches
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`to designing CMFB circuits.” (Ex. 1007, 3:51-53.) Whereas “[t]raditionally…the
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`discrete-time [CMFB] is employed only in discrete-time circuits,” Oliaei’s goal is
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`to “exploit[] the use of a discrete-time CMFB circuit in a continuous-time sigma-
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`delta modulator.” (Id., 3:55-60.) In short, Oliaei proposes a new use for an old
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`circuit. (Ex. 2002, ¶36.)
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`Because Oliaei was using conventional CMFB circuits in known
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`arrangements, its description of the CMFB circuits shown in Figures 5 and 6 is
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`sparse, comprising less than 35 lines of text. (See, e.g., Ex. 1007, 5:43-5:65, 6:4-
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`6:19; Ex. 2002, ¶37.)
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`Oliaei’s Figure 5 is reproduced below side-by-side with Figure 6.22 of
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`Johns. As this comparison confirms, the two circuits include the same basic
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`components.
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`Ex. 1007, Figure 5
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`Ex. 1005, Figure 6.22
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`Oliaei describes this embodiment in one paragraph, which never even discusses
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`certain components shown in the figure, such as capacitors 509-513, which are
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`essential to its operation. (See, e.g., Ex. 1007, 5:43-5:65). Oliaei provides no hint
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`or suggestion that Figure 5 depicts anything other than a conventional SC-CMFB
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`circuit, and if it were anything other than a conventional SC-CMFB circuit, a
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`POSITA would have expected such differences to be described. Indeed, it is
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`indistinguishable from the Johns circuit described in the ’463 patent, other than
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`being oriented vertically, and specifying the desired common mode generically as
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`Vcm. (Id.; cf. Ex. 1005, 12; Ex. 2002, ¶38.)
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`Like the conventional CMFB circuit described in Section II.A, Oliaei’s
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`feedback (509, 511) and fly (512, 513) capacitors are alternately connected and
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`disconnected on clock phases, Φ1 and Φ2, respectively. (Ex. 1007, 5:51-53.) This
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`switching operation causes the CMFB circuit to “measure[] the common mode
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`components of signals Vop and Vom as needed to adjust Vcntrl, the control voltage
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`that is fed back to produce the desired common mode voltage.” (Id., 5:56-60; Ex.
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`2002, ¶39.)
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`Oliaei observes that, in conventional CMFB circuits, “[t]he capacitive load
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`of the amplifier is larger when the switches 502 are closed [(i.e., during the first
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`clock phase Φ1)].” (Ex. 1007, 5:61-62.) Accordingly, Oliaei’s Figure 6,
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`reproduced below, provides a nominally identical load at the output terminal on
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`different clock phases. (Id., 6:7-15; see also Pet., 29 (“With this addition, the
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`capacitive load impedance seen by the differential output is the same in both
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`phases, thus reducing common-mode error variation”); Ex. 2002, ¶40.)
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`Ex. 1007, Fig. 5 (two copies, rotated)
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`Ex. 1007, Fig. 6 (rotated)
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`As Oliaei itself admits, the Figure 6 embodiment is simply two sets of the
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`Figure 5 embodiment: “the combination of 2 sets of the circuits shown in Figure
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`5, hence the name symmetric SC-CMFB.” (Ex. 1007, 6:8-10; see also Pet., n.1, 29
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`(“The circuit illustrated in Oliaei’s Figure 6…form[s] a symmetrical circuit that is
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`effectively a combination of two sets of the circuit 500”); Ex. 1002, n.6, ¶99.) This
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`is illustrated in the figures above, in which on top is shown two copies of Figure 5,
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`oriented to more clearly depict how Figure 6 (below) is merely a combination of
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`two sets of the circuit in Figure 5. The first circuit (top, left) provides a feedback
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`signal on clock phase Φ1, when switches 604 are closed connecting the first circuit
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`to produce a feedback signal. During phase Φ1, switches 606 are open, meaning
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`the second circuit is disconnected from the first circuit and thus prevented from
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`adjusting the feedback signal generated by the first circuit. This configuration is
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`reversed during clock phase Φ2, when switches 606 are closed and switches 604
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`are open. Figure 7 shows that clock phase Φ1 and Φ2 are non-overlapping, meaning
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`there is no point in time when both sets of switches 604 and switches 606 are
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`closed. (Ex. 2002, ¶41.)
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`(Ex. 1007, Fig. 7.)4
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`Oliaei did not purport to improve on conventional CMFB circuits in any
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`w