Patent No. 7,012,463
`Petition For Inter Partes Review
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`
`v.
`
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 7,012,463
`
`Inter Partes Review No.: IPR2020-01336
`
`____________________________________________
`
`DECLARATION OF DR. DOUGLAS HOLBERG
`IN SUPPORT OF PETITIONER XILINX’S REPLY
`TO PATENT OWNER’S RESPONSE BRIEF IN THE
`INTER PARTES REVIEW OF U.S. PAT. NO. 7,012,463
`
`

`

`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ........................................................................................... 1
`
`DR. KINGET’S ANALYSIS .......................................................................... 1
`
`III. MY ANALYSIS .............................................................................................. 4
`
`IV. CONCLUDING STATEMENT ....................................................................11
`
`ii
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`

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`I.
`
`INTRODUCTION
`
`1.
`
`Supplemental to the declaration I provided on July 20, 2020, which is
`
`incorporated herein by reference, I have been asked by Xilinx, Inc. and Xilinx Asia
`
`Pacific Pte. Ltd. (“Xilinx”) to opine on the analysis undertaken by Dr. Peter Kinget
`
`as described in his declaration dated April 29, 2021 (“Kinget Declaration”), and
`
`more particularly at Paragraphs 87 – 105 of the Kinget Declaration.
`
`2.
`
`The analysis provided in this supplemental declaration is based on my
`
`education and experience as an engineer, and upon my knowledge of CMOS
`
`integrated circuit design. In addition to the documents I identified in my original
`
`declaration, I have also considered Dr. Kinget’s declaration (Ex. 2002) and Patent
`
`Owner’s Response dated April 29, 2021.
`
`
`
`II. DR. KINGET’S ANALYSIS
`
`3.
`
`I am familiar with the tools used by Dr. Kinget in his analysis. More
`
`specifically, I am familiar with the LTSpice simulation tool Dr. Kinget employed
`
`to create the schematics for the circuits he describes in Paragraphs 89 through 93
`
`of the Kinget Declaration.
`
`4.
`
`I am also familiar with the combined simulation test bench that Dr.
`
`Kinget employed to compare the performance of the three types of common-mode
`
`feedback circuits (the “unmodified CMFB circuit in Figure 5 of Oliaei, Petitioner’s
`
`- 1 -
`
`

`

`proposed modifications to Figure 5 of Oliaei, and the `463 patent’s improved
`
`CMFB circuit applied to Olieaie’s folded-cascode amplifier”). For clarity, I will
`
`henceforth use the term “Oliaei/Vittoz Circuit” when referring to what Dr. Kinget
`
`describes as “Petitioner’s proposed modifications to Figure 5 of Oliaei.”
`
`5.
`
`Based upon my experience as a circuit designer, I believe that the
`
`parameter values selected by Dr. Kinget, as described in Paragraph 98 of the
`
`Kinget Declaration are not unreasonable values – but certainly are not the only
`
`reasonable values that a POSITA would consider in order to evaluate the
`
`performance of the Oliaei/Vittoz Circuit.
`
`6.
`
`Dr. Kinget’s analysis provides only a single simulation using only a
`
`single set of parameter values. Ex. 2002, ¶¶97-98. A POSITA would not have
`
`reached a definitive conclusion regarding the performance of the Oliaei/Vittoz
`
`Circuit, or the other circuits simulated by Dr. Kinget, based upon such a limited
`
`data set1. Rather, a POSITA would have undertaken routine investigation and
`
`experimentation in order to evaluate circuit performance.
`
`7.
`
`In fact, Dr. Kinget’s results, reproduced below, show that for at least
`
`one criterion the Oliaei/Vittoz Circuit performed better than Oliaei’s unmodified
`
`
`1 While there may be instances in which the results of a single circuit simulation are so at odds
`with expectations or so extreme that a conclusion could be drawn based upon that single
`simulation, the results of Dr. Kinget’s simulation, as described in Paragraph 99 of the Kinget
`Declaration are not of that nature.
`
`2
`
`

`

`circuit. Specifically, Dr. Kinget’s simulation results show that the common-mode
`
`variation for Oliaei’s unmodified circuit (the curve shown in red) is about 5 mV,
`
`whereas the common-mode variation for the Oliaei/Vittoz Circuit (the curve shown
`
`in blue) is around only 1 mV (comparable to the common-mode variation of the
`
``463 Patent circuit simulation, in fact, as shown by the purple curve). Ex. 2002,
`
`¶99.
`
`Ex. 2002, ¶99 (annotated)
`
`
`
`8.
`
`A POSITA would recognize that reducing common-mode variation is
`
`desirable, as recognized by the `463 Patent. Ex. 1001, 1:40-67. A POSITA would
`
`further recognize from Dr. Kinget’s simulation results that Oliaei/Vittoz Circuit
`
`(blue curve) provides improved performance in this regard relative to Oliaei’s
`
`unmodified circuit (red curve). At a minimum, this result would have prompted
`
`further investigation and experimentation.
`
`3
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`

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`
`
`III. MY ANALYSIS
`
`9.
`
`I do not believe that a POSITA must (or even necessarily would) run
`
`computer simulations in order to understand the basic operation of a circuit (such
`
`as the Oliaei/Vittoz Circuit). Based upon my years of experience in working with
`
`POSITAs, I believe a POSITA would be able to understand the basic functioning
`
`of such a circuit by analyzing the schematic (when combined with the POSITA’s
`
`education and experience). In fact, I describe in my original declaration how a
`
`POSITA would understand the operation of Oliaei’s circuits, both alone and in
`
`combination with Vittoz’s teaching based upon the references’ schematics and
`
`general knowledge and skill of a POSITA. Ex. 1002, e.g., ¶¶98-105, 123-125, 221-
`
`249, 261-272.
`
`10. However, I recognize that circuit simulations (e.g. SPICE) are
`
`necessary for evaluating circuits prior to committing them to fabrication. One of
`
`the key ways that circuit simulations are used by a POSITA is to quickly and
`
`inexpensively “change” various components and their values (without the need to
`
`actually construct a physical circuit) in order to investigate how those components
`
`and values impact circuit performance.
`
`11.
`
`In my analysis, as described in the following paragraphs, I undertook
`
`what I believe to be the type of routine investigation and experimentation that a
`
`4
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`

`

`POSITA would undertake in order to evaluate the Oliaei/Vittoz Circuit using
`
`computer simulation.
`
`12. Based upon the description and the netlist provided in his declaration,
`
`I reconstructed Dr. Kinget’s simulation of the three circuits that he simulated. My
`
`test bench schematic is shown below and represents what Dr. Kinget describes in
`
`his declaration at Paragraphs 89 through 98, including using the component values
`
`Dr. Kinget used. Attached hereto as Appendix A is the listing of the netlist for the
`
`simulation I ran.
`
`
`
`5
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`

`

`Figure 1: Simulation of the Circuit Dr. Kinget Presented
`
`13. Not surprisingly, the results of my simulation closely track that of Dr.
`
`Kinget when the same component values are used, as shown below.
`
`
`
`
`
`
`
`Figure 2:Results Using Dr. Kinget’s Values
`
`14. The results of this initial simulation gave me sufficient reason to
`
`investigate the Oliaei/Vittoz Circuit further. I recognized, as would a POSITA, that
`
`different component values could impact the results of the circuit performance,
`
`including capacitor values, and switch sizes, etc.
`
`6
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`

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`15. Dr. Kinget testified he selected a 1:10 ratio (size of precharging
`
`capacitors relative to feedback capacitors) for his simulation, based upon the
`
`teachings of Johns & Martin (Ex.1005). Ex. 2002, ¶98. I note that Johns & Martin
`
`provides a range of values for such applications, including a 1:4 ratio. Ex.1005,
`
`p.691. I re-ran the simulation using the 1:4 capacitor ratio suggested by Johns &
`
`Martin. Ex.1005, p.691. The results of the simulation are reproduced below and
`
`show the Oliaei/Vittoz Circuit (blue curve) has improved common-mode level
`
`performance relative to the unmodified Oliaei circuit (red curve). Further, these
`
`results are significantly improved relative to Dr. Kinget’s sole simulation.
`
`
`
`
`
`Figure 3: Results Using 1:4 Capacitor Ratio
`
`16. Another parameter that would occur to a POSITA is to vary the size
`
`of the switches used in the circuit. Dr. Kinget used switches with a 2 µm / 0.18 µm
`
`width to “provide a small enough RC time constant for effective operation of the
`
`CMFB circuit.” Ex. 2002, ¶98. A POSITA would have recognized that acceptable
`
`operation of the circuit can be obtained with various switch sizes, including
`
`7
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`

`

`minimum switch sizes (for the given technology node and application), as taught
`
`by Johns & Martin. Ex. 1005, p. 291. I assume for the purposes of this declaration
`
`that the minimum switch size for a 0.18um process is 0.4 µm / 0.18 µm. When
`
`using a minimum size switch, the options for the dummy transistor is minimum as
`
`well (one cannot make a transistor less than minimum size). Using a minimum
`
`switch size of a 0.4 µm / 0.18 µm, for instance, also provides a small enough RC
`
`time constant for effective operation of the CMFB circuit, as shown by the
`
`following simulation results. Because I was using a minimum switch size I could
`
`not make a smaller dummy switch, so both the switch and dummy were simulated
`
`as the same size. As also shown below, this simple change in the switch and
`
`dummy sizes also significantly improves the common-mode level performance of
`
`the Oliaei/Vittoz Circuit (blue curve) relative to the unmodified Oliaei circuit (red
`
`curve). Comparing these results to Dr. Kinget’s sole simulation results further
`
`demonstrates significantly improved performance relative to the parameters Dr.
`
`Kinget selected.
`
`
`
`8
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`

`

`Figure 4: Results Using Minimum Switch Sizes
`
`17. Based upon the trend between the 1:10 capacitor ratio and the 1:4 capacitor
`
`ratio (comparing Figures 2 and 3 above), a POSITA would likely consider further
`
`decreasing the ratio of the capacitors to see if the trend continued toward further
`
`improved results. While I recognize Johns & Martin cautions against using
`
`precharging capacitors that are too large (as well as against using capacitor that are
`
`too small), the range is provided as a guideline (“might be between one-quarter and
`
`one-tenth”) and not as a bright-line rule that would discourage a POSITA from
`
`experimenting outside of the range. Ex. 1005, 291. For example, it would be
`
`reasonable to take the trend to a logical conclusion of a 1:1 ratio as a matter of
`
`routine experimentation. Consistent with how a POSITA might approach the
`
`evaluation, I reran the simulation an additional time, this time employing a 1:1
`
`capacitor ratio value along with a minimum switch size of 0.4µ/0.18 µ. The results,
`
`reproduced below, show improved common-mode level performance of the
`
`Oliaei/Vittoz Circuit (blue curve) relative to Oliaei’s unmodified circuit (red
`
`curve). In fact, this simulation demonstrates performance by the Oliaei/Vittoz
`
`Circuit (blue curve) comparable to the circuitry of the `463 Patent (purple curve).
`
`
`
`9
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`

`

`
`
`18. As the above described simulations demonstrate, the (simulated)
`
`performance of the CMFB circuits considered by Dr. Kinget can be significantly
`
`impacted by relatively simple changes in component. Fortunately, these impacts
`
`are well-understood and predictable (as demonstrated by the availability of
`
`simulation tools such as used by Dr. Kinget himself).
`
`19. The simulations I ran are merely representative of the types of simulation
`
`runs a POSITA would undertake in order to evaluate the performance of a CMFB
`
`circuit, such as the types considered in Dr. Kinget’s declaration. In my personal
`
`experience of circuit design, I would anticipate running many such simulations
`
`before reaching any conclusions regarding the feasibility or performance of a
`
`proposed circuit modification.
`
`20. With all due respect to Dr. Kinget, if an engineer reporting to me concluded
`
`that the Oliaei/Vittoz circuit would not perform well, based upon only a single
`
`simulation using only a single set of component/parameter values, I would
`
`consider that engineer’s work to be sub-par and unacceptable. In my opinion, Dr.
`
`Kinget’s single simulation is not representative of how a POSITA would evaluate
`
`10
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`

`

`the Oliaei/Vittoz Circuit and does not support his conclusion that a POSITA would
`
`not have been motivated to combine the references. Rather, in addition to analysis,
`
`I think that a relatively few number of computer simulations would support a
`
`POSITA’s motivation to combine Oliaei and Vittoz as I outlined in my original
`
`declaration. Ex. 1002, ¶¶200-218.
`
`IV. CONCLUDING STATEMENT
`
`
`
`21.
`
`In my original declaration, I identified and factually supported
`
`numerous rationales under which a POSITA would have found it obvious to
`
`combine Oliaei and Vittoz. Ex. 1002, ¶¶200-21. Dr. Kinget’s analysis, using only a
`
`single simulation with only a single set of parameter values, does not reflect how a
`
`POSITA would consider that combination. In fact, as my own simulations
`
`demonstrate, a POSITA would have found ample reason to combine Oliaei and
`
`Vittoz using routine experimentation.
`
`22. Under penalty of perjury, all statements made herein of my own
`
`knowledge are true, and I believe that all statements made herein on information
`
`and belief to be true. I have been warned and I am aware that willful false
`
`statements are punishable by fine or imprisonment or both under Section 1001 of
`
`Title 18 of the United States Code.
`
`23.
`
`In signing this Declaration, I understand that the Declaration will be
`
`filed as evidence in a contested case before the Patent Trial and Appeal Board of
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`11
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`

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`the United States Patent and Trademark Office. I acknowledge that I may be
`
`subject to cross-examination in the case and that cross-examination will take place
`
`in the United States. If cross examination is required of me, I undertake to appear
`
`within the United States during the time allotted for cross-examination, and within
`
`the limits of my ability so to do.
`
`I declare under penalty of perjury that the foregoing is true and correct.
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`Executed on _22 July 2021_____.
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`__________________________________
`Dr. Douglas Holberg
`
`12
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`

`

`
`
`V.
`
`
`Appendix A: Kinget duplicated simulation
`
`* F:\Documents\Docs\Consulting\Xilinx\SlaterMatsil\US7012463\Simulations 463\Kinget_\Kinget_1.asc
`Vclock1 clock1 0 PULSE(0 1.8 0 {tr} {tr} {Ton} {Tperiod})
`Vclock2 clock2 0 PULSE(0 1.8 {Tperiod/2} {tr} {tr} {Ton} {Tperiod})
`V1 vdd 0 {Vdd}
`V2 vincm 0 {Vdd/2}
`V3 cmref 0 {Vcmref}
`XX16 clock1 clock2 vdd 0 clock1_2 clock2_2 clk_buffer
`XX12 vincm vincm vdd 0 pbias_2 fb_2 biasn_2 voutn_2 voutp_2 folded_cascode
`XX15 clock1 clock2 vdd 0 clock1_1 clock2_1 clk_buffer
`XX13 vincm vincm vdd 0 pbias_1 fb_1 biasn_1 voutn_1 voutp_1 folded_cascode
`XX14 clock1_1 clock2_1 cmref biasn_1 0 voutn_1 voutp_1 fb_1 sc_cmfb
`XX17 clock1 clock2 vdd 0 clock1_3 clock2_3 clk_buffer
`XX11 vincm vincm vdd 0 pbias_3 fb_3 biasn_3 voutn_3 voutp_3 folded_cascode
`XX9 clock1_3 clock2_3 cmref biasn_3 0 voutn_3 voutp_3 fb_3 sc_cmfb_imp_dummy params: fly_scale=1
`XX10 clock1_2 clock2_2 cmref biasn_2 0 voutn_2 voutp_2 fb_2 sc_cmfb_imp_dummy
`
` *
`
` block symbol definitions
`.subckt clk_buffer clkin1 clkin2 VDD VSS clkout1 clkout2
`M11 out1 clkin1 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M12 out1 clkin1 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M13 out2 out1 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M14 out2 out1 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M15 out3 out2 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M16 out3 out2 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M17 clkout1 out3 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M18 clkout1 out3 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`C1 clkout1 VSS {Cclock}
`M2 out1_2 clkin2 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M1 out1_2 clkin2 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M3 out2_2 out1_2 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M4 out2_2 out1_2 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M5 out3_2 out2_2 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M6 out3_2 out2_2 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`M7 clkout2 out3_2 VDD VDD PMOS18 l=0.18u w={Wp} ad={Wp*1u} as={Wp*1u} pd={Wp} ps={Wp} m={mp}
`M8 clkout2 out3_2 VSS VSS NMOS18 l=0.18u w={Wn} ad={Wn*1u} as={Wn*1u} pd={Wn} ps={Wn} m={mn}
`C2 clkout2 VSS {Cclock}
`.param Wn = 1u
`.param mn = 1
`.param Wp = 3u
`.param mp = 1
`.param Cclock = 200f
`.ends clk_buffer
`
`.subckt folded_cascode vinp vinn VDD VSS pbias nbias_in nbias_out voutn voutp
`M5 CS pbias VDD VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=6
`M8 voutn pbias VDD VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=3
`M1 pbias pbias VDD VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=3
`M9 voutp pbias VDD VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=3
`I1 pbias VSS {Ibias}
`M4 fcasn vinp CS VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=3
`M3 fcasp vinn CS VDD PMOS18 l=0.54u w=30u ad=30p as=30p pd=30u ps=30u m=3
`M6 fcasn nbias_in VSS VSS NMOS18 l=0.54u w=10u ad=10p as=10p pd=10u ps=10u m=6
`M7 fcasp nbias_in VSS VSS NMOS18 l=0.54u w=10u ad=10p as=10p pd=10u ps=10u m=6
`M11 voutn casn fcasn VSS NMOS18 l=0.54u w=10u ad=10p as=10p pd=10u ps=10u m=3
`M10 voutp casn fcasp VSS NMOS18 l=0.54u w=10u ad=10p as=10p pd=10u ps=10u m=3
`CLp voutp VSS {Cload}
`CLn voutn VSS {Cload}
`I2 VDD nbias_out {Ibias}
`M2 nbias_out nbias_out VSS VSS NMOS18 l=0.54u w=10u ad=10p as=10p pd=10u ps=10u m=3
`E1 casn VSS VDD VSS 0.5
`.param Ibias = 20u
`.param Cload = 5p
`.ends folded_cascode
`
`
`13
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`.subckt sc_cmfb clock1 clock2 cmref biasn VSS voutn voutp fb
`Msw2 voutn clock2 cn VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw3 fb clock2 b VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw5 cn clock1 cmref VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw6 b clock1 biasn VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw1 voutp clock2 cp VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw4 cp clock1 cmref VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Cbfly1 cn b {Cfly}
`Cafly1 cp b {Cfly}
`Cbcmfb1 voutn fb {Ccmfb}
`Cbcmfb2 voutp fb {Ccmfb}
`.param Ccmfb = 1000f
`.param fly_scale = 10
`.param Cfly = {Ccmfb/fly_scale}
`.param Wswitch = 2u
`.ends sc_cmfb
`
`.subckt sc_cmfb_imp_dummy clock1 clock2 cmref biasn VSS voutn voutp fb
`Msw2 voutn clock2 cn VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw3 fb clock2 b VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw5 cn clock1 cmref VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw6 b clock1 biasn VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw1 voutp clock2 cp VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Msw4 cp clock1 cmref VSS NMOS18 l=0.18u w={Wswitch} ad={Wswitch*1u} as={Wswitch*1u} pd={Wswitch} ps={Wswitch}
`Cbfly1 cn b {Cfly}
`Cafly1 cp b {Cfly}
`Cbcmfb1 voutn fb {Ccmfb}
`Cacmfb1 voutp fb {Ccmfb}
`Msw7 fb clock1 fb VSS NMOS18 l=0.18u w={Wdummy} ad={Wdummy*1u} as={Wdummy*1u} pd={Wdummy} ps={Wdummy}
`C2 biasn VSS {C2}
`C1 b VSS {C1}
`.param Ccmfb = 1000f
`.param fly_scale = 10
`.param Cfly = {Ccmfb/fly_scale}
`.param Wswitch = 2u
`.param Wdummy = 1u
`.param C1 = 530f
`.param C2 = 400f
`.ends sc_cmfb_imp_dummy
`
`.model NMOS NMOS
`.model PMOS PMOS
`.lib F:\Documents\LTspiceXVII\lib\cmp\standard.mos
`.param Tperiod = 625n
`.param td1 = 0
`.param tr_factor = 4000
`.param tr=Tperiod/tr_factor
`.param tnov=Tperiod/100
`.param Ton=Tperiod/2-2*tr-tnov
`.tran 0.01n 100u
`.include p18_cmos_models_tt.inc
`.param Vdd = 1.8
`.param Vcmref = 0.90
`.param Ibias = 20u
`.options reltol=1e-5
`.options abstol=1e-14
`.options chgtol=1e-16
`.options vntol=1e-8
`* Simulation Control
`* Parameters
`* Transistor models
`.backanno
`.end
`
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