I 1111111111111111 11111 111111111111111 11111 11111 1111111111 lll111111111111111
`
`US007286075B2
`
`(IO) Patent No.: US 7,286,075 B2
`
`c12) United States Patent
`
`(45)Date of Patent:
`
`Hennessy et al.
`
`Oct. 23, 2007
`
`(54)ANALOG TO DIGITAL
`CONVERTER WITH
`DITHER
`
`5,852,415 12/1998 Cotter et al.
`
`
`
`A
`
`
`
`6,486,806 Bl 11/2002 Munoz
`
`6,747,522 B2 * 6/2004 Pietruszynski
`
`
`et al. ...................... 331/177 R
`(75)Inventors: Michael Hennessy, Limerick (IE);
`
`
`
`
`
`
`
`6,784,814 Bl* 8/2004 Nair et al. .................. 341/118
`
`
`Christopher Peter Hurrell, Cookham
`
`
`
`6,850,181 Bl* 2/2005 Tsinker ....................... 341/163
`(GB); Colin Gerard Lyden, Baltimore
`
`
`6,914,550 B2 * 7/2005 Cai ............................ 341/155
`(IE)
`
`
`
`7,015,853 Bl* 3/2006 Wolff et al .................. 341/155
`
`
`
`7,023,372 Bl* 4/2006 Singh et al ................. 341/155
`
`
`
`
`7,026,975 Bl* 4/2006 Steward et al. ............. 341/161
`
`2004/0100397 Al 5/2004 Abdelatty
`
`(73) Assignee: Analog Devices, Inc., Norwood, MA
`
`
`
`
`
`(US)
`
`OTHER PUBLICATIONS
`
`( *) Notice: Subject to any disclaimer, the term of this
`
`
`
`
`
`patent is extended or adjusted under 35
`
`U.S.C. 154(b) by O days.
`
`
`
`International Search Report in PCT/US2006/044122, Feb. 27, 2007.
`
`
`
`
`
`
`
`(21) Appl. No.: 11/273,196
`
`
`
`
`
`Nov. 14, (22)Filed: 2005
`
`* cited by examiner
`
`(74)Attorney, Agent, or Firm-Wolf, Greenfield & Sacks,
`
`Primary Examiner-Peguy JeanPierre
`
`
`
`
`
`P.C.
`
`(65)
`
`
`
`Prior Publication Data
`
`
`
`US 2007/0109168 Al May 17, 2007
`
`(57)
`
`ABSTRACT
`
`(56)
`
`
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`An analog to digital converter is provided comprising an
`
`
`
`
`
`(51)Int. Cl.
`
`
`
`array of capacitors for sampling an input, each capacitor
`H03M 1112 (2006.01)
`
`
`
`having at least one associated switch for controllably con
`
`
`
`
`(52)U.S. Cl. ....................... 341/172; 341/155; 341/144
`
`
`
`
`
`necting a terminal of the capacitor to a first reference voltage
`
`
`
`(58)Field of Classification Search ................ 341/144,
`
`
`
`
`or to a second reference voltage; and a sequence generator
`
`341/155, 172,122,120
`
`
`
`
`
`for generating a sequence of bits, wherein during sampling
`
`
`
`See application file for complete search history.
`
`
`of the input onto the array of capacitors an output of the
`
`
`
`
`sequence generator is supplied to the switches of a first
`
`
`
`
`group of capacitors to control whether a given capacitor
`
`
`
`
`within the first group is connected by its associated switch
`
`
`to the first reference voltage or to the second reference
`
`
`
`
`4,831,381 A * 5/1989 Hester ........................ 341/172
`voltage.
`
`
`5,010,339 4/1991 Giangano et al.
`A
`
`
`5,621,409 4/ 1997 Cotter et al.
`A
`
`5,675,340 10/ 1997 Hester
`A
`
`
`
`
`
`25 Claims, 3 Drawing Sheets
`
`10
`
`14
`c'
`
`N·DAC
`
`MAINP·DAC
`
`3
`Ce MSBs
`
`40
`
`Initial Sampling
`
`State of
`Reference
`
`switches defined
`
`by output of
`
`Pseudo Random
`Generator
`
`After sampling Phase \he
`
`
`
`Reference switches return
`
`to the initial SAR state
`
`in preparation for bit trial testing
`
`SAR
`
`44
`
`42
`
`70
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 1
`
`
`
`US007286075B2
`
`(IO) Patent No.: US 7,286,075 B2
`
`c12) United States Patent
`
`(45)Date of Patent:
`
`Hennessy et al.
`
`Oct. 23, 2007
`
`(54)ANALOG TO DIGITAL
`CONVERTER WITH
`DITHER
`
`5,852,415 12/1998 Cotter et al.
`
`
`
`A
`
`
`
`6,486,806 Bl 11/2002 Munoz
`
`6,747,522 B2 * 6/2004 Pietruszynski
`
`
`et al. ...................... 331/177 R
`(75)Inventors: Michael Hennessy, Limerick (IE);
`
`
`
`
`
`
`
`6,784,814 Bl* 8/2004 Nair et al. .................. 341/118
`
`
`Christopher Peter Hurrell, Cookham
`
`
`
`6,850,181 Bl* 2/2005 Tsinker ....................... 341/163
`(GB); Colin Gerard Lyden, Baltimore
`
`
`6,914,550 B2 * 7/2005 Cai ............................ 341/155
`(IE)
`
`
`
`7,015,853 Bl* 3/2006 Wolff et al .................. 341/155
`
`
`
`7,023,372 Bl* 4/2006 Singh et al ................. 341/155
`
`
`
`
`7,026,975 Bl* 4/2006 Steward et al. ............. 341/161
`
`2004/0100397 Al 5/2004 Abdelatty
`
`(73) Assignee: Analog Devices, Inc., Norwood, MA
`
`
`
`
`
`(US)
`
`OTHER PUBLICATIONS
`
`( *) Notice: Subject to any disclaimer, the term of this
`
`
`
`
`
`patent is extended or adjusted under 35
`
`U.S.C. 154(b) by O days.
`
`
`
`International Search Report in PCT/US2006/044122, Feb. 27, 2007.
`
`
`
`
`
`
`
`(21) Appl. No.: 11/273,196
`
`
`
`
`
`Nov. 14, (22)Filed: 2005
`
`* cited by examiner
`
`(74)Attorney, Agent, or Firm-Wolf, Greenfield & Sacks,
`
`Primary Examiner-Peguy JeanPierre
`
`
`
`
`
`P.C.
`
`(65)
`
`
`
`Prior Publication Data
`
`
`
`US 2007/0109168 Al May 17, 2007
`
`(57)
`
`ABSTRACT
`
`(56)
`
`
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`An analog to digital converter is provided comprising an
`
`
`
`
`
`(51)Int. Cl.
`
`
`
`array of capacitors for sampling an input, each capacitor
`H03M 1112 (2006.01)
`
`
`
`having at least one associated switch for controllably con
`
`
`
`
`(52)U.S. Cl. ....................... 341/172; 341/155; 341/144
`
`
`
`
`
`necting a terminal of the capacitor to a first reference voltage
`
`
`
`(58)Field of Classification Search ................ 341/144,
`
`
`
`
`or to a second reference voltage; and a sequence generator
`
`341/155, 172,122,120
`
`
`
`
`
`for generating a sequence of bits, wherein during sampling
`
`
`
`See application file for complete search history.
`
`
`of the input onto the array of capacitors an output of the
`
`
`
`
`sequence generator is supplied to the switches of a first
`
`
`
`
`group of capacitors to control whether a given capacitor
`
`
`
`
`within the first group is connected by its associated switch
`
`
`to the first reference voltage or to the second reference
`
`
`
`
`4,831,381 A * 5/1989 Hester ........................ 341/172
`voltage.
`
`
`5,010,339 4/1991 Giangano et al.
`A
`
`
`5,621,409 4/ 1997 Cotter et al.
`A
`
`5,675,340 10/ 1997 Hester
`A
`
`
`
`
`
`25 Claims, 3 Drawing Sheets
`
`10
`
`14
`c'
`
`N·DAC
`
`MAINP·DAC
`
`3
`Ce MSBs
`
`40
`
`Initial Sampling
`
`State of
`Reference
`
`switches defined
`
`by output of
`
`Pseudo Random
`Generator
`
`After sampling Phase \he
`
`
`
`Reference switches return
`
`to the initial SAR state
`
`in preparation for bit trial testing
`
`SAR
`
`44
`
`42
`
`70
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 1
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 2
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 3
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 4
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 5
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 8
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 9
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1001 Page 10
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