IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004
`
`269
`
`A 2.5-V 10-b 120-MSample/s CMOS Pipelined ADC
`Based on Merged-Capacitor Switching
`
`Sang-Min Yoo, Jong-Bum Park, Seung-Hoon Lee, and Un-Ku Moon
`
`Abstract—This work describes a 10-b multibit-per-stage
`pipelined CMOS analog-to-digital converter (ADC) incorporating
`the merged-capacitor switching (MCS)
`technique. The pro-
`posed MCS technique improves the signal processing speed and
`resolution of the ADC by reducing the required number of unit
`capacitors by half in comparison to a conventional ADC. The ADC
`resolution based on the proposed MCS technique can be extended
`further by employing a commutated feedback-capacitor switching
`(CFCS) technique. The prototype ADC achieves better than 53-dB
`signal-to-noise-and-distortion ratio (SNDR) at 120 MSample/s and
`54-dB SNDR and 68-dB spurious-free dynamic range (SFDR) for
`input frequencies up to Nyquist at 100 MSample/s. The measured
`differential and integral nonlinearities of the prototype are within
`0 40 LSB and
`0 48 LSB, respectively. The ADC fabricated
`in a 0.25- m CMOS occupies 3.6 mm2 of active die area and
`consumes 208 mW under a 2.5-V power supply.
`
`Index Terms—Analog-to-digital converter (ADC), merged-
`capacitor switching (MCS), multiplying ADC (MADC), pipeline.
`
`I. INTRODUCTION
`
`T HE dramatic growth in the high-tech sectors of the con-
`
`sumer market has created many unprecedented challenges
`in the area of integrated circuits. The present and future commu-
`nication systems including high-speed modems and broadband
`wired and wireless communication subsystems require increas-
`ingly higher performance analog-to-digital converters (ADCs).
`The required level of accuracy can exceed 10 b at the conversion
`speed of hundreds of megahertz. The conventional pipelined ar-
`chitecture has been widely employed to meet the required per-
`formance in this arena due to properly managed tradeoffs be-
`tween speed, power consumption, and die area [1]–[12]. Among
`a variety of pipelined ADCs, the multibit-per-stage architecture
`is more suitable for high resolution, as the single-bit-per-stage
`structure requires more stages, higher power consumption, and
`larger chip area. However, the multibit-per-stage architecture
`has a relatively low signal processing speed due to the reduced
`feedback factor in the closed-loop configuration of the ampli-
`fiers. In switched capacitor type multiplying digital-to-analog
`converters (MDACs) used in conventional pipelined ADCs, the
`
`Manuscript received June 2, 2003; revised October 17, 2003. This work was
`supported in part by the Ministry of Information and Communications, Korea,
`under the ITRC support Program and the IDEST of KAIST. This paper was
`recommended by Associate Editor M. Flynn.
`S.-M. Yoo was with the Department of Electronic Engineering, Sogang Uni-
`versity, Seoul 121 742, Korea. He is now with Samsung Electronics Company,
`Yongin 449 711, Korea.
`J.-B. Park and S.-H. Lee are with the Department of Electronic Engineering,
`Sogang University, Seoul 121 742, Korea (e-mail: hoonlee@sogang.ac.kr).
`U.-K. Moon is with the Department of Electrical and Computer Engineering,
`Oregon State University, Corvallis, OR 97331 USA.
`Digital Object Identifier 10.1109/TCSII.2004.827555
`
`Fig. 1. Proposed 10-b 120-MSample/s ADC.
`
`mismatch between capacitors limits the differential nonlinearity
`(DNL) of ADCs. This is because each DNL step is defined by
`the random process variation of each unit capacitor value. A
`common centroid geometry layout technique can improve this
`capacitor matching for DNL, but it can not have an effect on
`random mismatch [13]. Naturally, increasing the capacitor size
`can directly improve the capacitor matching accuracy, but at the
`added cost of increased load capacitance. This means the ampli-
`fiers would dissipate more power or the ADC sampling speed
`would have to be reduced.
`In this paper, the merged-capacitor switching (MCS) tech-
`nique is proposed to improve the sampling rate and the resolution
`of an ADC, resulting in a single-channel 10-b 120- MSample/s
`performance [14], [15]. The prototype ADC based on the MCS
`technique enjoys the benefit of employing only eight unit-size
`capacitors for a 4-b MDAC instead of 16 capacitors normally
`required in the conventional MDAC architecture. The MDAC
`structure incorporating the proposed MCS technique can also
`lend itself to the commutated feedback-capacitor switching
`(CFCS) technique, which can increase the ADC resolution
`(DNL) even more [14], [16]. This paper is organized as follows.
`The ADC architecture with the proposed MCS technique is
`discussed in Section II. Section III deals with the CFCS tech-
`nique based on the proposed MCS technique to achieve higher
`resolution. Circuit implementation is described in Section IV
`and the measured results of the prototype are summarized in
`Section V. Finally, the conclusions are given in Section VI.
`
`II. ADC ARCHITECTURE BASED ON PROPOSED
`MCS TECHNIQUE
`
`The block diagram of the proposed 10-b pipelined ADC
`is illustrated in Fig. 1. It is based on a conventional three-
`stage pipelined architecture. The ADC consists of an input
`
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`270
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`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004
`
`Fig. 2. Conventional 4-b MDAC.
`
`sample-and-hold amplifier (SHA), two 4-b MDACs, three 4-b
`subranging flash ADCs, and some extra supporting circuit
`blocks. Two nonoverlapping clock phases are internally gener-
`ated for concurrent operations of all stages to convert analog
`input signals to digital output codes. Each of the three stages
`generates a 4-b digital code from the flash ADC, and the digital
`codes are processed in the digital correction/redundancy logic
`yielding a final 10-b word.
`The proposed MCS technique, applied to capacitor arrays in
`the MDAC, merges two unit capacitors into one without af-
`fecting the performance of the remaining circuits of the ADC.
`This means the number of unit capacitors required in a conven-
`tional MDAC is reduced by 50%. For a given minimum-size
`unit capacitor, the operating speed of amplifiers can be increased
`with less power consumption since the total load capacitance is
`roughly reduced by a half. Alternately, the unit capacitor size
`may be doubled to obtain the better capacitor matching accu-
`racy while speed and power consumption remain unchanged.
`A conventional 4-b MDAC as shown in Fig. 2 has 16 unit
`capacitors, a residue amplifier, and a decoding circuit to con-
`trol the switches connected to the capacitors. During the sam-
`pling phase, all the MDAC capacitor bottom plates are con-
`nected to the analog input voltage
`, which is the output of the
`previous stage. During the following amplification phase, each
`bottom plate of capacitors
`to
`is connected to
`or
`, depending on the digital code generated by the flash
`ADC. The two remaining capacitors
`and
`are con-
`nected to the amplifier output,
`, for proper residue am-
`plification of 8 .
`The MCS technique as illustrated in Fig. 3 reduces the
`required number of MDAC capacitors by a half, by merging
`eight pairs of capacitors,
`,
`into eight new unit capacitors
`to
`. The function of the
`proposed MDAC employing the MCS is identical to that of
`the conventional MDAC. The only difference is that the signal
`ground (GND) is needed in the MCS technique, equivalent
`to when two different references (
`and
`) are
`applied to two unit capacitors in the conventional MDAC. It
`is noted, for example, that
`and
`of Fig. 3(a) are directly
`mapped to the function of
`in Fig. 3(b).
`The 4-b MDAC with the proposed MCS technique is imple-
`, GND,
`mented with eight unit capacitors connected to
`and
`, as shown in Fig. 4. The detailed connection of
`each capacitor bottom plate by the 4-b digital code from the
`flash ADC during MDAC residue amplification is summa-
`rized in Table I, where “0001” to “1111” in the left column
`
`Fig. 3. MDAC during amplification based on (a) conventional and (b) pro-
`posed MCS techniques.
`
`Fig. 4. The 4-b MDAC implementation based on the proposed MCS
`technique.
`
`TABLE I
`MDAC CAPACITOR SWITCHING DURING AMPLIFICATION BASED ON THE
`PROPOSED MCS TECHNIQUE
`
`are corresponding to the digital outputs from the 4-b flash
`subranging ADC and “F/B” indicates feedback connection.
`In a fully differential implementation, any fixed bias voltage
`can be employed so that the GND reference is not needed.
`The proposed fully differential 4-b MDAC is implemented as
`
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`

`

`YOO et al.: A 2.5-V 10-B 120-MSAMPLE/S CMOS PIPELINED ADC BASED ON MCS
`
`271
`
`Fig. 5. Fully differential 4-b MDAC based on the proposed MCS technique.
`
`shown in Fig. 5. In this prototype integrated circuit (IC) imple-
`was employed for GND to simplify layout
`mentation,
`and to minimize floating nodes, instead of using a floating
`differential reset switch as in [17]. With this bias voltage, the
`input common-mode voltage of the MDAC amplifier changes
`of
`). Considering
`approximately by 64 mV (
`some amount of positive common-mode charge injection
`from the pMOS sampling switches turning off, the effect is
`negligibly small in this multibit MDAC.
`
`III. RESOLUTION IMPROVEMENT BASED ON MCS TECHNIQUE
`
`A conventional CFCS technique that was developed for a 1-
`or 2-b per stage architecture with a single feedback capacitor
`in [16] can be extended to ADCs using the MCS technique.
`Since the conventional multibit MDAC architecture with dig-
`ital error correction uses two unit capacitors as a feedback ca-
`pacitor (Fig. 2), it is difficult to apply the CFCS technique di-
`rectly. Although the CFCS technique can be applied to a modi-
`fied MDAC architecture with digital error correction using one
`unit capacitor as the feedback capacitor, the resulting exten-
`sion to the multibit MDAC becomes very complex due to extra
`dummy capacitors. However, the MCS structure using a single
`feedback capacitor can easily lend itself to the CFCS technique
`as follows.
`The proposed 4-b MDAC based on both of the MCS and
`CFCS techniques is shown in Fig. 6. During the sampling phase,
`to
`are connected to the analog
`all the bottom plates of
`input voltage
`. During the amplification phase, one of the
`to
`is used as a feedback capacitor de-
`eight capacitors
`pending on the digital code from the flash ADC and the re-
`or GND.
`maining seven capacitors are connected to
`Table II shows how to connect the eight MDAC capacitors de-
`pending on the 4-b digital code. All the capacitors are utilized
`as the feedback capacitor according to the digital code.
`The corresponding residue plot of a typical 4-b MDAC is il-
`lustrated in Fig. 7. At the comparator decision boundary, the
`residue drop depends on the matching of the capacitors, which
`limits the DNL of the MDAC and the ADC. Capacitors with
`mismatches can be represented by
`
`for
`
`(1)
`
`Fig. 6. Proposed 4-b MDAC implementation based on the MCS and CFCS
`techniques.
`
`TABLE II
`MDAC CAPACITOR SWITCHING DURING AMPLIFICATION BASED ON
`PROPOSED MCS AND CFCS TECHNIQUES
`
`.
`where
`.
`Each error term represents the mismatch of the capacitor
`In the proposed MDAC employing only the MCS technique,
`for example, the residue drop at the transition point from
`“0001” to “0010” can be calculated as follows (refer to Fig. 7
`and Table I) :
`
`(2)
`(3)
`
`, are labeled in Fig. 7. If the
`, and
`,
`Voltages
`and
`are
`MDAC capacitors have no mismatch,
`and
`, respectively, generating the residue voltage drop
`. Due to mismatches, the induced error
`of
`results as the DNL at this transition. This result is similar to the
`conventional MDAC without the MCS technique. Expressions
`similar to (3) can be derived for all other transition points.
`
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`272
`
`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004
`
`Fig. 7. Residue plot of a 4-b MDAC based on the combined MCS and CFCS techniques.
`
`For an MDAC structure employing the MCS and CFCS tech-
`niques together, the residue drop with the same transition point
`from “0001” to “0010” can be calculated as follows (refer to
`Fig. 7 and Table II) :
`
`(4)
`
`(5)
`
`From (3) and (5), it is observed that the induced error at the
`same transition point is roughly reduced by a half, when the
`MCS and CFCS techniques are combined. The residue drops
`obtained at all other transition points also show similar trends.
`The reduced transition error at each residue drop (proportional
`to DNL) improves the ADC linearity. If desired, this can be
`further enhanced by increasing the unit capacitor size in the
`MDAC as much as the number of capacitors reduced by the
`MCS technique.
`In this paper, only the MCS technique is implemented in the
`prototype IC to obtain a high-speed operation of 120 MHz at
`10-b accuracy as described in Sections IV and V. The CFCS
`technique combined with the MCS technique for higher resolu-
`tion is verified only by simulation as follows. One hundred ADC
`samples are simulated to verify the resolution and yield im-
`provement. The DNL distributions of the simulated ADC sam-
`ples are shown in Fig. 8. The ADCs have a 4-stage pipelined
`architecture (4-4-4-5) to obtain 14-b outputs. The unit capac-
`itor mismatch of the conventional MDAC for simulation is set
`to 0.1% for a 12-b-level resolution, which is extracted from the
`measured prototype ADC [14]. The unit capacitor mismatch of
`the MDAC using both of the MCS and CFCS techniques is set
`assuming that the MCS MDAC capacitors employ
`to
`the increased capacitor size by a factor of two to obtain the same
`loading condition as the conventional MDAC. About 70% of the
`conventional ADCs are at a 12-b level and about 80% of the pro-
`posed ADCs using the MCS and CFCS techniques are at a 13-b
`level. If the proposed design techniques and the layout tech-
`niques to improve capacitor matching are combined together,
`
`Fig. 8. DNL distributions of simulated ADC samples.
`
`the resolution (DNL) of the prototype ADC can be extended
`significantly.
`
`IV. 10-B 120-MSAMPLE/S ADC IMPLEMENTATION
`
`A fully differential architecture is employed in all analog
`blocks to improve the converter performance. The ADC is op-
`input signal swing
`timized to operate with a maximum 2-
`with a 2.5-V supply voltage. The input SHA consists of CMOS
`switches, two input sampling capacitors, and a folded cascode
`amplifier with a loop gain bandwidth of 320 MHz. The ADC
`is optimized to handle both single-ended and differential input
`signals with a wide bandwidth for high dynamic performance
`up to 120-MHz sampling rate. The conventional two-sampling-
`capacitor architecture employed in the SHA is realized with
`small die area and low power consumption. Taking into consid-
`eration the thermal (kT/C) noise for 10-b accuracy, the sampling
`capacitance used in the SHA is 1.2 pF.
`Each MDAC consists of opamp, capacitor arrays, and re-
`lated switches. A two-stage Miller-compensated amplifier with
`a simulated dc gain of 100 dB is used in the MDAC and the
`proposed MCS technique is employed in the capacitor array.
`The unit capacitor size of the first- and second-stage MDAC
`is 0.2 pF and 0.1 pF, respectively, considering the adequate ca-
`pacitor matching and thermal (kT/C) noise for the required res-
`
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`YOO et al.: A 2.5-V 10-B 120-MSAMPLE/S CMOS PIPELINED ADC BASED ON MCS
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`273
`
`TABLE III
`ENCODING FROM THERMOMETER CODE TO BINARY CODE
`
`Fig. 9. Comparator preamp with reset switch.
`
`Fig. 10. Block diagram of the proposed encoding.
`
`olution in each stage. The two-stage opamp of the first-stage
`MDAC has a loop gain bandwidth of 240 MHz with a phase
`to ob-
`margin of 63 for an approximate feedback factor of
`tain a 7-b accurate settling time in less than 4 ns at the output.
`The preamps in the flash subranging ADCs employ a small
`pMOS reset switch at the outputs as shown in Fig. 9 for low
`power consumption and high-speed operation. The proposed
`encoder in the flash ADCs employs a logic-based two-step
`encoding scheme to reduce chip area and power consumption
`instead of a conventional ROM-based encoding [15]. Fig. 10
`shows the block diagram of the proposed encoding scheme
`and Table III illustrates the encoding from a thermometer
`code into a binary code implemented in the flash ADCs with
`redundant codes required for digital error correction. The
`proposed encoding circuit is partitioned into the coarse and
`fine encoders. Three bits of T11, T7, and T3 are used as inputs
`of the coarse encoder to select one group as inputs of the
`fine encoder between four groups of bits (T2-T1, T6-T5-T4,
`T10-T9-T8, and T14-T13-T12). Three bits of T11, T7, and
`T3 and the selected group of bits is passed to the coarse and
`fine encoders, which generate the two most significant bits
`and the two least significant bits, respectively. The number of
`MOS transistors and the power consumption required in the
`ROM-based encoder are reduced by a half compared with those
`of the logic-based encoder.
`
`V. PROTOTYPE MEASUREMENTS
`
`The proposed ADC was fabricated in a 0.25- m double-poly
`five-metal CMOS process. The prototype, shown in Fig. 11, oc-
`
`Fig. 11. Die photograph of the prototype ADC.
`
`mm ) active die area, and dissi-
`cupies 3.6-mm (
`pates 208 mW when operated with a 120-MHz clock and a 2.5-V
`supply. In the IC measurements setup, external low-pass and/or
`band-pass filters at the inputs suppress the harmonics and noise
`from the test signal generator and a transformer provides a clean
`single to differential input signal conversion. External buffers
`connected to the ADC digital output drive high-speed measure-
`ment equipment directly at the full conversion speed. As shown
`in Fig. 12, the measured differential and integral nonlineari-
`LSB and
`LSB at a 10-b ac-
`ties show less than
`curacy. Fig. 13(a) and (b) shows the measured signal spectrum.
`The measured signal-to-noise-and-distortion ratio (SNDR) with
`a 10-MHz input sine wave at 100 MSample/s is 58 dB, and it
`drops by 6 dB at 120 MSample/s due to the increased noise
`
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`274
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`IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 5, MAY 2004
`
`Fig. 12. Measured DNL and INL.
`
`Fig. 14. Measured dynamic performance. (a) SFDR and SNDR versus
`sampling frequency and (b) SFDR and SNDR versus input frequency.
`
`TABLE IV
`PERFORMANCE SUMMARY
`
`Fig. 13. Measured signal spectrum (

n = 10 MHz) (a) at 100 MSample/s and
`(b) at 120 MSample/s.
`
`floor level. However, the ADC achieves the spurious-free dy-
`namic range (SFDR) of 68 dB at 120 MSample/s.Fig. 14(a)
`and (b) shows the dynamic performance of the prototype ADC.
`At the increased sampling rate of 120 MHz and the input fre-
`quency of 3 MHz, the measured SNDR demonstrates 53 dB.
`The multibit-per-stage architecture incorporating the MCS tech-
`nique maintains the SNDR over 54 dB and the SFDR over 68 dB
`for signal frequencies up to Nyquist at a 100-MHz sampling
`rate. The measured results are summarized in Table IV.
`
`VI. CONCLUSION
`
`This paper describes circuit design techniques applicable to
`high-speed and high-resolution ADC systems. As a design ex-
`ample, a 10-b 120-MSample/s single-channel pipelined CMOS
`ADC has been demonstrated. The proposed MCS technique
`in a multibit-per-stage pipelined architecture achieves high
`conversion speed and high SFDR. It is verified in simulation
`that the ADC resolution can be improved further by employing
`the CFCS technique. Another important advantage of this MCS
`technique is that the amount of metal lines/routing, switches,
`and logic gates driving the affected capacitors is reduced by
`approximately 50%. This results in reduced load and parasitic
`capacitance, lower coupling noise, less power, and less chip
`area. The measurement results demonstrate the effectiveness of
`the MCS technique for speed and accuracy in the context of the
`multibit-per-stage pipelined ADC implementation.
`
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`

`YOO et al.: A 2.5-V 10-B 120-MSAMPLE/S CMOS PIPELINED ADC BASED ON MCS
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`275
`
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`