energy. In particular, ‘UP’ and ‘DOWN’ transitions consume energy
`2 J.
`of 0.5 CVref
`the proposed 10-bit ADC
`A single-ended implementation of
`implementation of the MCS SAR is shown in Fig. 2. The switching
`network, number of cycles and logic complexity is the same as that of
`the conventional switching scheme. The following Sections elaborate
`on switching energy and matching requirements for a 10-bit MCS SAR.
`
`inV
`
`8B
`
`refV
`refV
`
`cmV
`
`9B
`
`256C 128C
`B6
`B7
`
`64C
`B5
`
`32C
`
`2C
`B1
`
`C
`B0
`
`C
`
`B -B
`9
`
`logic
`
`0
`
`Dout
`conversion
`phase
`
`0B
`
`sampling
`phase
`
`9B
`
`B - B = 10 bit binary word
`9
`0
`
`Fig. 2 10-bit MCS-SAR ADC
`
`SAR switching energy: The average energy required for charging and
`discharging the SAR capacitor array determines the efficiency of the
`switching scheme [1]. The average switching energy for different
`switching schemes [1, 3, 5] was compared through a behavioural
`simulation of a 10-bit SAR ADC. The switching energy efficiency for
`different schemes is discussed below.
`The behavioural simulation of average switching energy for different
`schemes is shown in Fig. 3. With respect to the conventional switching tech-
`nique, the split-capacitor scheme [1] achieves 37.4% (Eavg ¼ 852.3 CVref
`2 ),
`the energy-saving scheme [3] achieves 58.7% (Eavg ¼ 563.8 CVref
`2 ) and
`the set and down scheme [5] achieves 81% (Eavg ¼ 255 CVref
`2 ). However,
`these switching schemes achieve energy savings at the cost of increased
`digital switching complexity, common mode variation and matching
`requirements.
`
`Merged capacitor switching based SAR ADC
`with highest switching energy-efficiency
`
`V. Hariprasath, J. Guerber, S.-H. Lee and U.-K. Moon
`
`A modified merged capacitor switching (MCS) scheme is proposed for
`the successive approximation register (SAR) analogue-to-digital con-
`verter (ADC). The conventional MCS technique previously applied
`to a pipelined ADC improves signal processing speed and, with use
`in the SAR ADC,
`this scheme achieves lowest switching energy
`among existing switching schemes. The MCS scheme achieves
`93.4% less switching energy as compared to the conventional
`architecture.
`
`Introduction: The capacitive array digital-to-analogue converter (D/A)
`in the feedback path of the SAR ADC approximates the sampled input
`voltage after every comparison. The conventional capacitor array switch-
`ing scheme of the SAR ADC is energy inefficient [1] in performing this
`approximation. This Letter explains the MCS scheme [2] for a SAR
`ADC and enumerates the advantages of this scheme in comparison
`with the present techniques.
`
`refV
`
`cmV
`
`cmV
`
`2C
`C C
`-V > 0.5V
`V
`ip
`in
`ref
`
`2C
`
`C C
`
`cmV
`
`cmV
`
`cmV
`
`cmV
`
`cmV
`
`cmV
`
`inV
`ipV
`
`2C
`
`C C
`
`2C
`
`C C
`
`cmV
`
`cmV
`
`cmV
`
`2C
`
`2C
`
`C C
`in-VVip
`
`C C
`
`>0
`
`cmV
`
`cmV
`cmV
`E = 0
`
`a
`
`cmV
`
`cmV
`2
`E = 0.5CV
`ref
`2
`E = 0.5CV
`ref
`cmV
`
`cmV
`
`2C
`C C
`-V > -0.5V
`V
`in
`ref
`
`ip
`
`2C
`
`C C
`
`refV
`
`cmV
`
`cmV
`
`refV
`
`cmV
`
`2C
`C
`C
`-V > -0.25V
`in
`ref
`
`ip
`
`V
`
`ref
`
`2
`
`2C
`
`C
`
`C
`
`ref
`
`2
`
`refV
`
`refV
`
`cmV
`
`2C
`C
`C
`-V >0.75V
`in
`ref
`
`ip
`
`V
`
`2C
`
`C
`
`C
`
` conventional [1]
` split-capacitor [1]
` energy saving [3]
` set and down [5]
` MCS
`
`200
`
`600
`400
`output code
`
`800
`
`1000
`
`1800
`
`1600
`
`1400
`
`1200
`
`1000
`
`800
`
`600
`
`400
`
`200
`
`0
`
`0
`
`ref
`
`energy, CV2
`
`Fig. 3 Switching energy comparison
`
`The MCS scheme is 93.4% (Eavg ¼ 84.7 CVref
`2 ) more efficient than
`the conventional switching scheme and is the highest reported switching
`energy efficiency among existing methods. Average switching energy
`for
`the different switching schemes and the proposed switching
`scheme is given below:
`
`2n+1−2i(2i − 1)CV 2
`ref J
`
`conventional scheme [1] Eavg ≃ (cid:2)n
`i=1
`energy saving scheme [3] Eavg ≃ 3.2n−3
`+ (cid:2)n
`2n+1−2i(2i−1 − 1)CV 2
`ref J
`i=3
`set and down scheme [5] Eavg ≃ (cid:2)n
`i=1
`
`2n−2−iCV 2
`ref J
`
`(1)
`
`(2)
`
`(3)
`
`E = 0.625CV
`
`refV
`
`cmV
`
`cmV
`
`cmV
`
`E = 0.125CV
`
`cmV
`
`refV
`
`cmV
`
`cmV
`
`E = 0.125CV
`
`ref
`
`2
`
`2C
`C
`C
`-V > -0.5V
`in
`ref
`
`ip
`
`V
`
`2C
`
`C
`
`C
`
`refV
`
`cmV
`
`cmV
`
`cmV
`
`2C
`C
`C
`-V > -0.75V
`in
`ref
`
`C
`
`C
`
`refV
`
`refV
`
`cmV
`
`ip
`2C
`
`V
`
`b
`
`E = 0.625CV
`
`ref
`
`2
`
`2C
`C
`C
`-V > 0.5V
`in
`
`ip
`
`V
`
`ref
`
`2C
`
`C
`
`C
`
`cmV
`
`cmV
`
`refV
`
`cmV
`
`2C
`C
`C
`-V > 0.25V
`in
`ref
`
`ip
`
`V
`
`2C
`
`C
`
`C
`
`refV
`
`cmV
`
`Fig. 1 Merged capacitor switching scheme and energy consumption
`
`Merged capacitor switching scheme: The energy consumption of a
`3-bit conventional switching scheme is described in [3]. The energy
`consumption is quite different for the ‘UP’ and ‘DOWN’ transitions
`[1]. In particular, the conventional SAR switching scheme consumes
`five times more energy for a ‘DOWN’ transition as compared to the cor-
`responding ‘UP’ transition, as illustrated in [3]. This inefficiency in
`switching energy leads to increased power consumption, dynamic
`settling errors in references and in turn limits the speed of the converter.
`A three-level capacitor array D/A with series capacitor coupling was
`used in [4] to partially address some of the above inefficiencies with
`the added cost of calibration and additional digital complexity.
`A 3-bit MCS scheme is shown in Figs. 1a and b. The input is sampled
`onto the virtual node. The first comparison does not consume any
`switching energy as compared to the conventional scheme. Further,
`‘UP’ and ‘DOWN’ transitions are symmetrical and consume equal
`
`ELECTRONICS LETTERS 29th April 2010 Vol. 46 No. 9
`
`Authorized licensed use limited to: Karen Rutherfod. Downloaded on December 17,2020 at 21:27:27 UTC from IEEE Xplore. Restrictions apply.
`
`Xilinx v. Analog
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`Analog 2009
`
`Page 1 of 2
`
`

`

`MCS scheme Eavg ≃ (cid:2)n−1
`i=1
`
`2n−3−2i × (2i − 1)CV 2
`ref J
`
`(4)
`
`results in improved INL and DNL performance as compared to a
`conventional architecture.
`
`INL and DNL requirements: The unit capacitor in the SAR ADC
`capacitor array is typically limited by matching requirements. The vari-
`ation in unit capacitors was assumed to be Gaussian distributed (N (0,
`s2)), where sis the standard deviation of matching between unit capaci-
`tors. Assuming Vref and GND as the reference levels for the capacitor
`array D/A, the INL and DNL requirement for an ‘n’ bit conventional
`converter can be derived as follows:
`(Ci + DCi)bi
`Vout(n) = Sn−1
`(5)
`Vref = Dout Vref
`i=1
`Ctotal
`(6)
`DNL(n) = Vout(n) − Vout(n − 1), INL(n) = Vout(n) − Videal(n)
`(7)
`E(DNL2)max = 2ns2, sDNL,max = 2n/2s
`E(INL2)max = 2n−2s2, sINL,max = 0.5 × 2n/2s
`(8)
`where Dout is the output code of the ADC, and Vout(n), DCi, Ctotal are the
`reference voltage, mismatch and total capacitance of the capacitive array
`D/A. The total capacitance was assumed to be constant for all the
`switching schemes. The INL and DNL requirements for the different
`switching schemes are shown in Table 1.
`
`Table 1: INL and DNL comparison for 10bit SAR ADC
`
`Conclusions: A three-level capacitor switching scheme is proposed for
`SAR ADC. This switching scheme achieves the highest switching
`energy efficiency among the existing switching schemes while reducing
`static linearity requirements. The MCS scheme also has relaxed match-
`ing requirements for the capacitor array without increasing the complex-
`ity of digital logic and switches.
`
`# The Institution of Engineering and Technology 2010
`15 March 2010
`doi: 10.1049/el.2010.0706
`V. Hariprasath, J. Guerber and U.-K. Moon (School of Electrical
`Engineering and Computer Science, Oregon State University, 1148
`Kelley Engineering Center, Corvallis, OR 97331-5501, USA)
`E-mail: venkatha@eecs.oregonstate.edu
`S.-H. Lee (Electronic Engineering, Sogang University, 1 Sinsoo-Dong,
`Mapo-Gu, Seoul 121-742, Korea)
`
`References
`
`1 Ginsburg, B.P., and Chandrakasan, A.P.: ‘An energy-efficient charge
`recycling approach for a SAR converter with capacitive DAC’. IEEE
`Int. Symp. on Circuits and Systems, May 2005, pp. 184–187
`2 Yoo, S., Park, J., Lee, S., and Moon, U.: ‘A 2.5-V 10-b 120-MSample/s
`CMOS pipelined ADC based on merged-capacitor switching’, IEEE
`Trans. Circuits Syst. II, 2004, 51, pp. 269–275
`3 Chang, Y., Wang, C., and Wang, C.: ‘A 8-bit 500-KS/s low power SAR
`ADC for bio-medical applications’. IEEE Asian Solid-State Circuits
`Conf., 2007, Jeju, Korea, November 2007, pp. 228–231
`4 Chen, Y., Tsukamoto, S., and Kuroda, T.: ‘A 9b 100MS/s 1.46 mW
`SAR ADC in 65 nm CMOS’. IEEE Asian Solid-State Circuits Conf.,
`Taipei, Taiwan, November 2009, pp. 145–148
`5 Liu, C., Chang, S., Huang, G., and Lin, Y.: ‘A 0.92 mW 10-bit 50-MS/s
`SAR ADC in 0.13 mm CMOS process’. Symp. on VLSI Circuits Digest
`of Technical Papers, June 2009, pp. 236–237
`
`16s
`
`16s
`16s
`√
`16s
`
`2
`
`Switching scheme sINL,max, LSB sDNL,max, LSB
`16s
`32s
`Conventional [1]
`√
`32s
`
`2
`32s
`32s
`√
`32s
`
`2
`
`Split-capacitor [1]
`
`Energy saving [3]
`Set and down [5]
`
`MCS
`
`The unit-capacitance for MCS SAR is twice that of the conventional
`SAR ADC when sized for the same kT/C noise consideration, which
`
`Authorized licensed use limited to: Karen Rutherfod. Downloaded on December 17,2020 at 21:27:27 UTC from IEEE Xplore. Restrictions apply.
`
`ELECTRONICS LETTERS 29th April 2010 Vol. 46 No. 9
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`Page 2 of 2
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