Trials@uspto.gov
`571-272-7822
`
`Paper 13
`Date: March 15, 2021
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`
`IPR2020-01559
`Patent 7,286,075 B2
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`Before JEFFREY S. SMITH, SCOTT A. DANIELS, and
`GEORGIANNA W. BRADEN, Administrative Patent Judges.
`DANIELS, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314, 37 C.F.R. § 42.4
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`571-272-7822
`
`Paper 13
`Date: March 15, 2021
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`
`IPR2020-01559
`Patent 7,286,075 B2
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`
`
`Before JEFFREY S. SMITH, SCOTT A. DANIELS, and
`GEORGIANNA W. BRADEN, Administrative Patent Judges.
`DANIELS, Administrative Patent Judge.
`
`DECISION
`Granting Institution of Inter Partes Review
`35 U.S.C. § 314, 37 C.F.R. § 42.4
`
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`
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`IPR2020-01559
`Patent 7,286,075 B2
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`INTRODUCTION
`I.
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. (collectively “Petitioner”
`or “Xilinx”) filed a Petition to institute an inter partes review of claims 1–25
`of U.S. Patent No. 7,286,075 B2 (“the ’075 patent”). Paper 2 (“Pet.”).
`Analog Devices, Inc. (“Patent Owner” or “Analog”) filed a Preliminary
`Response. Paper 6 (“Prelim. Resp.”).
`Under 35 U.S.C. § 314(a), an inter partes review may not be instituted
`“unless . . . there is a reasonable likelihood that the petitioner would prevail
`with respect to at least 1 of the claims challenged in the petition.” Upon
`consideration of the arguments and evidence presented by Petitioner and
`Patent Owner, we are persuaded that Petitioner has demonstrated, under
`35 U.S.C. § 314(a), a reasonable likelihood that it would prevail in showing
`the unpatentability of at least one of the challenged claims. Accordingly, we
`institute an inter partes review of the challenged claims.
`Real Parties in Interest
`A.
`Petitioner states that the real parties-in-interest are Xilinx, Inc. and
`Xilinx Asia Pacific Pte. Ltd. Pet. 1.
`Patent Owner states that Analog Devices, Inc. is the real party-in-
`interest in this proceeding. Paper 4, 2.
`Additional Proceedings
`B.
`The parties indicate that the ’075 patent has been asserted against
`Petitioner in Analog Devices, Inc. v. Xilinx, Inc. and Xilinx Asia Pacific Pte.
`Ltd., Case No. 1:19-cv-02225 in the United States District Court for the
`District of Delaware. Pet. 1; Paper 4, 2. Patent Owner also states that
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`“Petitioner[] filed petitions for Inter Partes Review of U.S. Patent
`No. 10,250,250 (Case No. IPR2020-01210), U.S. Patent No. 8,487,659
`(Case No. IPR2020-01219), U.S. Patent No. 7,012,463 (Case No. IPR2020-
`01336), U.S. Patent No. 7,719,452 (Case No. IPR2020-01561), and U.S.
`Patent No. 6,900,750 (Case Nos. IPR2020-01483, IPR2020-01484, and
`IPR2020-01564), which also are at issue in the above litigation.” Paper 4, 2.
`The ’075 Patent
`C.
`The ’075 patent describes problems and improvements related to
`analog to digital converters (“ADC”). Ex. 1001, 1:6–9. An analog to digital
`converter takes an analog signal as input and converts that analog signal into
`a corresponding digital output. See id. at 3:37–41. Figures 1 and 2,
`reproduced below, are graphs showing the correspondence between input
`analog signals (on the y-axis) with output digital signals (on the x-axis).
`See id. at 3:36–43, 3:53–55.
`
`As shown in Figure 1, above left, an input analog signal having a
`voltage level ranging between 0.5 and 1.5 units corresponds to bit-encoded
`digital output code XX001 (where XX are irrelevant bits). Id. at 3:37–41.
`Ideally, each range of analog input signals which each digital code spans is
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`equal, exhibiting “good linearity.” Id. at 1:13–14, 3:41–43. For example,
`each range should span 1.0 voltage units such that input voltages between
`0.5 and 1.5 units correspond to digital code XX001, input voltages between
`1.5 and 2.5 units correspond to digital code XX010, and so on. Id. at 3:36–
`43. As shown in Figures 1 and 2, however, a digital out code
`problematically spans a greater corresponding input voltage range than it
`should — an error known as differential non-linearity (DNL). Id. at 3:43–
`46; 3:57–67. DNL errors may also result in missing codes, as shown in
`Figures 1 and 2. Id. at 3:49–52; 3:57–67. The ’075 patent states that it was
`known in the prior art to address DNL errors and missing codes by “[a]dding
`a known dither to the operation of the analog to digital converter.” Id.
`at 4:1–7. The ’075 patent describes a particular technique of “adding dither
`to an input signal to be digitized” which uses a “switched capacitor
`architecture . . . to impose a perturbation or a dither onto the sampled
`signal.” Id. at 3:4–6, 4:23–26. Figure 3, reproduced below, illustrates an
`analog to digital converter having a particular switched capacitor
`architecture which adds dither to the conversion. Id. at 3:29–30, 4:44–45.
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`As shown in the analog to digital converter of Figure 3, an input
`voltage, signal AIN, is sampled onto the capacitors CB–CN of main P-DAC
`array 2 (interchangeably referred to as “main DAC array 2”). Id. at 5:62–65.
`That sampling is controlled by respective switches SB to SN, which
`selectively connect capacitors CB–CN to input signal AIN, first reference
`voltage Vrefp, or second reference voltage Vrefn. Id. at 5:57–6:2.
`Additionally, the analog to digital converter includes two other arrays
`of capacitors which are not used to sample input signal AIN: sub P-DAC
`array 10 having capacitors C1–CA (interchangeably referred to as “sub DAC
`array” or “sub array”) (Id. at 6:2–5) and an array of additional capacitors
`AC1–AC3 (Id. at 7:7–16). Using either, or both, of those other arrays, “a
`dither can be introduced into the analog to digital converter.” Id. at 7:46–51,
`8:16–19. In the case of sub DAC array 10, capacitors C1–CA are each
`respectively connected to switches S1–SA, which alternatively switch their
`corresponding capacitors between first reference voltage Vrefp and second
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`reference voltage Vrefn. Id. at 7:46–51. “[S]elective switching of capacitors
`within the sub capacitor array can be used to perturb the voltage that was
`sampled onto the main capacitor array during the sampling phase and hence
`introduce a positive or negative dither into the analog to digital converter.”
`Id. at 7:62–8:4. And, similarly to the sub DAC array, the array of additional
`capacitors AC1–AC3 provide a dither through respective switches SAC1–
`SAC3 selectively switching respective capacitors between first reference
`voltage Vrefp and second reference voltage Vrefn. Id. at 8:20–28.
`Furthermore, in both the sub P-DAC array 10 of capacitors C1–CA and
`the array of additional capacitors AC1–AC3, the capacitors’ respective
`switches “are driven in response to a pseudo random number generated by
`the pseudo random number generator 40.” Id. at 8:28–37. That is, “the
`pseudorandom generator 40 controls the switches SAC1, S1, S2, S3 and so
`on.” Id.; see id. 8:52–58.
`Illustrative Claims
`D.
`As noted previously, Petitioner challenges claims 1–25. Of the
`challenged claims, claims 1, 16, 20, 22, and 24 are independent. Each of
`dependent claims 2–15 depend from claim 1, claims 17–19 depend from
`claim 16, claim 21 depends from claim 20, claim 23 depends from claim 22,
`and claim 25 depends from claim 24. Claims 1 and 16 are reproduced below
`with certain limitations of interest highlighted:1
`1[pre]. An analog to digital converter for converting an analog
`input signal to a digital output signal, comprising
`1[a] a first group of capacitors for participation in a successive
`approximation conversion, each capacitor having at least one
`associated switch for controllably connecting a terminal of the
`
`1 We reference Petitioner’s bracketed labels and breaks in claims 1 and 16.
`See Pet. 29–30, 38–43.
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`capacitor to a first reference voltage or to a second reference
`voltage;
`1[b] a second group of capacitors for applying a dither and
`having switches for selectively connecting the capacitors to the
`first reference voltage or the second reference voltage and a
`sequence generator for generating a sequence of bits,
`1[c] wherein during sampling of the analog input signal onto
`at least some of the capacitors of the first group of capacitors or
`during conversion of a sample of the analog input signal an
`output of the sequence generator is supplied to the switches of
`the second group of capacitors to control whether a given
`capacitor within the second group is connected by its associated
`switch to the first reference voltage or to the second reference
`voltage, so as to apply a dither to said conversion.
`Ex. 1001, 9:42–61 (emphasis added).
`16[pre] An analog to digital converter, comprising
`16[a] a switched capacitor array for use in sampling an input
`signal and for converting a sample of said input signal to a digital
`value; and
`16[b] a switched capacitor digital to analog converter responsive
`to a control word,
`16[c] wherein after sampling an input signal onto the switched
`capacitor array to store charge in said array, the switched
`capacitor digital to analog converter is operated to make a known
`perturbation to the charge stored on the switched capacitor
`array.
`Id. at 10:49–59 (emphasis added).
`Prior Art and Asserted Challenges
`E.
`Petitioner contends that the challenged claims are unpatentable over
`the following specific challenges.2
`
`2 Petitioner supports its challenge with the opinion testimony of Dr. Douglas
`R. Holberg (Ex. 1003). Patent Owner’s arguments are supported by the
`testimony of Dr. Un-Ku Moon (Ex. 2001). See infra.
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`Claim(s) Challenged
`16, 17
`1–7, 9, 10, 12–25
`8
`11
`1–5, 7, 9–22
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`35 U.S.C. §
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`103(a)
`
`Reference(s)/Basis
`Confalonieri3
`Confalonieri, Hiller4
`Confalonieri, Hiller, Hester5
`Confalonieri, Hiller, Bjornsen6
`Cai,7 Bjornsen
`Cai, Bjornsen, Hester
`
`II. ANALYSIS
`A. Discretionary Denial under 35 U.S.C. § 325(d)
`Patent Owner makes several arguments asking that we exercise our
`discretion under 35 U.S.C. § 325(d) not to institute a trial because the prior
`art relied upon by Patent Owner, specifically Confalonieri, Cai, Hiller, and
`Bjornsen, are cumulative to the art cited and relied upon by the Examiner
`during prosecution of the application that became the ’075 patent. Prelim.
`Resp. 36–40, 53–57, and 64–67. For the reasons discussed below, we
`decline to exercise our discretion not to institute.
`35 U.S.C. § 325(d) states, in relevant part: “In determining whether to
`institute or order a proceeding under this chapter, chapter 30, or chapter 31,
`the Director may take into account whether, and reject the petition or request
`because, the same or substantially the same prior art or arguments previously
`were presented to the Office.” The Board uses a two-part framework for
`evaluating arguments under § 325(d):
`the same art
`(1) whether the same or substantially
`previously was presented to the Office or whether the same or
`
`
`3 Ex. 1012, US Patent No. 6,600,437 B1 (July 29, 2003).
`4 Ex. 1013, US Patent No. 4,550,309 (Oct. 29, 1985).
`5 Ex. 1014, US Patent No. 5,675,340 (Oct. 7, 1997).
`6 Ex. 1015, US Patent No. 7,129,874 B2 (Oct. 31, 2006).
`7 Ex. 1017, US Patent No. 6,914,550 B2 (July 5, 2005).
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`substantially the same arguments previously were presented to
`the Office; and
`(2) if either condition of first part of the framework is
`satisfied, whether the petitioner has demonstrated that the Office
`erred in a manner material to the patentability of challenged
`claims.
`Advanced Bionics, LLC v. MED-EL Elektromedizinische Geräte
`GmbH, IPR2019-01469, Paper 6 at 8 (PTAB Feb. 13, 2020) (precedential).
`“[T]he Becton, Dickinson factors provide useful insight into how to apply
`the framework under 35 U.S.C. § 325(d).” Id. at 9 (footnote omitted). The
`non-exclusive Becton, Dickinson factors are:
`(a) the similarities and material differences between the
`asserted art and the prior art involved during examination;
`(b) the cumulative nature of the asserted art and the prior
`art evaluated during examination;
`(c) the extent to which the asserted art was evaluated
`during examination, including whether the prior art was the basis
`for rejection;
`(d) the extent of the overlap between the arguments made
`during examination and the manner in which Petitioner relies on
`the prior art or Patent Owner distinguishes the prior art;
`(e) whether Petitioner has pointed out sufficiently how the
`Examiner erred in its evaluation of the asserted prior art; and
`(f) the extent to which additional evidence and facts
`presented in the Petition warrant reconsideration of the prior art
`or arguments.
`Becton, Dickinson & Co. v. B. Braun Melsungen AG, IPR2017-01586, Paper
`8 at 17–18 (PTAB Dec. 15, 2017) (precedential as to § III.C.5, first
`paragraph). Becton, Dickinson factors (a), (b), and (d) relate to the first part
`of the Advanced Bionics framework (whether the same or substantially the
`same art or arguments previously were presented to the Office), and Becton,
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`Dickinson factors (c), (e), and (f) relate to the second part of that framework
`(previous Office error). Advanced Bionics, IPR2019-01469, Paper 6 at 9–
`11.
`
`Primary References – Confalonieri and Cai
`1.
`Patent Owner argues that during prosecution “the Examiner was
`undoubtedly aware of the numerous statements in the ’075 specification to
`SARs with additional capacitors not used for sampling and converting the
`analog input signal.” Prelim. Resp. 36 (citing Ex. 1001, 6:57–60). The ’075
`patent specification states that “it is known to fabricate additional error
`correction capacitors within the arrays.” Id. It is not as clear as Patent
`Owner maintains, namely, that the known additional capacitors are “not used
`for sampling and converting.” Id.
`In any event, Confalonieri was not previously presented to the Office
`and is not listed as one of the “References Cited” on the face page of the
`’075 patent. Prelim. Resp. 36–40. Id., see also Ex. 1001, [56]. Patent Owner
`argues that “Confalonieri is cumulative of at least the admitted prior art in
`the specification, as well as art cited by the Examiner including Cai.” Id.
`at 53. We disagree. Our understanding is that Confalonieri teaches an ADC
`having a switched capacitor array CATT that is not part of the converter and
`not connected to the circuit input. Ex. 1012, 5:13–39, Figs. 5, 7. Comparing
`Confalonieri’s circuit for example to Wolff et. al., U.S. Patent No.
`7,015,853, applied by the Examiner during prosecution, we note applicant’s
`argument to the Examiner:
`Wolf[f] quite simply does not disclose a converter having a first
`group of capacitors for participation
`in a successive
`approximation conversion and a second group of capacitors
`(which does not participate in the conversion) for applying a
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`dither to the conversion. Accordingly, claims 1–12 are novel
`over Wolf[f].
`Ex. 1002, 69.
`In the challenges here, Confalonieri teaches a second switched
`capacitor array CATT that is not part of the converter and not connected to the
`circuit input. Ex. 1012, 5:13–39, Figs. 5, 7. We find this difference from
`the art cited in the underlying prosecution, .e.g., Wolff, and Cai, to be
`significant. In our view, although there are general structural similarities
`across the broad range of prior art ADC circuits, Confalonieri teaches a
`sufficiently unique circuit structure such that it is not substantially the same
`as the prior art cited during prosecution. Indeed, Patent Owner provides
`little substantive explanation or comparison with the cited prior art apart
`from alleging that Confalonieri discloses similar ADC architecture to Cai
`and that Cai is listed on the face page of the ’075 patent. Prelim. Resp. 38–
`39.
`
`On this record we find that Confalonieri is not substantially the same
`as Wolff, Cai and other art previously presented to the Office. Although Cai
`was cited by the Examiner, Cai is used in this proceeding as a primary
`reference for only two grounds and is cited in combination with the
`secondary references of Bjornsen and Hester which were not previously
`presented to the Office.
`Secondary References – Hiller and Bjornsen
`2.
`Hiller and Bjornsen are the secondary references relied on for certain
`of Petitioner’s challenges. Patent Owner argues “Confalonieri and Hiller,
`and the underlying arguments made in the Petition, are — at best —
`substantially the same as the prior art references presented to the Office.”
`Prelim. Resp. 53–57. Similarly, Patent Owner also argues that “Cai and
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`Bjornsen, and the underlying arguments made in the Petition, are—at best—
`substantially the same as the prior art references presented to the Office
`(which includes Cai).” Id. at 64–67.
`Neither secondary reference, Hiller nor Bjornsen, was cited during
`prosecution of the application that became the ’075 patent. Ex. 1001, [56].
`Patent Owner compares Hiller and Bjornsen to Giangano, which is listed on
`the face page of the ’075 patent. Patent Owner’s arguments as to similarity
`of Hiller and Bjornsen to Giangano compares, for example, Figures 1 of
`both Hiller and Giangano. Prelim. Resp. 53–57. This comparison relies on
`block diagrams described in each reference specifically as known prior art
`structures. Compare Ex. 1013, 1:6–10, with Ex. 1009, 2:40. A generalized
`comparison of basic universal circuit elements is not persuasive that the
`references are simply cumulative. Giangano discloses a bin averaging
`technique implemented on the circuit shown in Giangano’s Figure 2. It is
`not clear to us that Hiller’s ADC providing dither signals either in a first
`pass digitization (Figure 4) or in a second pass approximation of signals
`(Figure 5) are simply cumulative of Giangano’s bin-averaging function and
`structure. Overall, we find that Hiller and Bjornsen are not substantially the
`same as Giangano.
`Conclusion as to 35 U.S.C. § 325(d)
`3.
`Overall, reviewing Confalonieri, Cai, Hiller, Bjornsen, and the
`challenges based on these references, we do not find that the same or
`substantially the same art previously was presented to the Office or that any
`similar arguments were presented to the Office during prosecution.
`Accordingly, we need not and do not consider the second part of the
`Advanced Bionics framework, and we decline to exercise our discretion not
`to institute under Section 325(d).
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`Legal Standards of Obviousness
`B.
`Section 103(a) forbids issuance of a patent when “the differences
`between the subject matter sought to be patented and the prior art are such
`that the subject matter as a whole would have been obvious at the time the
`invention was made to a person having ordinary skill in the art to which said
`subject matter pertains.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406
`(2007).
`The question of obviousness is resolved on the basis of underlying
`factual determinations, including: (1) the scope and content of the prior art;
`(2) any differences between the claimed subject matter and the prior art;
`(3) the level of ordinary skill in the art; and (4) when available, evidence
`such as commercial success, long-felt but unsolved needs, and failure of
`others. Graham v. John Deere Co., 383 U.S. 1, 17–18 (1966); see KSR, 550
`U.S. at 407 (“While the sequence of these questions might be reordered in
`any particular case, the [Graham] factors continue to define the inquiry that
`controls.”). The Court in Graham explained that these factual inquiries
`promote “uniformity and definiteness,” for “[w]hat is obvious is not a
`question upon which there is likely to be uniformity of thought in every
`given factual context.” Graham, 383 U.S. at 18.
`The Supreme Court made clear that we apply “an expansive and
`flexible approach” to the question of obviousness. KSR, 550 U.S. at 415.
`Whether a patent claiming the combination of prior art elements would have
`been obvious is determined by whether the improvement is more than the
`predictable use of prior art elements according to their established functions.
`Id. at 417. To reach this conclusion, however, it is not enough to show
`merely that the prior art includes separate references covering each separate
`limitation in a challenged claim. Unigene Labs., Inc. v. Apotex, Inc., 655
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`F.3d 1352, 1360 (Fed. Cir. 2011). Rather, obviousness additionally requires
`that a person of ordinary skill at the time of the invention “would have
`selected and combined those prior art elements in the normal course of
`research and development to yield the claimed invention.” Id.
`A claimed invention may be obvious even when the prior art does not
`teach each claim limitation, so long as the record contains some reason why
`one of skill in the art would modify the prior art to obtain the claimed
`invention. See Ormco Corp. v. Align Tech., Inc., 463 F.3d 1299, 1307
`(Fed. Cir. 2006). And, as a factfinder, we also must be aware “of the
`distortion caused by hindsight bias and must be cautious of arguments reliant
`upon ex post reasoning.” KSR, 550 U.S. at 421. This does not deny us,
`however, “recourse to common sense” or to that which the prior art teaches.
`Id.
`
`Level of Ordinary Skill in the Art
`C.
`Factors pertinent to a determination of the level of ordinary skill in the
`art include: (1) educational level of the inventor; (2) type of problems
`encountered in the art: (3) prior art solutions to those problems; (4) rapidity
`with which innovations are made; (5) sophistication of the technology, and
`(6) educational level of workers active in the field. Envtl. Designs, Ltd. v.
`Union Oil Co., 713 F.2d 693, 696–697 (Fed. Cir. 1983) (citing Orthopedic
`Equip. Co. v. All Orthopedic Appliances, Inc., 707 F.2d 1376, 1381–82
`(Fed. Cir. 1983)). Not all such factors may be present in every case, and one
`or more of these or other factors may predominate in a particular case.
`Id. Moreover, these factors are not exhaustive but are merely a guide to
`determining the level of ordinary skill in the art. Daiichi Sankyo Co. Ltd,
`Inc. v. Apotex, Inc., 501 F.3d 1254, 1256 (Fed. Cir. 2007).
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`In determining a level of ordinary skill, we also may look to the prior
`art, which may reflect an appropriate skill level. Okajima v. Bourdeau, 261
`F.3d 1350, 1355 (Fed. Cir. 2001). Additionally, the Supreme Court informs
`us that “[a] person of ordinary skill is also a person of ordinary creativity,
`not an automaton.” KSR, 550 U.S. at 421.
`Petitioner, supported by the testimony of Dr. Holberg, argues that a
`person of ordinary skill in the art (“POSITA”) “would at least a Master’s
`degree in Electrical Engineering or equivalent field, including studies in the
`area of analog circuitry; or at least a Bachelor’s degree in Electrical
`Engineering and at least two years of experience working on analog circuitry
`design.” Pet. 23 (citing Ex. 1009 ¶¶ 54–56). Neither Patent Owner nor
`Dr. Moon dispute or offer an alternative level or skill in the art at this time.
`See gen., Prelim. Resp., see also Ex. 2001 ¶ 13 (Dr. Moon stating that
`Petitioner’s asserted level of ordinary skill in the art is “reasonable”).
`On this record, the parties appear to agree upon the proposed level of
`ordinary skill in the art is consistent with our review and understanding of
`the technology and descriptions in the ’075 patent and the prior art
`references that disclose electronic circuits including analog-to-digital
`converters using modulation feedback signals and charge injection in MOS
`transistor circuits to account for differential non-linearity. For purposes of
`this Decision, we rely on Petitioner’s proposed level of ordinary skill in the
`art.
`
`D. Claim Construction
`We interpret a claim “using the same claim construction standard that
`would be used to construe the claim in a civil action under 35 U.S.C.
`282(b).” 37 C.F.R. § 42.100(b). Under this standard, we construe the claim
`“in accordance with the ordinary and customary meaning of such claim as
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`understood by one of ordinary skill in the art and the prosecution history
`pertaining to the patent.” Id. Furthermore, at this stage in the proceeding,
`we expressly construe the claims only to the extent necessary to determine
`whether to institute inter partes review. See Nidec Motor Corp. v.
`Zhongshan Broad Ocean Motor Co. Ltd., 868 F.3d 1013, 1017 (Fed. Cir.
`2017) (“[W]e need only construe terms ‘that are in controversy, and only to
`the extent necessary to resolve the controversy.’” (quoting Vivid Techs., Inc.
`v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))).
`“perturbation”
`In the claim construction section of the Petition, Petitioner states that
`it “does not believe any claim construction is necessary here.” Pet. 23–24.
`Meanwhile, in its challenge to claim 16 over Confalonieri, Petitioner asserts
`that the “ordinary meaning of ‘perturbation’ is simply a small change in the
`quality or behavior of something,” yet Petitioner does not refer to, or cite, to
`any specific source for this definition. Id. at 28. Petitioner’s Declarant,
`Dr. Holberg, testifies similarly that “the ordinary meaning of ‘perturbation’
`is simply a small change in movement, quality, or behavior of something,
`especially an unusual change.” Ex. 1003 ¶ 81. Given these definitions,
`Petitioner argues that Confalonieri’s “offset compensation” applied by
`switched capacitor array CATT “is a known perturbation.” Pet. 30, see also
`Ex. 1003 ¶ 82 (Dr. Holberg testifying that a person of ordinary skill in the
`art would have understood that “compensating the offset corresponds to the
`switched capacitor digital to analog converter being operated to make a
`known perturbation”).
`Patent Owner disagrees, asserting that the meaning of “perturbation”
`does not include an “offset compensation” as disclosed by Confalonieri. See
`Prelim. Resp. 27 (“Confalonieri’s offset compensation is not a
`
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`Patent 7,286,075 B2
`perturbation.”). Patent Owner’s declarant, Dr. Moon, testifies that
`“[a]lthough I have heard ‘dither’ and ‘noise’ each referred to as a
`perturbation, I have never heard anyone call ‘offset compensation’ a
`perturbation.” Ex. 2001 ¶ 47. Dr. Moon does not identify which facts, if
`any, support this definition, outside of Dr. Moon’s memory. See Phillips v.
`AWH Corp., 415 F.3d 1303, 1318 (Fed. Cir. 2005) (en banc) (“conclusory,
`unsupported assertions by experts as to the definitions of a claim term are
`not useful to a court”).
`On the record before us, it is not clear based on either the intrinsic
`evidence in the ’075 patent or the extrinsic evidence advanced by the
`Declarants, whether the meaning of “perturbation” does, or does not,
`encompass “offset compensation.” At the moment, we need not determine
`what testimony is the most credible or construe this term for purposes of
`institution because we base our Decision on the challenges and combination
`of Cai and Bjornsen as discussed below. With respect to the grounds
`including Confalonieri, the parties may wish to develop their arguments and
`further evidence during trial as to the meaning of “perturbation.” For
`example, Patent Owner and Petitioner will have the opportunity to cross-
`examine Dr. Holberg and Dr. Moon, respectively, about the definition of
`“perturbation” during the course of the trial.
`Claims 1–5, 7, and 9–22 — Alleged Obviousness over Cai and
`E.
`Bjornsen
`Petitioner argues that claims 1–7, 9, 10, 12–25 of the ’075 patent are
`obvious over Cai and Bjornsen. As discussed below, and having reviewed
`the information and evidence provided by Petitioner and Patent Owner,
`including the relevant portions of the testimony of Dr. Holberg (Ex. 1003)
`and Dr. Moon (Ex. 2001), we are persuaded, on the current record, that
`
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`IPR2020-01559
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`Petitioner has demonstrated a reasonable likelihood of prevailing on this
`obviousness challenge.
`Cai
`1.
`Cai describes “analog to digital conversion systems (A/D converters
`or ADCs) in which two or more multi-bit successive approximation register
`(SAR) subconverter stages are cascaded” for “receiving an analog input and
`providing a digital output.” Ex. 1015, 2:54–59. The “cascaded SAR stages
`include capacitor arrays and switching systems to selectively couple the
`capacitors to array inputs, array outputs, or reference voltages for operation
`in sample, conversion, and residue amplification modes.” Id. at 2:59–62.
`Cai’s Figure 2A, reproduced below, is a schematic diagram illustrating a
`pipelined fully differential A/D converter with SAR subconverter stages.
`Id. at 4:13–16.
`
`
`
`As shown in Figure 2A, a plurality of cascaded subconverter
`stages 112, e.g., first subconverter stage 112a and second subconverter
`stage 112b, receive analog input 132. Id. at 5:10–13. Each SAR stage 112
`receives “an analog subconverter stage input signal (e.g., a voltage) 132,144
`and provides [a respective] M-bit digital output 120.” Id. at 5:18–21.
`Digital correction unit 118 receives the respective M-bit “digital
`output[s] 120 from each of the [subconverter] stages 112 to provide an error
`
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`IPR2020-01559
`Patent 7,286,075 B2
`corrected N-bit binary digital output 122 corresponding to the analog input
`signal voltage 132.” Id. at 5:14–18, 5:33–36. Figure 2C, reproduced below,
`is a schematic diagram detailing an exemplary SAR subconverter stage.
`Id. at 4:20–22.
`
`
`
`As shown in Figure 2C, subconverter stage 112 includes a switched
`capacitor system 160 that has a plurality or array of capacitors 162, a
`switching system 164, and a mode control system 166. Id. at 6:21–35;
`see id. at Fig. 2D. For example, “switching system 164 selectively couples
`individual capacitors in the array 162 to the switched capacitor system input
`node (VINP or VINM), the switched capacitor system output node (VOUTP
`or VOUTM), a first reference voltage (VREFP), or a second reference
`voltage (VREFM).” Id. at 7:44–49; see id. at Fig. 2D.
`Furthermore, subconverter stage 112 has three modes — sample,
`conversion, and residue amplification —which sequentially operate to
`perform various analog to digital conversion steps. Id. at 6:42–47; see id.
`
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`IPR2020-01559
`Patent 7,286,075 B2
`at 5:54–6:20. In sampling mode, input voltage 132, 144, is received to be
`“iteratively quantized in the conversion mode.” Id. at 5:59–62. During
`conversion mode, digital error correction system 118 “corrects for the effects
`of parasitic capacitances Cp and the offset voltage Vos since the offset
`voltage and parasitic capacitance effects operate to shift [a] transfer function
`by a constant amount.” Id. at 5:56–59, 9:38–32; see Fig. 2F. Ultimately, in
`residue amplification mode, subconverter stage 112 generates “a final digital
`output 120 (e.g., also M-bit binary) to the subconverter stage digital output
`correction unit 118 (FIG. 2A).” Id. at 7:20–24. Then, as noted above,
`“digital correction unit 118 receives the subconverter stage digital
`outputs 120 from each subconverter stage 112 and generates a digital output
`of N bits,” i.e., the resultant digital conversion of the original analog signal.
`Id. at 5:14–18, 5:33–36; see id. 1:61–66.
`Bjornsen
`2.
`Bjornsen describes an analog to digital converter system that converts
`an analog input signal into a digital output signal and includes a noise
`shaping first stage cascaded with a pipelined second stage.” Ex. 1015, 2:53–
`56. Bjornsen includes a “digital dither generator . . . to provide a dither
`signal to the ADC circuit.” Id. at 2:59–60. Figure 1 is a block diagram of an
`ADC circuit, and is reproduced below. Id. at 2:17–18.
`
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`
`
`
`As shown in Figure 1, ADC circuit 10 “converts an analog input
`signal g(t) into a digital output signal dg(k/N)” in two stages. Id. at 4:44–55.
`The first stage is a noise shaping stage 12. Id. at 4:47. In that stage, digital
`dither generator 18 generates dither signal dt(k). Id. at 4:50–51. Analog
`input signal v(k) is converted into a digital signal d1(k) by ADC1 22; dither
`signal dt(k) is su
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