`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`_____________________________________
`
`Case No. IPR2020-01559
`Patent No. 7,286,075
`____________________________________
`PATENT OWNER’S RESPONSE PURSUANT TO
`37 C.F.R. § 42.120
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`TABLE OF CONTENTS
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`IPR2020-01559
`Patent Owner’s Response
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`I.
`II.
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`4.
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`5.
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`Page
`INTRODUCTION ........................................................................................... 1
`TECHNICAL BACKGROUND ..................................................................... 3
`A.
`SAR ADCs ............................................................................................ 3
`B.
`Differential Non-Linearity (DNL) ........................................................ 7
`C. Dither ..................................................................................................... 9
`III. THE CLAIMED INVENTION ..................................................................... 14
`IV. PROSECUTION HISTORY ......................................................................... 18
`V.
`CLAIM CONSTRUCTION .......................................................................... 19
`A.
`Perturbation ......................................................................................... 19
`VI. THE PETITION’S CAI BASED GROUNDS SHOULD BE REJECTED .. 24
`A.
`Petitioner Has Not Demonstrated that Claims 1-5, 7, 9-22 Would
`Have Been Obvious in view of Cai and Bjornsen (Ground 5) ........... 24
`1.
`Cai’s Disclosures....................................................................... 24
`2.
`Bjornsen’s Disclosures .............................................................. 26
`3.
`Petitioner Has Not Established a Motivation To Combine Cai
`and Bjornsen ............................................................................. 29
`Even in Combination, Cai and Bjornsen Lack The Inventive
`Dither Techniques Recited in the Claims ................................. 33
`Cai and Bjornsen Do Not Disclose or Suggest Applying Dither
`“During Sampling,” Or “During Conversion”/“After
`Sampling,” As Independent Claims 1, 16, 20, And 22 Require
` ................................................................................................... 37
`The Combination of Cai With Bjornsen Does Not Render the
`Dependent Claims Obvious ...................................................... 42
`Petitioner Has Not Demonstrated that Claim 8 Is Obvious in view of
`Cai, Bjornsen, and Hester (Ground 6) ................................................. 43
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`6.
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`B.
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`B.
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`3.
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`3.
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`IPR2020-01559
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`Patent Owner’s Response
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`VII. THE PETITION’S CONFALONIERI BASED GROUNDS SHOULD BE
`REJECTED .................................................................................................... 43
`A.
`Petitioner Has Not Demonstrated Claims 16 and 17 Would Have Been
`Obvious Over Confalonieri (Ground 1) .............................................. 43
`1.
`Confalonieri’s Disclosures ........................................................ 43
`2.
`Confalonieri Does Not Teach or Suggest Making a
`“Perturbation” ........................................................................... 45
`Confalonieri Does Not Teach or Suggest Perturbation “After
`Sampling” by Perturbing “The Charge Stored on the Switched
`Capacitor Array” ....................................................................... 48
`Petitioner Has Not Demonstrated Claims 1-7, 9, 10 and 12-25 Would
`Have Been Obvious in view of Confalonieri and Hiller (Ground 2) .. 54
`1.
`Hiller’s Disclosures ................................................................... 55
`2.
`Confalonieri Does Not Disclose Applying Dither At All, And
`Hiller Only Discloses Applying Conventional Dither. Ground 2
`Thus Lacks The Inventive Dither Techniques Recited in the
`Claims. ...................................................................................... 57
`Confalonieri and Hiller Also Do Not Disclose Applying Dither
`“During Sampling,” Or “During Conversion”/“After Sampling”
` ................................................................................................... 59
`Petitioner Has Not Established A Motivation To Combine
`Confalonieri and Hiller ............................................................. 61
`The Combination of Confalonieri With Hiller Does Not Render
`the Dependent Claims Obvious ................................................ 70
`Petitioner Has Not Demonstrated that Claims 8 Is Obvious in view of
`Confalonieri, Hiller, and Hester (Ground 3) or that Claim 11 Is
`Obvious in view of Confalonieri, Hiller, Hester, and Bjornsen
`(Ground 4) ........................................................................................... 70
`VIII. CONCLUSION .............................................................................................. 70
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`C.
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`4.
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`5.
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`IPR2020-01559
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`Patent Owner’s Response
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`Patent Owner Analog Devices, Inc. (“Analog”) submits the following Patent
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`Owner Response (“POR”) to the petition filed by Xilinx, Inc. and Xilinx Asia Pacific
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`Pte. Ltd. (“Petitioner”) requesting inter partes review of claims 1–25 of U.S. Patent
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`No. 7,286,075 (Ex. 1001 (the “ʼ075 patent”)).
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`I.
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`INTRODUCTION
`The ’075 patent discloses novel, non-obvious dither techniques for reducing
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`differential nonlinearity (“DNL”) in a successive approximation register analog to
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`digital converter (“SAR ADC”).
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`As the ’075 patent recognizes, it was known at the time of the invention that
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`adding dither (noise) to an analog input signal could reduce DNL in an ADC. Dither
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`does not address the root causes of DNL or otherwise correct the conversion process,
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`but it randomizes the effects of the errors causing the nonlinearities, thereby
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`averaging them out. Then-existing dither techniques, however, required a
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`concomitant reduction in the input signal’s amplitude range, because the combined
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`signal had to fit in the converter’s range. This reduction in the input signal reduced
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`the signal to noise ratio (“SNR”) and limited the ADC’s resolution (i.e., the number
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`of bits of precision used to quantize an analog signal). As Petitioner’s expert
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`concedes, this consequence was a well-recognized downside to dither.. E.g.,
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`IPR2020-01561, Xilinx Exhibit 1002, ¶69 (“A downside to adding dither larger than
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`an LSB is that it results in reducing the usable signal range of the converter.”).
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`Given these disadvantages of, persons of skill in the art (“POSITA”)implementing
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`SAR ADCs at the time of the invention focused on other techniques that addressed
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`the root causes of DNL.
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`The ’075 inventors discovered a new way to apply dither to a SAR ADC that
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`avoided the recognized disadvantages of prior techniques. In particular, rather than
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`randomize the input signal before it is provided to an ADC, as was done in the prior
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`art including the Petition’s art, the ’075 invention instead randomized the converter
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`itself after the input signal was sampled on the SAR ADC’s capacitor array. The
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`’075 technique thus allows the full signal range to be utilized, maintaining maximum
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`resolution for the converter.
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`As the specification explains and the claims reflect, the inventors
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`accomplished this novel application of dither by randomly connecting dither
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`capacitors to a reference voltage to cause a redistribution or perturbation of already
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`stored charge (i.e., after the input signal has already been sampled onto the SAR
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`converter’s capacitor array), thereby altering conventional SAR comparison
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`equations to introduce a randomization factor to the reference scale. Moreover, by
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`omitting the component that would otherwise be required to add dither before the
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`conversion, the technique avoids new sources of uncontrolled noise or complexity.
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`None of the Petition’s art teaches or suggests the ’075 invention. Indeed,
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`Petitioner’s primary references, Confalonieri and Cai, say nothing about dither at all.
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`Instead, both are concerned with other issues such as reductions in offset error. The
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`Petition attempts to stretch the claims to cover these very different technologies, or
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`alternatively, to combine them with other prior art, Hiller and Bjornsen, teaching
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`conventional dither techniques. None of the prior art, alone or in combination,
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`teaches the critical elements of the claims including the patent’s inventive dither
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`technique, which randomizes the converter itself after the input signal is sampled
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`onto the SAR’s capacitor array. Moreover, Petitioner’s arguments for combining
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`this art is inconsistent both with the trial record and with the admissions of its own
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`expert.
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`II. TECHNICAL BACKGROUND
`A.
`SAR ADCs
`SARs are one of several known ADC architectures, each with different
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`tradeoffs in factors such as speed and accuracy. Other examples of ADCs include
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`flash, pipelined, and delta-sigma ADCs. Ex. 2017, ¶24.
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`In a SAR ADC, the ADC samples the input signal onto a set of capacitors and
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`then successively compares the input signal values to a series of predefined reference
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`values to create the digital representation of the input signal. Each comparison,
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`known as a “bit trial,” is analogous to measuring the weight of some unknown entity
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`using a balancing scale and a series of known, binary-valued weights. Weights are
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`successively added (and sometimes removed) in a series of closer approximations
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`until the combination of known weights approximately balances the unknown entity
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`(e.g., the combination of the 16, 4, and 1 ounce weights might approximate the
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`weight of a 21 ounce entity). Ex. 2017, ¶25.
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`In a SAR ADC, the unknown quantity is an analog input voltage Vin. The
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`known values or “weights” used to measure this unknown quantity are the capacitors
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`switched into the conversion operation during bit trials. A simplified description of
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`a typical SAR ADC is as follows. Conversion begins by sampling the analog input
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`voltage Vin onto a capacitor array. Sampling is performed, as shown below, by
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`connecting upper terminals to the input node via switch SB, and connecting the
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`common terminal to ground via switch SA. Ex. 1005, 10 (describing sample
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`mode). Ex. 2017, ¶26.
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`Next, the sampled input voltage Vin is held on the capacitor array by opening
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`switch SA to disconnect the common terminal from ground and switching the
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`upper terminals of the capacitors from the input terminal to ground. This operation
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`traps on the capacitor array an amount of charge proportional to input voltage Vin.
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`Ex. 1005, 10-11 (describing hold mode). Ex. 2017, ¶27.
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`Next, the SAR ADC measures the digital representation corresponding to the
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`held input voltage Vin by performing successive bit trials that determine, for each bit
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`trial, whether the held input voltage Vin is greater or less than the voltage
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`corresponding to the next-highest weighted capacitor in the array. During the first
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`bit trial, for example, the comparison operation may be expressed mathematically as
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`½Vref-Vin > 0, where the factor of ½ corresponds to the weight of the most significant
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`bit (MSB), i.e., the highest-weighted capacitor which is ½ the total capacitance of
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`the capacitor array. Physically, the comparison operation is the result of
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`redistributing the fixed charge held on the capacitor array by changing the position
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`of switch S4 (i.e., the switch coupled to the highest-weighted capacitor). Subsequent
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`bit trials test successively smaller voltages corresponding to lower-weighted
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`capacitors. Thus, the bit trial process adds to (or removes from) the voltage at the
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`common terminal in a series of closer approximations until the lowest-weighted
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`capacitor is reached. A SAR controller (not shown) receives the results for the bit
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`trials and creates a digital representation of the signal Vin. Ex. 1005, 11 (describing
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`redistribution mode); Ex. 2017, ¶28.
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`The resolution of the SAR, or any ADC, is the number of bits used to express
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`the digital value. This can be analogized to the number of decimal places of
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`precision used in expressing a number, e.g., 3.14159. Resolution is a key parameter
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`for an ADC and is dictated by aspects such as the signal to noise ratio (SNR). In
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`short, as the conversion attempts to convert to finer resolution, there is a point where
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`noise overwhelms the remaining signal to be converted and attempting to convert
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`beyond that point would convert noise, not signal, and result in gibberish. Ex. 2017,
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`¶29.
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`B.
` Differential Non-Linearity (DNL)
`DNL is a key parameter of SAR converters. As the patent explains, the term
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`“bin” is used to correspond to the range of an analog signal that will result in a
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`corresponding digital code (value). Ex. 1001, 1:25-28. In a perfectly linear system,
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`every bin is exactly the same size—1 least significant bit (LSB). Id., 3:55-57. DNL
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`represents the deviation in bin size. Id., 1:20-35; Ex. 1003, ¶27; Ex. 2017, ¶30.
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`For example, Figure 1, annotated below, shows an analog signal on the
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`horizontal axis, and the digital signal on the vertical axis. The size of an LSB is one
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`unit. Any analog signal in the green “bin” between 0.5 and 1.5 units should result
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`in the digital code XX001 (binary for 1). Ex. 2017, ¶31.
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`Ideally, the size of each bin (e.g., an analog range of 1, spanning from 0.5 to
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`1.5) is the same for each digital code (e.g., XX001), in the same way that each 1-
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`ounce reference weight used on a scale is expected to be precisely 1 ounce. As the
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`patent explains, however, bin sizes can deviate from this ideal due to physical
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`realities of circuit components, such as imprecision in capacitors. In some cases,
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`these deviations result in certain digital codes being “missing” from the output. For
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`example, in Figure 1, the bin sizes for XX011 and XX101 are so erroneously large
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`that the value XX100 (intended to capture analog signals from 3.5 to 4.5) has no bin.
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`The analog values in that range will thus always be wrongly digitized as a 3 or a 5,
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`instead of a 4. Ex. 1001, 3:36-52. Ex. 2017, ¶32.
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`C. Dither
`As the patent recognizes, prior to the invention, dither was a known technique
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`for decreasing DNL and reducing the effects of missing codes. Ex. 1001, 4:7-22.
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`These conventional dither techniques added a small pseudorandom amount to the
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`input signal. The combined signal was then sampled and quantized, and the dither
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`amount then removed from the digital result representing the combination of the
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`input signal and dither. This process improved linearity by spreading out the errors
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`associated with quantizing a given analog input value. Ex. 2017, ¶33.
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`The patent describes an example of these prior techniques, U.S. Patent No.
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`5,010,339 (Ex. 1009 (“Giangano”)). Ex. 1001, 1:41-55, 4:7-22. As disclosed in
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`Giangano, by adding dither to an input signal, “repeated input voltage signals of the
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`same value [are] converted in different bins” of the ADC, because the combined
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`signal is randomly varied around the input value to be converted. The resulting
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`effect is depicted below. Ex. 2017, ¶34.
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` For example (and for illustration purposes only), if the randomly selected
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`dither is +1 or -1:
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`• Without dither, an analog input of 4 is (incorrectly) in the bin for XX011
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`(binary for 3).
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`• If the dither value is randomly chosen to be -1, adding it to the analog input
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`of 4 would keep the input in the bin for XX011. But subtracting -1 from
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`that digitized output (3 – (-1)) would result in a digital value of 4.
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`• Likewise, if the randomly chosen dither value was +1, adding it to the
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`analog input of 4 would move the input to the bin for XX101 (5).
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`Subtracting +1 from that digitized output (5 – (+1)) would result in a digital
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`value of 4. Thus, the correct result can occur even with a missing code in
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`these last two cases.
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`• If the analog input was 2.7 without dither this signal would correctly be in
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`bin XX011; however, with dither value of +1 it would still be in bin XX011
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`and after subtracting the dither value would yield (incorrectly) binary value
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`of 2. (In this case, dither created an incorrect value; where a correct value
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`would result without dither.)
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`As this example corroborates, dither does not always correct the underlying errors
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`of the converter, nor produce the correct digital value for all analog inputs, but it
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`spreads out errors through randomizing the quantization in a beneficial way.
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`POSITAs often referred to dither as pushing noise spurs into the noise floor,
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`increasing the noise floor but minimizing particularly acute errors. Ex. 2017, ¶35.
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`Giangano’s Figure 1 exemplifies the prior art “in which a standard analog to
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`digital converter is associated within an additional external circuit which includes a
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`summer preceding the analog to digital converter.” Ex. 1001, 1:41-45. Number
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`gen(erator) 1 generates pseudorandom digital values that are converted to analog
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`dither values in DAC 3. The analog dither and analog input are summed to provide
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`a combined signal; the combined signal is then sampled onto capacitors in the
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`ADC 8 and converted to a digital value 9. Ex. 1009, 3:2-12. The digital dither 10
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`is then subtracted 11 from the combined signal to yield the final value 12. Id., 3:12-
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`22. Ex. 2017, ¶36.
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`IPR2020-01559
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`Patent Owner’s Response
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`At the time of the ’075 invention, although dither was known as a potential
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`technique for improving DNL in SAR ADCs, dither also had a number of well-
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`recognized disadvantages. Significantly, then-conventional techniques demanded a
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`reduction in the input signal’s full range of amplitude so that the combination of the
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`analog input signal and the analog dither signal could fit within the ADC’s input
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`range. This reduction in signal range reduced the signal to noise ratio, ultimately
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`resulting in reduced resolution of the ADC. Petitioner’s expert concedes this
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`downside to dither was known. IPR2020-01561, Xilinx Exhibit 1002 ¶69 (“A
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`downside to adding dither larger than an LSB is that it results in reducing the usable
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`signal range of the converter.”). In addition, the components used to add dither
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`(known noise) introduced unknown noise to the signal, detrimentally impacting
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`accuracy. Ex. 1001, 4:1-22; 1:52-55. Ex. 2017, ¶37.
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`Consequently, at the time of the patent, POSITAs designing SAR ADCs
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`typically focused on improving DNL by addressing root causes of the problem. For
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`example, designers would focus on calibration, capacitor layout, using unit size
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`capacitors for better capacitor matching, and other related measures to ensure more
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`accurate bin sizes for the ADC. Ex. 2018, 19:15-20:13 (“Q: …how would a person
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`of ordinary skill in the art, fix [DNL issues in a SAR ADC], at the time of the ’075
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`patent? … [in] the Leung paper that I'm co-author, … our goal was to achieve what
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`you call true 16 bit performance…we chose to calibrate the capacitors…”). Dr.
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`Holberg’s textbook includes a detailed discussion of DNL including capacitor
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`matching techniques, yet never mentions dither as a solution for DNL. Ex. 2014,
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`618-620, 656-657; Ex. 2001, ¶¶20-23; Ex. 2017, ¶38.
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`III. THE CLAIMED INVENTION
`The ’075 inventors discovered a new way to apply dither to a SAR ADC that
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`avoids these well-recognized disadvantages. In particular, rather than randomize
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`the input signal before it is provided to an ADC, as was done in the prior art and
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`the Petition’s art, the ’075 invention randomized the converter itself after the input
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`signal was sampled on the SAR ADC’s capacitor array. Ex. 2017, ¶39.
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`Figure 3 of the patent, below, illustrates this inventive technique:
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`IPR2020-01559
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`Like a conventional SAR, the ’075 SAR first samples a fixed amount of
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`charge onto the capacitors of the Main P-DAC (i.e., the main array). The input
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`signal AIN is then disconnected from those capacitors, trapping and holding an
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`amount of charge proportional to the input voltage. Bit trials are then performed
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`from the “most significant bit” (MSB) to the “least significant bit” (LSB), similar to
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`the comparison operations in the conventional SAR described in Section II.A. Ex.
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`2017, ¶¶40-41.
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`Unlike a conventional SAR, however, the ’075 invention applies the dither
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`to the converter itself. E.g., 1:6-10 (“The present invention relates to an
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`apparatus for and a method of applying dither to an analog to digital converter,
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`and to an analog to digital converter including such an apparatus.”); 7:46-51 (“The
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`inventors have realised that a dither can be introduced into the analog to digital
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`converter by modifying the switch positions during sampling ….”); Ex. 2017,
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`¶42.
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`In the ‘075 embodiments, a random number of AC capacitors and/or Sub-
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`DAC capacitors are switched during or after sampling, which in turn randomly
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`shifts the reference voltage that is compared to the held input voltage during each
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`bit trial. Ex. 1001, 8:16-34, 8:65-9:3. As the specification explains and Dr. Moon
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`confirms, this action applies dither to the converter itself by randomizing the
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`number of capacitors connected to the reference voltage during the initial
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`sampling state, or alternatively by randomizing the scale (i.e., the redistributed
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`charge) used to quantize the put signal AIN. Ex. 2017, ¶42.
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` For example, whereas the comparison operation during the first bit trial
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`would normally be ½Vref-AIN > 0, with the connection of a random number of AC
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`capacitors and/or Sub-DAC capacitors, the comparison equation becomes
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`(cid:4674)(cid:2869)(cid:2870)+∆(cid:3045)(cid:3028)(cid:3041)(cid:3031)(cid:3042)(cid:3040)(cid:4675)Vref -AIN > 0. As noted in the patent, the value of ∆(cid:3045)(cid:3028)(cid:3041)(cid:3031)(cid:3042)(cid:3040) depends
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`on the size and number of capacitors that are randomly selected for a given
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`conversion, thereby injecting a random perturbation into the conversion. The
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`invention thus applies dither by adding randomization to the converter (and
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`conversion process) itself, specifically the capacitance values used during bit trials,
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`in contrast to prior techniques which added randomization directly to the input signal
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`before sampling. Ex. 1009, 3:2-12; Ex. 1013, 1:6-16; Ex. 2017, ¶43.
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`The inventors’ approach of applying dither to the converter itself, during or
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`after sampling the analog input, has significant advantages. First, it allows the full
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`signal range to be sampled and converted, avoiding conventional dither’s downside
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`of reducing signal range and resolution. Ex. 1001, 7:46-8:4 (“[S]elective switching
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`of capacitors within the sub capacitor array can be used to perturb the voltage that
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`was sampled onto the main capacitor array during the sampling phase and hence
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`introduce a positive or negative dither into the analog to digital converter ….”).
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`Second, it avoids new sources of noise and errors, and reduces power consumption,
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`circuit size and expense. Id., 4:13-22 (explaining that invention eliminates circuit
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`components that “may be a source of noise, offset and gain error and may therefore
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`degrade other aspects of performance of the analog to digital converter” and are
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`“an expensive method of implementing dither functionality in terms of silicon area
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`used and power consumption of the ADC”). Third, the invention enables the same
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`capacitors to be used for dither as for other functions, and also allows dither to be
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`positive or negative. Id., 7:46-8:4 (confirming invention introduces dither by
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`“altering the switches S1 to SA of any of the capacitors C1 to CA of the sub
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`array”); Ex. 2017, ¶44.
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`IV. PROSECUTION HISTORY
`The patent issued following a thorough examination. The Examiner initially
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`IPR2020-01559
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`rejected the claims based on U.S. Patent No. 7,015,853 (Ex. 1010 (“Wolff”)), alone
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`or in view of U.S. Patent No. 6,850,181 (Ex. 1011 (“Tsinker”)). Ex. 1002, p. 47-52.
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`The inventors amended the claims and argued that Wolff “does not show a
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`switched capacitor array for use in sampling an input and converting an input to a
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`digital value along with a switched capacitor DAC for perturbing the first array that
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`was used in converting the input to a digital value.” Ex.1002, 69.
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`The Examiner allowed the claims, recognizing perturbation “to the charge
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`stored on the switched capacitor array” as a key element. As explained in the
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`Reasons for Allowance, the prior art did not “teach an analog to digital converter
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`that comprises, inter alia, a capacitor array for sampling an analog input signal to be
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`converted to digital, a switched capacitor DAC for receiving a dither signal to be
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`applied to the conversion process; a control word to be applied to the switches of
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`the DAC to make a known perturbation to the charge stored on the switched
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`capacitor array.” Ex. 1002, p. 98.1
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`1 The Petition contains a disclaimer argument. Pet. 20-23. As explained in the
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`POPR, that argument is incorrect. The Board need not address this dispute because
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`none of the Grounds rely on it.
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`V. CLAIM CONSTRUCTION
`A.
`Perturbation
`In its DI, the Board invited the parties to address the construction of
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`IPR2020-01559
`Patent Owner’s Response
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`“perturbation,” used in a few of the challenged claims. D.I., 17. The Board should
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`construe this term, consistent with its plain and ordinary meaning and its use in the
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`specification, as the creation of a small, random, noisy change. Ex. 2017, ¶48.
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`As Dr. Moon explains and the intrinsic evidence confirms, the “known
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`perturbation” is the mechanism through which the ’075 invention provides dither to
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`the converter. A “perturbation” is a small, random, noisy change. The claim
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`language recites—consistent with the patent specification’s description of the
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`invention—that this perturbation is made by redistributing the charge already
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`stored on the capacitor array during sampling of the input signal. For example, claim
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`16 recites:
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`wherein after sampling an input signal onto the switched capacitor array
`to store charge in said array, the switched capacitor digital to analog
`converter is operated to make a known perturbation to the charge
`stored on the switched capacitor array
`ʼ075 patent, claim 16; see also claim 20 (reciting that “perturbation” is supplied “to
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`the switches of a group of capacitors during sampling or during conversion”); claim
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`22 (reciting that, after sampling, the array is “operated to make a known
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`perturbation to the charge stored on the switched capacitor array or to the voltage
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`occurring on the array”); Ex. 2017, ¶49.
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`IPR2020-01559
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`Patent Owner’s Response
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`The ’075 specification repeatedly uses the term perturbation, consistent with
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`this ordinary meaning, to describe the disturbance or agitation of the charge stored
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`on the capacitor array, in a manner that introduces dither. For example:
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`• 7:46-62 (“The inventors have realised that a dither can be introduced into the
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`analog to digital converter by modifying the switch positions during
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`sampling… which in turn causes a negative perturbation to be introduced
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`into the main [capacitor] array…”);
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`• 7:62-8:4 (“selective switching of capacitors within the sub capacitor array
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`can be used to perturb the voltage that was sampled onto the main capacitor
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`array during the sampling phase and hence introduce a positive or negative
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`dither into the analog to digital converter”);
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`Trs. of Columbia Univ. v. Symantec Corp., 811 F.3d 1359, 1363 (Fed. Cir. 2016)
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`(“the only meaning that matters in claim construction is the meaning in the context
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`of the patent.”); GPNE Corp. v. Apple Inc., 830 F.3d 1365, 1370 (Fed. Cir. 2016)
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`(“when a patent ‘repeatedly and consistently’ characterizes a claim term in a
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`particular way, it is proper to construe the claim term in accordance with that
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`characterization”); Ex. 2017, ¶50.
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`The Examiner also correctly understood that a “perturbation” is a form of
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`noise. In the initial rejection of claim 16 (application claim 13), the Examiner
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`equated a “perturbation” with “noise,” referring to “a switched capacitor DAC,
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`IPR2020-01559
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`Patent Owner’s Response
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`which operates to make a known perturbation (noise) to the charge stored on the
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`switched capacitor.” Ex. 1002, 50; Ex. 2017, ¶51.
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`The Examiner’s use of “noise” as synonymous with “perturbation” is also
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`consistent with the way the Petition, the prior art, and Petitioner’s exhibits refer to
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`“dither” as the addition of “noise.” 2 Pet., 13 (referencing a diagram “showing the
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`application of dither through a pseudo-random noise generator”); id., 32 (“Hiller
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`discloses the provision of ‘well known’ dither by means of digital PRN [pseudo-
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`random noise] source 17.”); see also Ex. 1018, p. 2 (“It is, in fact, possible to reduce
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`the distortion, and also to improve the resolution below an LSB (least significant
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`bit), by adding noise (dither) to the signal of interest.”); Ex. 2017, ¶51.
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`The extrinsic evidence similarly confirms that a “perturbation” is the
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`mechanism that introduces the dither or noise. For example, the Wiley Electrical
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`and Electronics Engineering Dictionary (2004) defines dither/dithering as the
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`“incorporation of a small perturbation or a little noise, for instance to minimize the
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`effects of minor nonlinearities”. Ex. 2005; Ex. 2017, ¶52.
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`2 Petitioner also refers to perturbation and dither interchangeably when addressing
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`claim 16. Pet., 78 (“It would have been obvious to a skilled artisan to supply
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`the…so that a known perturbation (dither) will be applied…”).
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`IPR2020-01559
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`Patent Owner’s Response
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`Petitioner attempts to substantially broaden the meaning of a “perturbation”—
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`to require “simply a small change in the quality or behavior of something”—in an
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`effort to equate a perturbation with Confalonieri’s “offset compensation.” But
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`Petitioner’s definition is not only unsupported by any evidence; but also flatly
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`inconsistent with its own expert’s definition and use of the term, the ‘075
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`specification, purpose of the invention, and file history, and the extrinsic evidence.
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`Ex. 2017, ¶53.
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`Significantly, Petitioner’s expert proffered a different definition of
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`perturbation. Dr. Holberg testified that “the ordinary meaning of ‘perturbation’ is
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`simply a small change in movement, quality, or behavior of something, especially
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`an unusual change.” Ex. 1003, ¶81. The Petition, unsurprisingly, omits the last
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`clause in Dr. Holberg’s definition (which is in significant tension with Petitioner’s
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`invalidity theory). An “unusual change” connotes noise and randomness—like
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`dither—and is more consistent with Patent Owner’s proposed construction than
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`Petitioner’s. The Petition further ignores that Dr. Holberg has used the terms
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`perturbation and dither interchangeably.3 E.g., Ex. 1003, ¶29 (“The purported
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`3 Moreover, even if Dr. Holberg’s definition supported Petitioner’s argument (which
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`it does not), Dr. Holberg provides no evidence for his definition. See Phillips v.
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`AWH Corp., 415 F.3d 1303, 1318 (Fed. Cir. 2005) (en banc) (“conclusory,
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`IPR2020-01559
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`Patent Owner’s Response
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`invention of ’075 patent concerns