Patent No. 7,286,075
`Petition For Inter Partes Review
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
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`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`v.
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 7,286,075
`
`_______________
`Inter Partes Review No. ______
`____________________________________________________________
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`DECLARATION OF DR. DOUGLAS HOLBERG
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`Petition For Inter Partes Review
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`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.
`Petitioner,
`v.
`ANALOG DEVICES, INC.
`Patent Owner.
`
`Patent No. 7,286,075
`
`_______________
`Inter Partes Review No. ______
`____________________________________________________________
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`DECLARATION OF DR. DOUGLAS HOLBERG
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`Inter Partes Review of USP 7,286,075
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`APPENDIX LIST FOR DECLARATION OF DR. DOUGLAS HOLBERG
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`Appendix Description
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`Appendix
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`Curriculum Vitae
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`List of Materials Considered
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`A
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`B
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`I.
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`INTRODUCTION
`1. My name is Dr. Douglas R. Holberg. I have been retained as an
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`expert witness on behalf of Petitioner Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd.
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`(“Xilinx”) to provide expert opinions on the patentability of United States Patent
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`No. 7,286,075 (“the ’075 patent”).
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`2.
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`I am being compensated at my normal rate, plus reimbursement for
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`expenses, for my analysis. My compensation does not depend on the content of
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`my opinions or the outcome of this proceeding.
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`II. EXPERIENCE AND QUALIFICATIONS
`3.
`In formulating my opinions, I have relied upon my knowledge,
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`training, and experience in the relevant art. My qualifications are stated more fully
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`in my curriculum vitae, which has been provided as Appendix A. Here, I provide a
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`brief summary of my qualifications.
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`4. My education includes a B.S. in Electrical Engineering from Texas
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`A&M University in 1977, followed by a M.S. in Electrical Engineering from the
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`University of Texas at Austin in 1989. I earned a Ph.D. in Electrical Engineering
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`from the University of Texas at Austin in 1992.
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`5.
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`I have over 40 years of experience in the electronics field. During that
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`time, I have worked for several different electronics companies including: Mostek,
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`Texas Micro Engineering (acquired by Crystal Semiconductor), Crystal
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`Semiconductor, Cirrus Logic, Cygnal Integrated Products, and Silicon
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`Laboratories. I joined Silicon Laboratories when they acquired Cygnal, which I
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`co-founded in 1999.
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`6.
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`I am a named inventor on 40 U.S. patents. I have held a variety of
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`engineering positions throughout my career, from circuit designer, design manager,
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`Director of Engineering, Chief Technology Officer (CTO), Vice President (V.P.)
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`of Engineering, and V.P. of Technology. In addition to my engineering
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`experience, I also have served as an adjunct faculty member at the University of
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`Texas, where I taught CMOS analog and mixed-signal design for six years.
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`7.
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`I am the co-author of the textbook “CMOS Analog Circuit Design,”
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`the first edition of which published in 1987. As explained in the Preface of the
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`second edition, published in 2002, the objective of the textbook is to teach the
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`fundamentals and background that are necessary to understand how a “circuit
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`works.” It is now available in third edition and published in English and Chinese
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`(first and second edition). This textbook is widely used throughout the world by
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`new and experienced engineers in industry and by students in the classroom.
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`8.
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`Upon graduating from Texas A&M University, I went to work for
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`Mostek Corporation designing integrated circuits for telecommunications
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`applications. I designed an integrated dual tone multi frequency (DTMF)
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`generator. I received my first patent for this integrated DTMF generator. After
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`leaving Mostek, I joined a startup company, Texas Micro Engineering, as its
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`second employee. At Texas Micro Engineering, I designed, among other things, a
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`dual-channel (atrium-ventricle) pacemaker sense amplifier/filter using
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`discrete-time switched capacitor technology.
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`9. While enrolled in the Masters/Ph.D. program at the University of
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`Texas at Austin, I worked on the application of bipolar technology to dynamic
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`random access memory (DRAM) sense-amplifier architectures and
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`circuit-simulation algorithms. While at The University of Texas at Austin, I also
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`designed and laid out the mask set (The Holberg Mask Set) still in use by the
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`fabrication class/lab.
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`10. Upon graduating with a Ph.D., I went to work for Crystal
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`Semiconductor/Cirrus Logic, where I designed high frequency synthesizers for
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`hard-disk read-channel applications. I managed a group designing charge-coupled
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`device (CCD) interface circuits for digital camera applications, as well as
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`television encoder chips and CMOS imagers.
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`11. Upon leaving Cirrus, I started a company called Cygnal Integrated
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`Products, which develops mixed-signal microcontrollers. At Cygnal, I was the
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`founder, CTO, V.P. of Engineering, and an individual contributor. While at
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`Cygnal, I designed analog-to-digital converters (ADCs), (cid:39)Vbe temperature
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`sensors, input/output (I/O) cells/pads (both design and layout), as well as many
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`additional miscellaneous circuits. My company was later purchased by Silicon
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`Laboratories, where I remained employed as a manager of the microcontroller
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`group, followed by the position of V.P. of Technology.
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`12.
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`I have significant experience with the technology described in the
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`’075 patent, including analog to digital converters (ADCs) and digital to analog
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`converters (DACs). In addition, I have experience with r capacitors, transistors,
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`operational amplifiers, comparators, resistors, diodes, inductors, transformers,
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`oscillators, general integrated-circuit technology, analog/digital mixed-signal
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`circuits, device analysis and modeling, floor-planning and layout of integrated
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`circuits, and the tools used to design and verify integrated circuits (i.e., CAD
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`tools). In addition, I have experience with device modeling and characterization,
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`which has been applied throughout my career.
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`13. My analyses set forth in this declaration are informed by my
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`experience in the field of electrical engineering, including analog circuitry, ADCs,
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`and DACs. Based on my above-described experience, I believe that I am
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`considered to be an expert in the field.
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`III. MATERIALS CONSIDERED
`14.
`In preparing this Declaration, I have reviewed the ’075 patent and file
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`history. I also have considered each of the documents cited in this Declaration,
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`and the documents specifically identified in Appendix B. In formulating my
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`opinions, I have further relied upon my extensive experience in the relevant fields.
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`IV. BACKGROUND OF THE TECHNOLOGY
`A.
`Switched Capacitor Analog-to-Digital Converters
`15. ADCs are commonly used electronic devices for converting an analog
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`signal into a digital representation, while digital-to-analog converters (DACs)
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`perform the opposite operation—converting a digital signal into an analog one. By
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`November 2005 (the filing date of the ’075 patent) a wide variety of ADCs were
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`known, including flash, successive approximation (SAR), pipeline, and delta-
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`sigma converter architectures.
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`16. Switched capacitors have been used for many years in ADCs and
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`DACs. (McCreary, 1.) Capacitor-based ADCs operate by charge redistribution.
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`This technique, known since at least 1975 in successive approximation converter
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`architectures (also referred to as “SAR ADCs”), was in wide use by 2005. (See
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`McCreary.)
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`17. Such SAR ADCs are described, e.g., in a tutorial by Maxim Integrated
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`entitled “Understanding SAR ADCs: Their Architecture and Comparison with
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`Other ADCs,” where it is stated that “[s]uccessive-approximation-register SAR
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`analog-to-digital converters (ADCs) represent the majority of the ADC market for
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`medium- to high-resolution ADCs.” (Maxim Tutorial, 1.) Figure 1 (below)
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`illustrates a basic ADC architecture, which includes a feedback DAC that provides
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`a voltage for comparison to the analog input signal.
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`18. Figure 3 (below) illustrates a capacitive DAC that may be used as the
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`DAC in such ADCs.
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`19. Texas Instruments showed a similar architecture, in Figure 1 (below),
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`in a document entitled “The operation of the SAR-ADC based on charge
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`redistribution.” (See Kugelstadt.) As stated in the first sentence of the document
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`“[a]ll Texas Instruments TLV- and TLC-series sequential serial analog-to-digital
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`converters perform successive approximation based on charge redistribution.” (Id.,
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`1.)
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`20. The operation of SAR ADCs is also described in a reference guide
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`from Crystal/Cirrus Logic. (Crystal Ref. Guide, 21–24.) As Crystal/Cirrus Logic
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`acknowledges “[m]ost of today’s Successive Approximation Analog-to-Digital
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`Converters use binary-weighted capacitive arrays.” (Id., 21.)
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`21. The SAR technique involves sampling and holding the input signal
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`onto a capacitor array (usually binary-weighted), followed by selectively switching
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`each capacitor to one of two reference voltages (with one of them being ground in
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`a single-ended conversion system). (McCreary, 2–3.) This switching leads to a
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`redistribution of the charge and a change in voltage, which is assessed by a
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`comparator to determine the various bits of the digital signal. (Id., 2.) Thus, in
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`switched-capacitor architectures, the capacitor array performs various functions,
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`including receiving and holding the input signal, as well as operating as a DAC in
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`the successive approximation operation. (Maxim Tutorial, 1–4; Kugelstadt;
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`Crystal Ref. Guide, 21.)
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`B. Use of Dither in ADCs
`22. Dithering is a method used in ADCs to reduce non-linearity. The
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`reduction in non-linearity results in improved conversion accuracy. The method of
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`using dither to ADCs was known long before November 2005.
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`23. For example, a review article by Balestrieri describes using dither as
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`one of many ADC error compensation methods. Specifically, the review article
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`describes a “method for randomizing the ADC quantization errors by adding a
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`stimulus uncorrelated to the desired signal at the ADC input.” (Balestrieri, 1–3.)
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`24. Figure 5 (below) illustrates a system block diagram that includes a
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`typical ADC using dither. The dither is applied through a pseudo-random noise
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`generator coupled to an internal DAC. (Id., 3.)
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`25. Figure 1 (below) of Giangano, filed in 1990, illustrates a similar
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`arrangement. Giangano discloses applying the output of the number generator 1 to
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`an internal DAC 3 and adding it to an input signal VIN at adder 5. (Giangano,
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`3:2–4.) The number generator 1 is a “random number or sequential number
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`generator of conventional design.” (Id.) The resultant output on line 7 is
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`converted to a digital value by ADC 8. (Id., 3:8.) As Giangano acknowledges, “it
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`is important to restore the original input voltage [VIN]” so that the original voltage
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`is retrieved. (Id., 3:13–19.) A digital subtractor 11 is used to restore the original
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`input voltage VIN by subtracting the number generated by the number generator 1
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`from the digital value output from ADC 8. (Id.)
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`V.
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`SUMMARY OF THE ’075 PATENT
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`A.
`Filing Date and Priority Dates
`26. The ’075 patent claims priority to Application No. 11/273,196, filed
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`on November 14, 2005. The ’075 patent issued on October 23, 2007.
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`B.
`Specification
`27. The ’075 patent relates to an ADC employing switched capacitor
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`circuits and methods for using such converters. (’075 Patent, Abstract.) In
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`particular, the ’075 patent is directed to applying a perturbation, such as dither, to
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`an ADC. (Id., 1:6–9.) As the ’075 patent explains, ADCs exhibit non-linearities,
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`such as integral non-linearity (INL) and differential non-linearity (DNL). (Id.,
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`1:19–20, 1:37–40.) These non-linearities lead to problems such as “missing
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`codes.” (Id., 1:31–36.) “Missing codes” are unwanted because they lead to some
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`analog signal ranges not producing the correct corresponding digital code at the
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`output, as shown in Fig, 1 (reproduced below) of the ’075 patent. (Id., 3:37–52.)
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`28.
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`It was well-known in the prior art that applying a varying, but known
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`voltage, minimizes DNL errors and avoids the problem of “missing codes.” (Id.,
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`1:47–52, 4:1–3.)
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`29. The purported invention of ’075 patent concerns the application of a
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`perturbation/dither using capacitors that may already be part of the ADC. (Id.,
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`2:5–7, 4:23–30.)
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`30.
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` Figure 3 (below) illustrates an ADC of the ’075 patent. (Id., 4:43–
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`44.) The ADC comprises two switched capacitor arrays: a P-DAC connected to
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`the non-inverting input 4 of a comparator 6 and an N-DAC connected to the
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`inverting input 8. (Id., 4:45–50, Fig. 3.)
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`31. The P-DAC may include a main DAC array 2 (also referred to as
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`“MAIN P-DAC 2”) and a sub array 10 (also referred to as “SUB-DAC 10”). (Id.,
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`5:2–5.) In one embodiment, the main DAC array 2 and the sub DAC array 10 may
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`be “segmented.” (Id., 4:67–5:1.) As shown in Figure 3 (above), the main DAC
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`array 2 and the sub DAC array 10 are segmented by a coupling capacitor 12. (Id.,
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`5:5–11.) The capacitors in each switched capacitor array have associated switches
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`to connect the plates to either one of two reference voltages, Vrefn or Vrefp, or the
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`input voltage signal Ain (also referred to as “AIN”). (Id., 5:57–65.) Vrefn may
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`correspond to ground. (Id., 5:61–62.)
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`32. The ADC operates in a sampling phase and a conversion phase. In the
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`sampling phase, the capacitors CB to CN of the main DAC array 2 are connected
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`to the input signal path Ain using switches SB to SN. (Id., 5:62–65.) When the
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`switches SB to SN connect capacitors CB to CN to input signal path Ain, the input
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`voltage is sampled onto capacitors CB to CN. (Id.)
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`33. After the sampling phase, in the conversion phase, the “well-known”
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`successive approximation (SA) search is performed. (Id., 6:33–38.) The SA
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`search involves testing bits corresponding to the capacitors in the switched
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`capacitor array. Each individual capacitor in the switched capacitor array is
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`connected using a respective switch to a reference voltage. (Id., 6:33–43, Fig. 3.)
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`The capacitors of the array effectively form a capacitive potential divider, which
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`changes the voltage at the non-inverting input 4 of the comparator 6. (Id., 6:43–45,
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`Fig. 3.) The comparator 6 compares the voltage at its non-inverting input 4 to the
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`voltage at its inverting input 8 to see whether the voltage at its non-inverting input
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`4 is greater or less than the voltage at its inverting input 8. (Id., 6:45–47, Fig. 3.)
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`Based on the results of the comparison, the bit is either kept as part of the digital
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`output or discarded. (Id., 6:47–65, Fig. 3.)
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`34. Both the main DAC array 2 and the sub DAC array 10 participate in
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`the conversion, whereas only the main DAC array 2 participates in the sampling.
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`(Id., 5:62–65, 6:4–5, 6:38–56.) I note that Figure 3 (above) shows the successive
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`approximation controller 44 as connected to the switches SAC1 and SAC2. In the
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`’075 patent, the only discussion regarding the successive approximation controller
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`44 is at 8:59–62, which discusses the successive approximation controller 44
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`passing the result from the successive approximation conversion to adder 42.
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`35. The ’075 patent discusses correcting conversion errors by applying a
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`dither. (Id., 4:1–3.) The dither can be applied by using capacitors in the switched
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`capacitor array. (Id., 7:46–51.) The capacitors for applying the dither may be part
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`of the main DAC array 2, part of the sub DAC array 10, or additional capacitors
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`AC1 to AC3 as shown in Figure 3 (below). (Id., 7:46–8:22.) The dither may be
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`introduced by altering the switch positions of any of the switches S1 to SN or
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`SAC1 to SAC2 based on the pseudo random number generated by a pseudo
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`random number generator 40. (Id., 7:46–8:34.) The dither capacitors are
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`connected to Vrefp or Vrefn, based on the output of the pseudorandom generator 40
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`controlling each capacitor’s individual switch. (Id.) This technique “enables a
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`dither to be applied to a sampled voltage without introducing any additional
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`components into the analog signal path,” and “the dither can be applied without
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`fabricating any additional components within the analog to digital converter.” (Id.,
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`9:10–15.) Stated in another way, this technique “may be implemented without
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`modification of the switched capacitor array.” (Id., 4:29–30.)
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`36. The ’075 patent discloses different embodiments for applying dither.
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`In the first embodiment, the dither is applied using only the capacitors of the main
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`DAC array 10 and the sub DAC array 2. (Id., 4:23–30, 7:6–8:4, 9:10–15.) In this
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`embodiment, no additional capacitors are used to apply dither. (Id.)
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`37.
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`In the second embodiment, the dither is applied using some of the
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`capacitors in the sub DAC array 2 and one additional capacitor AC1. (Id., 8:5–15.)
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`38.
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`In the third embodiment, the dither is applied using multiple
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`additional capacitors AC1 to AC3 exclusively. (Id., 8:16–34.) As shown in Figure
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`3 (highlighted below), the capacitors AC1 to AC3 are separate from the main DAC
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`array 2 and the sub array 10.
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`2
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`Claims
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`I was asked to evaluate whether claims 1—25 of the ’075 patent are
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`C.
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`39.
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`patentable.
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`40.
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`Claim | is an apparatus claim directed to an ADC for converting an
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`analog input signalto a digital output signal. The claim requiresa first group of
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`capacitors for participating in a SA conversion. The claim requires each capacitor
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`haveat least one associated switch for controlling the connection of the capacitor
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`to a first or second reference voltage.
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`41. The claim also requires a second group of capacitors for applying a
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`dither and having switches for selectively connecting the capacitors to the first or
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`second reference voltage and a sequence generator. The sequence generator
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`generates a sequence of bits.
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`42. As required by the claim, during sampling of the analog input signal
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`onto at least some of the first group capacitors, or during conversion of a sample of
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`the analog input signal, the sequence generator supplies an output to the switches
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`of the second group of capacitors. The output from the sequence generator
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`controls whether a given capacitor of the second group of capacitors is connected
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`to the first or second reference voltage, so that a dither is applied to the conversion.
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`43. Claim 16 is an independent claim directed to an ADC system, and
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`claim 24 is an independent claim directed to a segmented ADC. Claim 20 is an
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`independent claim directed to a method for applying a dither to an ADC, and claim
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`22 is an independent claim directed to a method for adding dither to an input signal
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`to be digitized by an ADC.
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`44. Dependent claim 2 relates to the switches for the first group of
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`capacitors. Dependent claims 3, 4, 14, 15, 18, and 19 relate to the capacitors in the
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`second group of capacitors being switched to a certain state/value or connected to a
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`second reference voltage. Dependent claims 5 and 11 relate to capacitance values
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`of capacitors in the second group of capacitors. Dependent claim 6 relates to a
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`coupling capacitor. Dependent claim 7 relates to the weighing of the capacitors.
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`Dependent claim 8 relates to error correction bits. Dependent claims 9 and 21
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`relate to a pseudorandom bit sequence random/pseudo random changes.
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`Dependent claim 10 relates to an adder to apply a correction. Dependent claim 12
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`relates to a P-DAC and an N-DAC. Dependent claims 13 and 23 relate to additive
`
`dither, subtractive dither, or both. Dependent claim 17 relates to a switched
`
`capacitor DAC being an integral part of the switched capacitor array. Dependent
`
`claim 25 relates to the capacitors applying the dither as not varied during a SA
`
`conversion.
`
`VI. CLAIM CONSTRUCTION
`45.
`I have been informed that claim construction requires consideration of
`
`the words of the claims themselves, the specification, the prosecution history, and
`
`extrinsic evidence concerning relevant scientific principles, the meaning of
`
`technical terms, and the state of the art. I have also been informed that the
`
`specification is usually definitive, as it is the single best guide to the meaning of a
`
`disputed term.
`
`46.
`
`I have been informed that Xilinx did not propose a construction of any
`
`term. I agree that no terms need to be construed for the ’075 patent.
`
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`sf-4329103
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`
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`Inter Partes Review of USP 7,286,075
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`VII. RELEVANT LEGAL STANDARDS
`A. Anticipation
`47.
`It is my understanding that the claims of a patent are anticipated by a
`
`
`
`prior art reference if each and every element of the claim is found either explicitly
`
`or inherently in a single prior art reference or system. I understand that inherency
`
`requires a showing that the missing descriptive matter in the claim is necessarily or
`
`implicitly present in the allegedly anticipating reference and that it would have
`
`been so recognized by a person of ordinary skill in the art (“POSITA”). In
`
`addition, I understand that an enabling disclosure is a disclosure that allows a
`
`POSITA to make the invention without undue experimentation. Although
`
`anticipation typically involves the analysis of a single prior art reference, I
`
`understand that additional references may be used to show that the primary
`
`reference has enabling disclosure, to explain the meaning of a term used in the
`
`primary reference, and/or to show that a characteristic is inherent in the primary
`
`reference.
`
`48.
`
`I understand that if the reference is a device or system, the public need
`
`not have access to the inner workings of a device for it to be considered in public
`
`use or used by others.
`
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`sf-4329103
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`
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`Inter Partes Review of USP 7,286,075
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`
`B. Obviousness
`49.
`I understand that a claim is unpatentable if the differences between the
`
`
`
`claimed subject matter and the prior art are such that the subject matter as a whole
`
`would have been obvious at the time the claimed subject matter was made to a
`
`POSITA to which the subject matter pertains. I understand that a patent claim may
`
`be obvious to a POSITA in view of the prior art teachings of a single reference or a
`
`combination of references.
`
`50. To assess obviousness, I understand that I am to consider the scope
`
`and content of the prior art, the differences between the prior art and the claim, the
`
`level of ordinary skill in the art, and any secondary considerations to the extent
`
`they exist.
`
`51.
`
`It is also my understanding that there are principles that may be used
`
`as further guidance in obviousness analysis (especially when considering
`
`combinations of references), which include considering whether:
`
`(cid:120) the claimed subject matter is simply a combination of prior art elements
`
`according to known methods to yield predictable results;
`
`(cid:120) the claimed subject matter is a simple substitution of one known element
`
`for another to obtain predictable results;
`
`
`sf-4329103
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`Inter Partes Review of USP 7,286,075
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`
`(cid:120) the claimed subject matter uses known techniques to improve similar
`
`
`
`devices or methods in the same way;
`
`(cid:120) the claimed subject matter applies a known technique to a known device
`
`or method that is ready for improvement to yield predictable results;
`
`(cid:120) the claimed subject matter would have been “obvious to try” choosing
`
`from a finite number of identified, predictable solutions, with a
`
`reasonable expectation of success;
`
`(cid:120) there is known work in one field of endeavor that may prompt variations
`
`of it for use in either the same field or a different one based on design
`
`incentives or other market forces if the variations would have been
`
`predictable to a POSITA;
`
`(cid:120) there existed at the time of conception and reduction to practice a known
`
`problem for which there was an obvious solution encompassed by the
`
`patent’s claims; and
`
`(cid:120) there is some teaching, suggestion, or motivation in the prior art that
`
`would have led a POSITA to modify the prior art reference or to combine
`
`prior art reference teachings to arrive at the claimed subject matter.
`
`52.
`
`I understand that there are secondary considerations that may tend to
`
`show that a claimed invention would not have been obvious to a POSITA. These
`
`
`sf-4329103
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`Inter Partes Review of USP 7,286,075
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`include, for example, commercial success, long-felt but unsolved needs, failure of
`
`
`
`others, and unexpected results. I further understand that there must be a
`
`relationship, or nexus, between any secondary considerations and the novelty of
`
`the claimed invention.
`
`VIII. LEVEL OF ORDINARY SKILL IN THE ART FOR THE ’075
`PATENT
`53.
`I am informed and understand that various factors can be considered
`
`in determining a POSITA. I am informed and understand that those factors
`
`include: (1) the educational level of the inventors; (2) the type of problems
`
`encountered in the art; (3) prior art solutions to those problems; (4) the rapidity
`
`with which innovations are made; (5) sophistication of the technology; and (6)
`
`education level of active workers in the field.
`
`54.
`
`I have been informed that Xilinx proposed in the Petition that a
`
`POSITA in the field of the ’075 patent in 2005 would have at least a Master’s
`
`degree in Electrical Engineering or equivalent field, including studies in the area of
`
`analog circuitry; or at least a Bachelor’s Degree in Electrical Engineering and at
`
`least two years of experience working on analog circuitry design.
`
`55.
`
`I agree with this level of ordinary skill for the ’075 patent. Based on
`
`my experiences, I understand and know of the capabilities of a person of this skill
`
`level as of the time the ’075 patent was filed in 2005. I am familiar with how a
`
`
`sf-4329103
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`
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`Inter Partes Review of USP 7,286,075
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`POSITA would have understood and used the terminology found in the ’075 patent
`
`
`
`at the time of its filing, and with the state of the art at that time.
`
`IX. PRIOR ART
`56.
`I understand that each of the references discussed herein qualifies as
`
`prior art against the ’075 patent:
`
`57. U.S. Patent No. 6,660,437 (“Confalonieri,” Ex. 1013) was filed on
`
`April 1, 2002 and issued on July 29, 2003;
`
`58. U.S. Patent No. 4,550,309 (“Hiller,” Ex. 1014) was filed on February
`
`16, 1984 and issued on October 29, 1985;
`
`59. U.S. Patent No. 5,675,340 (“Hester,” Ex. 1015) was filed on April 7,
`
`1995 and issued on October 7, 1997;
`
`60. U.S. Patent No. 7,129,847 (“Bjornsen,” Ex. 1016) was filed on June
`
`10, 2005 and claims priority to a provisional application filed on June 10, 2004.
`
`Bjornsen published on December 15, 2005 and issued on October 31, 2006; and
`
`61. U.S. Patent No. 6,914,550 (“Cai,” Ex. 1018) was filed on October 9,
`
`2003, published on April 14, 2005, and issued on July 5, 2005.
`
`
`sf-4329103
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`
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`Inter Partes Review of USP 7,286,075
`
`X. ANALYSIS AND OPINIONS
`A. Claims 16 and 17 Are Unpatentable As Obvious Over
`Confalonieri Under 35 U.S.C. § 103(a)
`1.
`Summary of Confalonieri
`62. Confalonieri discloses a DAC for use in an analog-to-digital converter
`
`
`
`(A/D converter). (Confalonieri, 1:6–29, 3:35–42, 5:13–17.) Figure 4 (below)
`
`illustrates the DAC. The DAC comprises lower and upper arrays of switched
`
`capacitors. (Id., Fig. 4.) The DAC includes a shunt capacitance CATT. (Id.) The
`
`shunt capacitance CATT compensates for offset. (Id., 5:17–25.) Additionally, the
`
`shunt capacitance CATT enables all capacitors in the DAC to be integer numbers of
`
`a unit capacitance. (Id., 4:36–5:12.) As a result, the DAC is “more linear and
`
`accurate in operation.” (Id., 4:50; see also id., 4:65–5:4.)
`
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`sf-4329103
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`
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`Inter Partes Review of USP 7,286,075
`
`
`
`
`
`
`63. Figure 5 (highlighted below) shows an embodiment “used
`
`advantageously when it is required that an analog value corresponding to a given
`
`correction digital code is added to the analog voltage obtained from the
`
`conversion.” (Id., 5:13–17.) As shown in the figure, the shunt capacitance CATT
`
`(highlighted) is formed of a switched capacitor array comprising capacitors CA0,
`
`CA1, and CA2 and a group SWC of switches (including switches SWC1 and SW2).
`
`(Id., 5:13–39.)
`
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`
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`Inter Partes Review of USP 7,286,075
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`
`
` REGISTER.
`
`HIG.
`
`od
`
`64.
`
`The group SWC of switches are controlled by a digital code (also
`
`referred to as “correction digital code”). (/d., 5:33-36.) The digital code
`
`correspondsto the offset to be compensated. (/d.) The digital code consists of two
`
`bits BO and B1 andis stored in a register 10. Ud.) The capacitors C4, and Ca,
`
`(includedin the shunt capacitance Carr) are charged accordingto the digital code,
`
`whichresults in varying the voltage at the common node NSLofthe lowerarray.
`
`(Id., 5:36-39.)
`
`65.
`
`The use of the shunt capacitance Carr is not limited to improving
`
`accuracy by virtue of usin
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