throbber
UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` ______________________________
`
` ANALOG DEVICES, INC.
`
` Petitioner
`
` v.
`
` XILINX, INC.
`
` Patent Owner
`
` _____________________________
`
` Case No. IPR2020-01599
`
` Patent No. 7,286,075
`
` REMOTE VIDEO CONFERENCE
`
` VIDEOTAPED DEPOSITION OF
`
` UN-KU MOON, PH.D.
`
`DATE TAKEN: WEDNESDAY, SEPTEMBER 1, 2021
`
`REPORTED BY: RENEE HARRIS, CSR, CCR, RPR
`
`JOB NO. 4753420
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`PAGES: 1 - 126
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1023 Page 1
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

` UNITED STATES PATENT AND TRADEMARK OFFICE
`
` BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
` ______________________________
`
` ANALOG DEVICES, INC.
`
` Petitioner
`
` v.
`
` XILINX, INC.
`
` Patent Owner
`
` _____________________________
`
` Case No. IPR2020-01599
`
` Patent No. 7,286,075
`
` Remote Deposition of UN-KU MOON, PH.D.,
`
`the witness herein, at 9:04 a.m. Pacific Daylight
`
`Time, on Wednesday, September 1, 2021, before
`
`Renee Harris, California Certified Shorthand
`
`Reporter No. 14168, New Jersey Certified Court
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`Reporter No. 30XI00241200, and Registered
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`Professional Reporter.
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`

`

`A P P E A R A N C E S O F C O U N S E L :
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`O N B E H A L F O F P E T I T I O N E R A N A L O G D E V I C E S :
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` W I L M E R C U T L E R P I C K E R I N G H A L E A N D D O R R , L L P
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` B Y : B R I A N J . L A M B S O N , E S Q .
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` 1 8 7 5 P e n n s y l v a n i a A v e n u e , N W
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` W a s h i n g t o n D C 2 0 0 0 6
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` 6 5 0 - 6 0 0 - 5 0 2 6
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` b r i a n . l a m b s o n @ w i l m e r h a l e . c o m
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`O N B E H A L F O F P A T E N T O W N E R X I L I N X , I N C . :
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` M O R R I S O N & F O E R S T E R L L P
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` B Y : H E C T O R G . G A L L E G O S , E S Q .
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` J E A N N G U Y E N , E S Q .
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` 4 2 5 M a r k e t S t r e e t
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` S a n F r a n c i s c o , C A 9 4 1 0 5
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` ( 2 1 3 ) 8 9 2 - 5 2 5 5
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` h g a l l e g o s @ m o f o . c o m
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` j n g u y e n @ m o f o . c o m
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`A l s o P r e s e n t :
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` M i h a i M u r g u l e s c u , A n a l o g D e v i c e s , I n c .
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` S h u o - W e i C h a n
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`

`

` INDEX
`
`EXAMINATION BY: PAGE
`
`MR. GALLEGOS 5
`
` EXHIBITS
`
`EXHIBIT NO. DESCRIPTION PAGE
`
`Exhibit 1001 U.S. Patent 7,286,075 39
`
`Exhibit 1002 Prosecution History 113
`
`Exhibit 1012 U.S. Patent 6,600,437 (Confalonieri) 51
`
`Exhibit 1015 U.S. Patent 7,129,874 (Bjornsen) 73
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`Exhibit 1017 U.S. Patent 6,914,550 (Cai) 108
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`Exhibit 2001 First Declaration, Un-Ku Moon, Ph.D. 40
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`Exhibit 2017 Second Declaration, Un-Ku Moon, Ph.D. 94
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
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`

`

` APPEARING REMOTELY FROM CORVALLIS, OREGON;
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` WEDNESDAY, SEPTEMBER 1, 2021; 9:04 A.M.,
`
` UN-KU MOON, PH.D.,
`
`called as a witness and having been first duly
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`sworn by the Certified Shorthand Reporter, was
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`examined and testified as follows:
`
` EXAMINATION
`
` BY MR. GALLEGOS:
`
` Q. Good morning.
`
` A. Good morning.
`
` Q. Please state and spell your name for the
`
`record.
`
` A. Un-Ku Moon. U-n, k-u, last name m-o-o-n.
`
`Sometimes there's a hyphen between u-n and k-u.
`
` Q. Thank you, Dr. Moon.
`
` Are you under any medication that might
`
`prevent you from giving full and accurate answers
`
`today?
`
` A. No.
`
` Q. Is there any reason that would prevent
`
`you from giving full and accurate answers today?
`
` A. No, no reason not to.
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` Q. On your screen there, do you have any --
`
`do you have access to the live transcript of
`
`today's deposition?
`
` A. I don't. It's probably distracting,
`
`anyway, so...
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` Q. Do you have any other windows or programs
`
`like chat boxes open on your screen?
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` A. No. I just have this Firefox browser for
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`the Veritext.
`
` Q. Do you have any paper copies of your
`
`declarations or any of the exhibits that are part
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`of this proceeding there with you in your office?
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` A. Yeah, I have -- I have my declaration, I
`
`have the board decision and I have the '075
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`patent.
`
` Q. When you say your "declaration," you've
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`submitted two declarations in this proceeding;
`
`correct?
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` A. Yeah. The latest one. The longer one,
`
`yeah.
`
` Q. Does it have the designation Exhibit 2017
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`in the corner?
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` A. What would that be again?
`
` Q. 2017.
`
` A. 2017. I may have printed this from my
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`own work file. You said the exhibit number? Is
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`that what you're referring to?
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` Q. Yes, sir.
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` A. So this one must be printed from my work
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`file, I'm guessing.
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` Q. But you understand that would be a true
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`and accurate copy of the second declaration you
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`submitted in this proceeding; is that correct?
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` A. Yes. And usually when you share, I
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`usually look at it on the computer just because
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`it's better for my eyes, so...
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` Q. Understood.
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` A. Yeah.
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` Q. On all of the paper documents that you
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`have there with you, do you have any handwritten
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`notes on any of the pages?
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` A. No. Just the circle with the name in the
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`front.
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` Q. I'm sorry, what do you mean by "just the
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`circle with the name in the front"?
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` A. I have like a circle around
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`"declaration." Circle around "decision." Circle
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`around "Hennessy." So I sort of know which one
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`I'm grabbing, yeah.
`
` Q. Understood. Thank you.
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` So I assumed you were in your office, but
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`why don't you make clear for the record: Where is
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`it that you're seated?
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` A. I'm in my office, yeah.
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` Q. And is there anyone in the room there
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`with you?
`
` A. No.
`
` Q. Dr. Moon, have you ever designed a SAR
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`ADC?
`
` A. Yes.
`
` Q. And when was that?
`
` A. The latest publication on that was 2019.
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` Q. Was that the only SAR ADC you've
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`designed?
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` A. No. There are a number of SARs before
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`that.
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` Q. When was the earliest?
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` A. Earliest, I can't -- I can't remember the
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`year. So it's probably, if I would guess, maybe
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`15 years or so maybe.
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` Q. So approximately --
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` A. But I have -- I can look through my list
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`of publications if there's an opportunity.
`
` Q. Just approximately, 2006 or so?
`
` A. 2005, 2006, yeah. I'm just -- the name
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`that comes to mind is my student name Hariprasath
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`Venkatram that might -- that might have been one
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`of the earlier ones.
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` Q. How many SAR ADCs do you think you've
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`actually designed?
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` A. I don't know. A number of them. There
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`are SARs chips and there are publications about
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`SAR architectures, things like that, so...
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` Q. How many SAR ADCs went as far as tape-out
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`that you designed?
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` A. It's really hard to remember that exactly
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`because I do have a lot of publications.
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` Q. But at least some of the SAR ADCs you
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`designed did go to tape-out; is that correct?
`
` A. Yeah, 2019. The latest one I remember
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`very well since that's pretty recent, yeah.
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` Q. Have you ever designed a pipelined ADC?
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` A. Yes, I have -- I have done a lot of
`
`those, yes.
`
` Q. When is the most recent one?
`
` A. The one I just mentioned, the 2019 one is
`
`a pipeline SAR. So that's already a pipeline in
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`that sense.
`
` What are some other pipelines? There's a
`
`pipeline a few years back probably based on some
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`time domain stuff. There's lots of them. Again,
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`publications records is probably a good way to
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`scan through. Search for "pipeline." I usually
`
`say that, yeah.
`
` Q. And the most recent one which was the
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`pipelined SAR, how many stages did that have?
`
` A. Two-step. That was two-step.
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` Q. So in each step, how many bit trials were
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`there?
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` A. So again, this is just coming from
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`memory. So even though it's my own work, so with
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`that in mind, I think the first stage I had about
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`9 or so bits, and then it was followed by another
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`9 or so in the second stage.
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` I say two stages, but it's -- the first
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`stage is sort of a broken up into coarse and fine.
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`There's another little thing that's part of the
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`first stage which is a 5-bit coarse quantizer if I
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`remember correctly. But if you're a pipeline
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`person, you would think of this as two-step, yeah.
`
` Q. Did you also design pipelined ADCs that
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`did not involve a SAR per stage?
`
` A. Yeah. So some of the earlier pipeline
`
`work typically has a flash, sub-ADC. So some of
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`those would not have SAR.
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` Q. The most recent SAR ADC that was the
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`pipelined ADC, that had switched capacitors in the
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`ADCs; is that correct?
`
` A. Yeah, it's a discrete time. Yeah.
`
` Q. As part of that -- strike that.
`
` Have you ever designed a delta-sigma ADC?
`
` A. Yes.
`
` Q. When was that?
`
` A. I have done lots. Actually when I first
`
`came to -- I actually worked on delta-sigma for a
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`while, from as far back as 20-some years.
`
` Q. So in the latest SAR ADC that you
`
`designed that was part of the pipelined ADC, was
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`dither applied?
`
` (Reporter clarification.)
`
` THE WITNESS: Yes. Yes, the dither was
`
` applied in the first stage.
`
`BY MR. GALLEGOS:
`
` Q. So after the input signal -- let me
`
`clarify that.
`
` So dither was not applied to the input
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`signal prior to the ADC; is that correct?
`
` MR. LAMBSON: Objection to form.
`
` THE WITNESS: So I don't know what you're
`
` so -- if you're trying to relate to patent,
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` if you can be a little more specific, we can
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` deal with that.
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` So this one had a -- just explain what
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` this is. It had a 9-bit first stage, and the
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` dither was added to help with the residue
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` amplifier non-linearity. The purpose of this
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` one was that, yeah.
`
` BY MR. GALLEGOS:
`
` Q. So where exactly was it applied?
`
` A. I don't think you'll follow exactly, as
`
`you can apply in different places. But we -- you
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`know what, I don't think I can give you an exact
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`answer. But I'll have to look at the details
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`again.
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` But bottom line is, dither is there by
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`the time it does the residue amplification. So
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`that you who go through active stage, residue
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`amplification, it tends to be non-linear; that the
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`addition of dither helped linearize that. That
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`was the purpose. So I can say that, yeah.
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` Q. Was dither subsequently removed?
`
` A. Yes.
`
` Q. And was it removed immediately after the
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`residue amplifier?
`
` A. The dither is removed in the digital
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`domain after the bits.
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` Q. So this dither was applied before the
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`residue amplifier; correct?
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` MR. LAMBSON: Objection to form.
`
` THE WITNESS: So someplace before,
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` sometime before the residue amplification is
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` done, the residue is gained up, yeah.
`
` BY MR. GALLEGOS:
`
` Q. So it was sometime -- strike that.
`
` You don't recall where it was actually
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`applied, whether it was at the input signal or
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`somewhere during the bit trials or after the bit
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`trials in the first stage, but prior to the
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`residue amplifier; is that correct?
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` MR. LAMBSON: Objection to form.
`
` THE WITNESS: Well, if you're asking if
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` it was like externally added, it's not -- it
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` wasn't done that way.
`
` The SAR process, you can do it many
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` different ways. As I told you before, the
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` first stage is a 9-bit, but I told you there
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` was a course quantization, and it does some
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` course quantization, and then it -- the
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` subranging. So there are opportunities to do
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` that at different times.
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` So it was -- that's the part I can't
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` remember exactly, yeah.
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` BY MR. GALLEGOS:
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` Q. Would it make a difference as to where in
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`those various times you referred to that dither
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`was introduced?
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` MR. LAMBSON: Objection to form.
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` THE WITNESS: Before the -- yeah. I
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` mean, again, what I'm going to say is for the
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` purpose of what we wanted to do, for the
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` residue amplifier, there's -- there's -- you
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` just had to get there before the residue
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` amplifier. But you have to take care of
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` other things.
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` It's just when you start putting stuff
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` into the chip, you have to make sure it's not
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` doing anything else.
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` BY MR. GALLEGOS:
`
` Q. Did you design any SAR ADCs where dither
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`was not applied?
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` A. Yeah. So some of the SARS I've done
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`before, we did not use dither. I remember one
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`work where we -- where we called -- what we called
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`SAR to trilevel SAR, and where we took advantage
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`of the regeneration time in the comparator. So
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`that SAR had no dither.
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` Q. Did you design any SAR ADCs where dither
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`was applied but not subsequently removed?
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` A. No. I can't imagine that ever happening
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`in a SAR.
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` Q. Why is that?
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` A. Because if you put dither into the SAR,
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`you're adding noise. So you'll lose accuracy if
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`you don't remove it.
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` Q. Did you design any SAR ADCs where dither
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`was applied to the input signal prior to the
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`converter?
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` MR. LAMBSON: Objection to form.
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` THE WITNESS: Yeah, I'm not exactly sure
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` what you're referring to. I don't -- if
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` you're talking, if I try to test something,
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` and you know, externally added the dither
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` stuff, I haven't done that work.
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` BY MR. GALLEGOS:
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` Q. So to the extent that you've designed SAR
`
`ADCs and tested them in your lab and you used
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`dither, dither was always applied to the
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`converter; is that your testimony?
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` MR. LAMBSON: Objection.
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` THE WITNESS: The dither I have applied
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` to SAR, the one that I remember very clearly
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` is the one I just described.
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` Trying to think of other things, and it's
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` not -- other variations. Nothing comes to
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` mind immediately, so...
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` BY MR. GALLEGOS:
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` Q. Let's focus on the SAR ADCs, the early
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`ones, as far back as the 2005 time frame.
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` A. Okay.
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` Q. Did they involve dither or the
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`application of dither?
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` A. No. A lot of our focus then was trying
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`to improve like the DNL, INL types of things with
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`proper kind of switching sequence of the charge
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`from capacitors.
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` Q. What was the earliest SAR ADC you
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`designed that dither was applied?
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` A. Where dither was applied? That's the
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`thing. I'm trying to think of a SAR specifically,
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`because dither has been applied and sometimes it's
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`pipeline, and I can think of sometimes it's
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`delta-sigma.
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` Applying dither in a SAR, first of all,
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`was not that -- it was not common until very
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`recently. So I'm trying to think of when I did
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`that other than 2019, and it's difficult for me to
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`get specific without really scanning through my --
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`I have like 300 papers. So I have to really look
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`through them if I want to get any more detailed.
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` Q. For all of the ADCs that you designed
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`where dither was applied, was dither always
`
`removed after conversion?
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` MR. LAMBSON: Objection to form.
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` THE WITNESS: I would say no. Like
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` delta-sigma, dither's almost never removed.
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` I can't think of one I removed, yeah.
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` BY MR. GALLEGOS:
`
` Q. So for the delta-sigma ADCs, dither was
`
`applied but it was not removed; is that correct?
`
` A. Right. The purpose of it is, even though
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`we use the same word, dither, they are completely
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`different, so...
`
` Q. Did you design SAR ADCs where dither was
`
`applied?
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` A. I just said that, right. The 2019 one,
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`that's the one I remember most clearly, yeah.
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` Q. Did you design any delta-sigma ADCs where
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`dither was applied?
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` A. Yes.
`
` Q. Did you design delta-sigma ADCs where
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`dither was applied but not removed?
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` A. All the delta-sigma ADC, dither was not
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`removed.
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` Q. Did you design any pipelined ADCs where
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`dither was applied but not removed?
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` A. In a pipeline ADC, depending on how you
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`inject the dither, that's a place where some case
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`you would remove and some case you couldn't. I
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`can clearly picture now where dither did not need
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`to be removed.
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` Q. Why wasn't it removed in that instance?
`
` A. It was -- it was -- it was a case where
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`dither was injected at the -- just at the
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`quantizer, sub-ADC quantizer to calibrate gain
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`error.
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` So in such case, since it's not a
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`linearizing dither; it's a test signal dither
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`where I inject it, it goes to a system and it's
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`absorbed by the digital redundancy of the pipeline
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`ADC.
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` That description probably wouldn't make
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`clear sense to a non-technical person. But a
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`person who was doing pipeline ADC would know what
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`I mean by that, yeah.
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` Q. Have you ever designed an offset
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`compensation circuit for an ADC?
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` A. Yeah, we often do.
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` Q. Have you done so in connection with the
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`SAR ADC?
`
` A. No. And we often don't, also.
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` Q. Have you designed an offset compensation
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`circuit in connection with a pipelined ADC?
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` A. I'm not, you know, recalling like
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`anything specific at the moment.
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` But when we do want to compensate for
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`offset, we typically do it sometimes by like
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`trimming the differential input of an off-amp or
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`comparator is one way we often do it, or sometimes
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`by a little trim -- trimmable, like a capacitance
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`at the input or things like that, of the
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`comparator or of the amplifier.
`
` Q. In connection with the most recent SAR
`
`ADC that you designed, did you also design a
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`dither generator circuit?
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` A. Yes.
`
` Q. Can you describe it?
`
` A. It's just a -- it's a multi-level dither.
`
`It's a digital word that goes through a set of
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`capacitors. Actually, we also had a set of
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`different reference voltages to create different
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`levels.
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` Q. And that digital word controlled switches
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`in the capacitor array; is that correct?
`
` A. That's correct.
`
` Q. Dr. Moon, what is dither?
`
` A. I mean, I have said some things -- I
`
`guess I can look at my declaration. But I don't
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`have a copy other than a hard one.
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` It's used to -- it's somewhat broadly
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`used, but it's basically referring to the process
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`of adding a random signal, random noise, into a
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`converter.
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` Q. Okay. So going back, how did you inject
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`dither into your 2019 pipeline SAR ADC?
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` A. Again, I told you the different levels of
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`dither controls -- digitally controlled. That was
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`generated externally. You could build circuits to
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`do that, pseudorandom-number-generator type of
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`thing. And then that drove a set of switches that
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`configures different size capacitors or different
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`levels of reference voltages.
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` Q. And that was in the capacitor array that
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`immediately preceded the residue amplifier in that
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`design; correct?
`
` A. That's the part I can't remember exactly
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`to get into. So, you know, it could be done.
`
` Q. When did you first learn of dither?
`
` A. First learn of dither, maybe in grad
`
`school, when I was doing my Ph.D work.
`
` Q. 1980s?
`
` A. I'm not that old. My Ph.D was -- I think
`
`I got my Ph.D in '94. So probably from like 1990,
`
`1994, that time frame. Perhaps a little earlier,
`
`yeah.
`
` Q. You received your master's in electrical
`
`engineering in 1989; correct?
`
` A. Right.
`
` Q. Did you learn about dither at least as
`
`early as when you were working on your master's
`
`degree?
`
` A. Maybe. I might have heard it but not --
`
`I don't know if I really knew anything about it
`
`other than maybe hearing of it or something.
`
` Q. So do you recall hearing about dither in
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`the late 1980s?
`
` A. No, I don't recall about them at all.
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` But the reason I'm saying that is that
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`the person who was my advisor who was there for a
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`little bit and left. So I -- so I -- so I
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`actually transferred over to a different program
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`for my Ph.D.
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` Well, I was there for a master's program,
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`and that guy was known for doing some delta-sigma
`
`work. So I'm sort of thinking, maybe I did, so
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`that's about all I can say.
`
` Q. So there's the possibility, at least,
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`that by the late 1980s, you knew about the use of
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`dither in connection with delta-sigma ADCs; is
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`that correct?
`
` A. The reason that's really hard --
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` MR. LAMBSON: Objection.
`
` THE WITNESS: -- to comment because I
`
` just -- I just don't know. And the dither
`
` thing is really something that it became more
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` predominant later on when I started working
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` in delta-sigma.
`
` So, you know, there are some books out
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` there on delta-sigma; if you look at what
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` year those are, they probably have something
`
` about that.
`
` BY MR. GALLEGOS:
`
` Q. By the time you received your Ph.D in
`
`1994, you certainly knew about the application of
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`dither in the context of ADCs; correct?
`
` A. The reason I think that's likely is
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`probably because I was a little bit more well-read
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`in publications, a variety, when I was in Ph.D
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`program.
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` But that wasn't what I did. So it's
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`not -- it's not with certainty what -- I read a
`
`lot of papers as a Ph.D candidate.
`
` Q. So you wouldn't be surprised to learn
`
`that there were papers written about the use of
`
`dither in the context of ADCs; is that correct --
`
` MR. LAMBSON: Objection --
`
` Q. -- this is while you're working on your
`
`Ph.D?
`
` A. Very specifically in the context of
`
`delta-sigma modulators. That's where dither was
`
`used in the past.
`
` Q. So no later than 1994 were you aware of
`
`the use of dither in connection with any other
`
`types of ADCs?
`
` A. That, I'm pretty sure, no. Because
`
`dither, even for calibration of a pipeline ADC,
`
`didn't come about until much later.
`
` Q. So you were a professor, a teaching
`
`professor, at Oregon State University by 1998; is
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`that correct?
`
` A. That is correct.
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` Q. And you taught between 1998 and 2005; is
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`that correct?
`
` A. Yeah, I mean, I've been -- I've been
`
`teaching. I'm still here, so, yeah.
`
` Q. Did you teach ADCs in that period?
`
` A. I don't teach the analog digital
`
`converter class, but there was a time where I
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`taught the -- sort of a high kind of senior-level
`
`graduate class where you talk about a lot of
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`different things; and talk about filters, you
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`know, a variety, and that may have included some
`
`ADCs.
`
` Q. Did that include the application of
`
`dither in the context of ADCs?
`
` A. I don't think so.
`
` Q. Why don't you think so?
`
` A. Because dither was -- you know, usually
`
`you're teaching about the fundamental things, and
`
`dither is a somewhat advanced topic; it can be.
`
`It tends to be -- it tends to come later in
`
`people's research, usually.
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` Q. So in the period between 1998 and 2005,
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`were you familiar with the application of dither
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`in the context of ADCs apart from delta-sigma
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`ADCs?
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` A. Delta-sigma was the primary focus for
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`dither. When I did that pipeline gain error
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`calibration, that was the dither. It might have
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`been around that time frame. But that was for
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`gain calibration.
`
` I have a paper published on that. I
`
`can't remember the year, yeah.
`
` Q. Can you tell me the approximate year?
`
` A. I mean, all it takes is -- if you look
`
`through my publications list in front of you, if
`
`you search for "background calibration," it will
`
`come out.
`
` Q. And for that particular pipelined ADC,
`
`what type of ADC was it per stage?
`
` A. It was -- if I remember, that was -- that
`
`was 1.5-bit per stage. 1.5-bit is a pseudo 2-bit
`
`stage. I think it was a 1.5-bit pipeline. It's
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`hard to -- it's hard to even say a year. It's
`
`probably around that time.
`
` Q. What "is around that time"? What does
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`that mean?
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` A. You asked me once I came to Oregon State,
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`have I heard of dither in different things other
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`than delta-sigma between 2005 or so. So I feel
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`like I may have done that pipeline one.
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` Q. So by 2005, applying dither to a
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`converter would have been known to a person of
`
`ordinary skill in the art; correct?
`
` MR. LAMBSON: Objection to form.
`
` THE WITNESS: I wouldn't make a general
`
` statement like that.
`
` I would say by 2005, if I could -- if you
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` would tell me what year that was. By the
`
` time I did publish that, it was just getting
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` sort of the idea of using dither as test
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` signal in a pipeline was getting started,
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` whatever that year was.
`
` BY MR. GALLEGOS:
`
` Q. And for the pipelined stage that you just
`
`descr

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