United States Patent (I9|
`United States Patent 1191
`McDonald
`McDonald
`
`mi 3,879,724
`3,879,724
`l II I
`[45] Apr. 22, 1975
`l45J Apr. 22, 1975
`
`[54]
`(54)
`
`INTEGRATING ANALOG TO DIGITAL
`INTEGRATING ANALOG TO DIGITAL
`CONVERTER
`CONVERTER
`Inventor: John C. McDonald, Los Altos, Calif.
`[75]
`Inventor: John C. McDonald. Los Altos. Calif.
`[ 75]
`[73] Assignee: Vidar Corporation, Mountain View,
`(73) Assignee: Vidar Corpontion, Mountain View.
`Calif.
`Calif.
`Nov. 19, 1973
`Filed.
`[22]
`(22) Filed:
`Nov. 19, 1973
`[21] Appl. No : 417,367
`(21) Appl. No.: 417,367
`
`[52] U.S. Cl..... 340/347 AD; 328/158; 340/347 NT
`(52] U.S. Cl •..... 340/347 AD; 328/158: 340/347 NT
`[51] Int. Cl..............................................H03k 13/17
`Int. Cl ............................................ H03k 13/17
`(5 I]
`[58] Field of Search.............. 340/347 NT, 347 AD;
`(58) Field of Search ............... 340/347 NT, 347 AD;
`318/361; 328/158
`318/361; 328/158
`
`[56]
`[ 5 6 J
`
`3,241,016
`3.241,016
`3,422,424
`3,422.424
`
`References Cited
`References Cited
`UNITED STATES PATENTS
`UNITED STATES PATENTS
`3/1966 Wattson................................... 318/18
`3/1966 Wattson ................................ 318/18
`1/1969 Belct............................. 340/347 AD
`I /I 969 Be let .. .. .. ..... .. .. .......... ... 340/ 34 7 AD
`
`6/1970 Dano.............................. 340/347 AD
`3.516.085
`3,516.085
`6/1970
`Dano ............................ 340/347 AD
`3.605.001 9/1971 Toshima-ku......................... 318/631
`Toshima-ku ........................ 318/631
`3,605.001
`9/1971
`5/1972 Wheable......................... 340/347 NT
`3.665.457
`3.665.457
`5/1972
`Wheable ....................... 340/347 NT
`7/1972 Prill................................ 340/347 AD
`3.678.501
`3.678.501
`7/1972
`Prill .............................. 340/347 AD
`1/1973 Guillen et al.................. 340/347 AD
`3,710.377
`3.710,377
`1/1973
`Guillen et al. ............... 340/347 AD
`3.714.590 1/1973 Freeman et ai......................328/158
`Freeman et al.. ................... 328/158
`3.714.590
`1/1973
`3/1973 Brinkmanetai.............. 340/347 AD
`3.721.975
`Brinkman ct al. ........... 340/347 AD
`3.721.975
`3/1973
`
`Primary Examiner—Charles E. Atkinson
`Priman· £:rami11er-Charles E. Atkinson
`Assistant Examiner—Vincent J. Sunderdick
`Assis1a;11 £:ramitrer- Vincent J. Sunderdick
`Attorney, Agent, or Firm—Flehr, Hohbach, Test,
`A11or11ey, Agelll, or Firm-Flehr, Hohbach, Test,
`Albritton & Herbert
`Albritton & Herbert
`
`ABSTRACT
`[57]
`ABSTRACT
`(57)
`An integrating analog to digital converter which uti­
`An integrating analog to digital converter which uti(cid:173)
`lizes a successive approximation analog to digital con­
`lizes a successive approximation analog to digital con(cid:173)
`verter and integrates by adding a predetermined num­
`verter and integrates by adding a predetermined num(cid:173)
`ber of approximations and averages the sum.
`ber of approximations and averages the sum.
`9 Claims, 3 Drawing Figures
`9 Claims, 3 Drawing Figures
`
`OFFSET
`
`17
`1
`
`I
`
`r---~~~~~•~~L~e
`r--- ----------,
`i
`I , - - - - . :
`22
`I
`
`DIT ER
`
`I
`I
`I
`I
`
`H SPEED
`CONVERTER
`
`VERT MSB
`
`DIGITAL OUTPUT
`MSB TO LSB
`
`START
`
`n
`n.1om
`Where
`ffl•l.2,3, M
`etc.
`
`51
`, - - - - - -T 'V
`
`LINE
`VOLTAGE
`
`SYNC
`TllollNG
`
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`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

`PATENTEDAPR22I975
`PATENTED APR 2 21975
`
`3,879,724
`3,879,724
`
`SHEET 1 OF 2
`SHEET 1 OF 2
`
`17
`I
`OFFSET
`AMPLIFIER J
`
`DIT ER
`DITHER
`
`II
`
`ANALOG
`INPUT
`
`COMPARE
`” ATOR
`274/
`
`26
`
`D/A
`CONVERTER
`1 Is'-J
`
`—oVREF
`
`SUCCESSIVE ,
`APPROXIMATION i
`A/D CONVERTER I
`
`CONTROL
`LOGIC
`
`I T
`’__ I
`
`41
`
`FULL
`FULL
`ADDER
`ADDER
`o-—
`MODE
`MODE.._.___. _ _.
`
`REGISTEREE
`
`INTEGRATING
`INTEGRATING
`A/D CONVERTER
`A/D CONVERTER
`V
`MODE
`
`J_59
`
`SELECTOR
`
`DIGITAL
`DIGITAL
`OUTPUT
`OUTPUT
`
`h
`
`48
`48
`
`SHIFT
`REGISTER
`
`36
`~
`
`----(cid:173)
`
`37
`HIGH SPEED
`HIGH SPEED
`A/ D CONVERTER
`A/D CONVERTER
`38
`
`INVERT MSB
`INVERT MSB
`33
`
`-e---------------
`DIGITAL O.UTPUT
`DIGITAL OUTPUT
`MSB TO LSB
`MSB TO LSB
`
`START
`START
`
`FIG. 1
`FIG. 1
`
`CONVERSION
`CONVERSION
`COUNTER
`COUNTER
`
`fn
`
`44^
`STARTo
`STc,;..AR;.;...T"---i
`
`n
`n = iom
`n:1om
`where
`where
`m=l,2,3,
`ffl=l,2,3, MOOE
`MODE
`etc.
`etc.
`
`SHIFT
`SHIFT
`REGISTER
`REGISTER
`Preset
`RESET
`^43
`43
`
`CONVERT
`CONVERT
`LOGIC
`LOGIC
`
`I
`
`51
`---..J.-..--U-51
`rtx
`
`LINE o.
`LINE o---◄
`VOLTAGE
`VOLTAGE
`
`SYNC
`TIMING
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 2
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

`PATENTED APR 2 21975
`
`3,879.724
`3,879,724
`
`SHEET 2 Of 2
`SHEET 2 OF 2
`- .
`
`e
`f
`
`a At
`
`- t
`
`FIG.2
`
`e
`e6
`es
`e4
`
`.6e=LSB-{ea
`e2
`e1
`
`Ein
`
`_.
`
`FIG.3
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 3
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

`5
`5
`
`10
`
`3,879,724
`3,879,724
`
`1
`1
`INTEGRATING ANALOG TO DIGITAL
`CONVERTER
`INTEGRATING ANALOG TO DIGITAL
`CONVERTER
`
`2
`2
`are added. Means are provided for dividing the sum of
`are added. Means are provided for dividing the sum of
`the additions by the number of conversions to provide
`the additions by the number of conversions to provide
`an integrated digital output representative of the ana­
`an integrated digital output representative of the ana(cid:173)
`log input signal.
`log input signal.
`BACKGROUND OF THE INVENTION
`BACKGROUND OF THE INVENTION
`BRIEF DESCRIPTION OF THE DRAWINGS
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention is directed to an integrating
`The present invention is directed to an integrating
`FIG. 1 is a block diagram of an A/D converter em­
`analog to digital (A/D) converter.
`analog to digital (A/D) converter.
`FIG. I is a block diagram of an A/D converter em(cid:173)
`bodying the present invention;
`Prior analog to digital conversion techniques can be
`bodying the present invention;
`Prior analog to digital conversion techniques can be
`conveniently classified into two groups; namely, inte­
`FIG. 2 is a waveform useful in understanding the in­
`FIG. 2 is a waveform useful in understanding the in-
`conveniently classified into two groups; namely, inte(cid:173)
`grating and instantaneous.
`vention; and
`grating and instantaneous.
`10 vention; and
`FIG. 3 is a graph useful in understanding a particular
`Integrating A/D converters include a VCO (voltage
`FIG. 3 is a graph useful in understanding a particular
`Integrating A/D converters include a VCO (voltage
`controlled oscillator) with counter and the dual slope
`aspect of the invention.
`controlled oscillator) with counter and the dual slope
`aspect of the invention.
`techniques. Both provide normal mode integration by
`techniques. Both provide normal mode integration by
`DETAILED DESCRIPTION OF THE PREFERRED
`DETAILED DESCRIPTION OF THE PREFERRED
`measuring a voltage over a predetermined period of
`measuring a voltage over a predetermined period of
`EMBODIMENT
`EMBODIMENT
`time to determine its average value. This technique 15
`time to determine its average value. This technique 15
`causes the average voltage to be read in the presence
`Referring now to FIG. 1, an analog input voltage
`causes the average voltage to be read in the presence
`Referring now to FIG. I, an analog input voltage
`of noise. The VCO technique tends to drift and, in ad­
`waveform is applied across terminals 11 to a differen­
`of noise. The VCO technique tends to drift and, in ad(cid:173)
`waveform is applied across terminals 11 to a differen(cid:173)
`tial amplifier 12. The output voltage of amplifier 12 is
`dition, a precision oscillator is required to gate the
`dition, a precision oscillator is required to gate the
`tial amplifier 12. The output voltage of amplifier 12 is
`VCO to the counter. Thus, it is relatively costly. How­
`offset by means of a negative voltage source designated
`VCO to the counter. Thus, it is relatively costly. How(cid:173)
`offset by means of a negative voltage source designated
`ever, the speed of this type of A/D converter is faster 20
`—V which is coupled to a feedback network including
`ever, the speed of this type of A/D converter is faster
`20 -V which is coupled to a feedback network including
`than the second or dual slope type converter. In the
`resistors 13, 14, referenced to common, and a resistor
`resistors 13, 14, referenced to common, and a resistor
`than the second or dual slope type converter. In the
`dual slope technique, the unknown voltage generates
`16 which couples the negative voltage source to the
`16 which couples the negative voltage source to the
`dual slope technique, the unknown voltage generates
`one slope and the reference voltage generates a second
`feedback network. The combination of the feedback
`one slope and the reference voltage generates a second
`feedback network. The combination of the feedback
`slope with a counter measuring the total time of the ref­
`network 13, 14 and 16 and the amplifier 12 constitutes
`network 13, 14 and 16 and the amplifier 12 constitutes
`slope with a counter measuring the total time of the ref(cid:173)
`an offset amplifier 17. Such amplifier provides an out­
`erence slope. The dual slope technique provides nor- 25
`erence slope. The dual slope technique provides nor- 25
`an offset amplifier 17. Such amplifier provides an out(cid:173)
`mal mode integration and stability at low cost but at the
`put on line 18 of a single voltage polarity or a unipolar
`mal mode integration and stability at low cost but at the
`put on line 18 of a single voltage polarity or a unipolar
`expense of speed.
`output where the analog input is bipolar.
`expense of speed.
`output where the analog input is bipolar.
`The unipolar output on line 18 is coupled to a sample
`Instantaneous A/D converters, of course, by defini­
`Instantaneous A/D converters, of course, by defini(cid:173)
`The unipolar output on line 18 is coupled to a sample
`tion offer no integration of the analog input waveform.
`and hold network 19. This sample and hold network 19
`and hold network 19. This sample and hold network 19
`tion offer no integration of the analog input waveform.
`is coupled to the input of a successive approximation
`The digital output is representative of input voltage at 3θ
`The digital output is representative of input voltage at 30
`is coupled to the input of a successive approximation
`A/D converter indicated by dashed block 21. Such A/D
`a given instant of time. Converters include the servo
`AID converter indicated by dashed block 21. Such A/D
`a given instant of time. Converters include the servo
`type where an UP/DOWN counter is utilized, the ramp
`converter may be of standard configuration. One type
`converter may be of standard configuration. One type
`type where an UP/DOWN counter is utilized, the ramp
`acceptable for use in the embodiment of the present in­
`type where the time is measured from the beginning of
`type where the time is measured from the beginning of
`acceptable for use in the embodiment of the present in(cid:173)
`vention is sold under the trademark REDCOR model
`the ramp to the time at which the ramp voltage equals
`vention is sold under the trademark REDCOR model
`the ramp to the time at which the ramp voltage equals
`663. Such a converter comprises a comparator 22 to
`the input voltage, and lastly the successive approxima- 35
`the input voltage, and lastly the successive approxima- 35
`663. Such a converter comprises a comparator 22 to
`which the analog input signal is coupled along with the
`tion A/D converter. The latter uses a digital to analog
`tion AID converter. The latter uses a digital to analog
`which the analog input signal is coupled along with the
`D/A converter 26 output 27. The difference between
`converter which provides an analog output signal
`DIA converter 26 output 27. The difference between
`converter which provides an analog output signal
`these voltages is coupled to a feedback loop including
`which is compared with the analog input signal. By suc­
`these voltages is coupled to a feedback loop including
`which is compared with the analog input signal. By suc(cid:173)
`a control logic unit 23. The digital output of the control
`cessive approximation starting at the most significant
`a control logic unit 23. The digital output of the control
`cessive approximation starting at the most significant
`bit (MSB) the digital to analog converter is caused to 40
`logic unit 23 is coupled by lines 25 to digital to analog
`bit ( MSB) the digital to analog converter is caused to 40
`logic unit 23 is coupled by lines 25 to digital to analog
`converter 26. The analog voltage on line 27 is derived
`produce an analog signal equal in magnitude to the
`converter 26. The analog voltage on line 27 is derived
`produce an analog signal equal in magnitude to the
`from VBef· as controlled by digital lines 25. In this man­
`input analog signal. Such a converter is fast and very
`from V REF as controlled by digital lines 25. In this man(cid:173)
`input analog signal. Such a converter is fast and very
`ner, control logic unit 23 produces a digital output
`accurate.
`ner, control logic unit 23 produces a digital output
`accurate.
`value in a successive approximation manner which ap­
`value in a successive approximation manner which ap(cid:173)
`OBJECTS AND SUMMARY OF THE INVENTION 45
`OBJECTS AND SUMMARY OF THE INVENTION 45
`proaches the analog input to comparator 22. Such digi­
`proaches the analog input to comparator 22. Such digi(cid:173)
`tal output at 24 is a succession of binary bits starting
`It is a general object of the present invention to pro­
`tal output at 24 is a succession of binary bits starting
`It is a general object of the present invention to pro(cid:173)
`with the most significant bit (MSB) down to a least sig­
`vide an A/D converter which provides alternatively in­
`with the most significant bit ( MSB) down to a least sig(cid:173)
`vide an A/D converter which provides alternatively in(cid:173)
`nificant bit (LSB). Each analog to digital conversion by
`stantaneous and integrating operation.
`nificant bit ( LSB ). Each analog to digital conversion by
`stantaneous and integrating operation.
`the successive approximation converter 21 is initiated
`It is another object of the invention to provide an
`the successive approximation converter 21 is initiated
`It is another object of the invention to provide an
`through a start winding 28 coupled to control logic unit
`50 through a start winding 28 coupled to control logic unit
`A/D converter as above which is temperature stable.
`AID converter as above which is temperature stable.
`23.
`It is another object of the invention to provide an
`23.
`ft is another object of the invention to provide an
`Both offset amplifier 17 and the successive approxi­
`A/D converter as above which is largely digital in con­
`Both offset amplifier 17 and the successive approxi(cid:173)
`AID converter as above which is largely digital in con(cid:173)
`mation A/D converter 21 are isolated from the remain­
`struction.
`mation A/D converter 21 are isolated from the remain-
`struction.
`der of the circuitry by a guard shield 29. The digital
`It is another object of the invention to provide an $$
`55 der of the circuitry by a guard shield 29. The digital
`It is another object of the invention to provide an
`output of winding 24 is coupled to a secondary winding
`A/D converter as above which has common mode re­
`output of winding 24 is coupled to a secondary winding
`AID converter as above which has common mode re(cid:173)
`31 to thus transformer couple through the guard shield
`jection without the use of a differential amplifier.
`31 to thus transformer couple through the guard shield
`jection without the use of a differential amplifier.
`circuit to the remaining circuitry; the start winding 28
`It is another object of the invention to provide an in­
`circuit to the remaining circuitry; the start winding 28
`It is another object of the invention to provide an in(cid:173)
`is similarly coupled through the guard shield to a pri­
`tegrating A/D converter which easily accommodates
`is similarly coupled through the guard shield to a pri-
`tegrating AID converter which easily accommodates
`mary winding 32. Such shielding provides for common
`analog input signals of either + or — polarity.
`60 mary winding 32. Such shielding provides for common
`analog input signals of either+ or - polarity.
`mode noise reduction.
`In accordance with the above objects an integrating
`mode noise reduction.
`In accordance with the above objects an integrating
`Comparator 22 of the converter 21 includes an input
`analog to digital converter is provided comprising ana­
`Comparator 22 of the converter 21 includes an input
`analog to digital converter is provided comprising ana(cid:173)
`designated “dither.” This is necessary for providing en­
`log to digital (A/D) converting means to provide a sub­
`designated "dither." This is necessary for providing en(cid:173)
`log to digital (A/D) converting means to provide a sub(cid:173)
`hanced resolution of the overall integrating A/D con­
`stantially instantaneous digital output signal indicative
`hanced resolution of the overall integrating AID con-
`stantially instantaneous digital output signal indicative
`verter which will be described below.
`of the instantaneous amplitude of an analog input sig-
`65 verter which will be described below.
`of the instantaneous amplitude of an analog input sig(cid:173)
`The instantaneous digital output of converter 21 is
`nal. Means are coupled to the converting means for ini­
`The instantaneous digital output of converter 21 is
`nal. Means are coupled to the converting means for ini(cid:173)
`coupled through the transformer constituting windings
`tiating successive A/D conversions. The digital outputs
`coupled through the transformer constituting windings
`tiating successive AID conversions. The digital outputs
`24 and 31 to a shift register 33. As discussed above, this
`of a predetermined number of successive conversions
`24 and 31 to a shift register 33. As discussed above, this
`of a predetermined number of successive conversions
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 4
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

`3,879,724
`3,879,724
`
`3
`3
`is a serial train of binary information with the most sig­
`is a serial train of binary information with the most sig(cid:173)
`nificant bit being the first bit and the least significant
`nificant bit being the first bit and the least significant
`bit the last bit. When register 33 is filled, a conversion
`bit the last bit. When register 33 is filled, a conversion
`counter unit 34 recognizes that the successive approxi­
`counter unit 34 recognizes that the successive approxi(cid:173)
`mation converter has completed its function in provid­
`mation converter has completed its function in provid(cid:173)
`ing an instantaneous digital indication of the instanta­
`ing an instantaneous digital indication of the instanta(cid:173)
`neous amplitude of the analog input at terminals 11.
`neous amplitude of the analog input at terminals 11.
`After one conversion, the contents of shift register 33
`After one conversion, the contents of shift register 33
`are transferred via multiple lines 36 into a shift register
`are transferred via multiple lines 36 into a shift register
`37. The line containing the most significant bit, how­
`37. The line containing the most significant bit, how(cid:173)
`ever, includes an inverter 38 which inverts this bit when
`ever, includes an inverter 38 which inverts this bit when
`the total digital output from the converter 21 is shifted
`the total digital output from the converter 21 is shifted
`into shift register 37. The purpose of the inverter is to
`into shift register 37. The purpose of the inverter is to
`convert the digital output of converter 21 to a true
`convert the digital output of converter 21 to a true
`two’s complement number. A typical successive ap­
`two's complement number. A typical successive ap(cid:173)
`proximation analog to digital converter with an offset
`proximation analog to digital converter with an offset
`input voltage equal to the full scale voltage will indicate
`input voltage equal to the full scale voltage will indicate
`a negative input or negative full scale input in a two’s
`a negative input or negative full scale input in a two's
`complement binary form with the exception that the
`complement binary form with the exception that the
`most significant bit, MSB, is inverted. Therefore, to
`most significant bit, MSB, is inverted. Therefore, to
`provide a true two’s complement for negative input
`provide a true two's complement for negative input
`voltages, this bit must be inverted. From an absolute
`voltages, this bit must be inverted. From an absolute
`standpoint, of course, the successive approximation
`standpoint, of course, the successive approximation
`A/D converter 21 receives only positive inputs because
`A/D converter 21 receives only positive inputs because
`of the offset amplifier 17.
`of the offset amplifier 17.
`TABLE I
`TABLE I
`
`01
`
`0
`I
`I
`
`11
`
`0
`0
`
`INPUT VOLTAGE
`INPUT VOLT AGE
`
`01
`
`1!
`
`11
`
`0
`0
`
`-FULL SCALE
`-FULL SCALE
`
`4
`4
`In the preferred embodiment of the invention a bi­
`In the preferred embodiment of the invention a bi(cid:173)
`nary coded decimal or BCD format is used where the
`nary coded decimal or BCD format is used where the
`total number of conversions n is equal to IO1" where m
`total number of conversions n is equal to I om where m
`is an integer. Thus, by definition, division is accom-
`is an integer. Thus, by definition, division is accom-
`5 plished merely by truncation or a shifting of the “deci­
`5 plished merely by truncation or a shifting of the "deci(cid:173)
`mal” or base point. Thus, conversion counter 34 by
`mal" or base point. Thus, conversion counter 34 by
`means of line 48 supplies the quantity m to divider 46
`means of line 48 supplies the quantity m to divider 46
`to shift the decimal point m number of times. From a
`to shift the decimal point m number of times. From a
`more general standpoint, if a general binary radix were
`more general standpoint, if a general binary radix were
`10 desired, then the number of conversions, n, should be
`10 desired, then the number of conversions, n, should be
`made equal to n, should be made equal to B" where m
`made equal ton, should be made equal to B'" where m
`is still an integer and B is the radix.
`is still an integer and B is the radix.
`Where merely the instantaneous or high speed A/D
`Where merely the instantaneous or high speed AID
`conversion of an analog input is desired, the device of
`conversion of an analog input is desired, the device of
`15 the present invention may function in that mode. Here
`15 the present invention may function in that mode. Here
`selector unit 49 which is coupled to both the output of
`selector unit 49 which is coupled to both the output of
`shift register 37 and 46 would select register 37 which
`shift register 37 and 46 would select register 37 which
`contains the successive approximation A/D converter
`contains the successive approximation A/D converter
`digital output 21. The convert logic 43 would, of
`digital output 21. The convert logic 43 would, of
`20 course, only make a single conversion and adder 41
`20 course, only make a single conversion and adder 41
`would not function.
`would not function.
`In the integrating A/D conversion mode, all compo­
`In the integrating A/D conversion mode, all compo(cid:173)
`nents function including a sync timing unit 51 which is
`nents function including a sync timing unit 51 which is
`either coupled to a 60 cycle ac line voltage or is driven
`either coupled to a 60 cycle ac line voltage or is driven
`25 by a crystal oscillator unit. For an effective integrating
`25 by a crystal oscillator unit. For an effective integrating
`output it is necessary that the conversions are made cy­
`output it is necessary that the conversions are made cy(cid:173)
`clically; in other words, that the samples of the wave­
`clically; in other words, that the samples of the wave(cid:173)
`form at input terminals 11 are equally spaced. Thus,
`form at input terminals 11 are equally spaced. Thus,
`DIGITAL REPRESENTATION
`DIGITAL REPRESENTATION
`sync timing unit 51 is coupled to conversion logic unit
`sync timing unit 51 is coupled to conversion logic unit
`L.SB
`MSB
`LSB
`MSB
`3θ 43 to inhibit a start indication to converter 21 after
`- - - - - - - - - - - - - - - - - - - - - - - 30 43 to inhibit a start indication to converter 21 after
`+ FULL SCALE
`I
`1
`1
`1
`1
`1
`1
`1
`0
`1
`+ FULL SCALE
`I
`0
`conversion has taken place until the next proper
`conversion has taken place until the next proper
`1
`0
`I
`0
`equally spaced time interval.
`1
`0
`equally spaced time interval.
`I
`0
`0
`0
`0
`In general, it has been found that for the integrating
`0
`In general, it has been found that for the integrating
`1
`0
`I
`0
`analog to digital converter of the present invention to
`analog to digital converter of the present invention to
`0
`0
`35 provide an integrated output which is identically equal
`I
`I
`35 provide an integrated output which is identically equal
`I
`0
`to the integral of the voltage given by a voltage con­
`to the integral of the voltage given by a voltage con(cid:173)
`I
`trolled oscillator (VCO) and associated counter, a
`I
`trolled oscillator ( VCO) and associated counter, a
`I
`large number of samples must be provided which are
`large number of samples must be provided which are
`equally spaced.
`equally spaced.
`40 Proof of this is as follows: Assume an input analog
`40
`Proof of this is as follows: Assume an input analog
`voltage waveform as shown in FIG. 2 where the ampli­
`voltage waveform as shown in FIG. 2 where the ampli(cid:173)
`tude of the waveform is given as e and integration is to
`tude of the waveform is given as e and integration is to
`be accomplished from time a to time b.
`be accomplished from time a to time b.
`VCO CASE
`VCO CASE
`The VCO transfer function is
`The VCO transfer function is
`f = ke pulses/second (1)
`f = ke pulses/second ( I )
`In an incremental time A(t,/is constant since e does not
`In an incremental time /1 1t,f is constant since e does not
`change during this time. The number of pulses occuring
`change during this time. The number of pulses occuring
`during this time is The total pulses during the in­
`during this time is f,11,t. The total pulses during the in(cid:173)
`terval a to ft is
`terval a to b is
`
`01
`
`10
`
`1
`I
`0
`0
`0
`I
`I
`0
`0
`
`01
`
`0
`0
`0
`0
`0
`I
`I
`
`01
`
`11
`
`0
`0
`0
`0
`0
`I
`I
`
`01
`
`11
`
`0
`0
`
`0
`0
`
`0
`0
`
`0
`0
`
`0
`0
`
`0
`0
`I
`I
`
`i1
`
`0
`0
`
`01
`
`0
`I
`I
`
`I1
`
`01
`
`0
`I
`I
`
`11
`
`0
`0
`
`0
`0
`
`01
`0
`1
`I
`I
`
`0
`0
`
`More specifically, the contents of shift register 37
`More specifically, the contents of shift register 37
`while providing an instantaneous A/D conversion indi­
`while providing an instantaneous A/D conversion indi(cid:173)
`cation of the instantaneous amplitude of the analog
`cation of the instantaneous amplitude of the analog
`input signal, also allows an integrating A/D conversion
`input signal, also allows an integrating AID conversion
`mode. This is accomplished by adding the contents of
`mode. This is accomplished by adding the contents of 45
`45
`a shift register 39 to register 37 by a full adder 41. Shift
`a shift register 39 to register 37 by a full adder 41. Shift
`register 39 contains the binary running sum of the in­
`register 39 contains the binary running sum of the in(cid:173)
`stantaneous readings loaded into shift register 37.
`stantaneous readings loaded into shift register 37.
`Thus, the full adder 41 in combination with the shift
`Thus, the full adder 41 in combination with the shift
`register 37 and 39 constitute means for adding the digi­
`register 37 and 39 constitute means for adding the digi- 50
`tal output of a predetermined number of successive
`ta! output of a predetermined number of successive
`conversions. This predetermined number is determined
`conversions. This predetermined number is determined
`by conversion counter 34 where the number is deter­
`n
`by conversion counter 34 where the number is deter-
`n
`mined by its n input. Conversion counter 34 is coupled
`Total pulses = lim Σ fj Ai t
`mined by its n input. Conversion counter 34 is coupled
`Total pulses
`r
`lim
`to a convert logic unit 43 by a line 44. The counter 34
`n-+“> o
`5d
`to a convert logic unit 43 by a line 44. The counter 34 5:i
`n+oo
`0
`causes logic unit 43 to give start indications through
`causes logic unit 43 to give start indications through
`transformer 32, 28 to the successive approximation
`transformer 32, 28 to the successive approximation
`However, from integral calculus this is identically
`A/D converter 21 after each conversion is completed
`However, from integral calculus this is identically
`AID converter 21 after each conversion is completed
`up to n number of conversions. At this time the integra­
`up ton number of conversions. At this time the integra(cid:173)
`b
`tion has been completed and the divider unit 46 cou­
`6C Total Pulses =
`tion has been completed and the divider unit 46 cou- 61'
`b
`pled to shift register 39 contains the sum of the prede­
`f a
`pied to shift register 39 contains the sum of the prede-
`f
`termined number, n, of analog to digital conversions
`termined number, n, of analog to digital conversions
`a
`performed by successive approximation converter 21.
`performed by successive approximation converter 21.
`If the sum is now divided by n, the number of conver­
`If the sum is now divided by n, the number of conver(cid:173)
`sions made, the output on lines 47 will be the integrated
`65
`sions made, the output on lines 47 will be the integrated 65
`value of the analog input waveform on terminals 11 in
`value of the analog input waveform on terminals 11 in
`digital output format over the period of the n conver­
`digital output format over the period of the n conver-
`sions.
`sions.
`
`Total Pulses
`
`f dt
`f dt
`
`Substituting for f
`Substituting for .f
`
`Total pulses =
`Total pulses=
`
`k
`k
`
`b
`b
`/
`J
`a
`a
`
`e dt
`e dt
`
`(2)
`(2)
`
`(3)
`(3)
`
`(4)
`(4)
`
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. Exhibit 1027 Page 5
`Xilinx, Inc. and Xilinx Asia Pacific Pte. Ltd. v. Analog Devices, Inc. IPR2020-01559
`
`

`

`3,879,724
`3,879,724
`
`5
`5
`Therefore, if the frequency of the VCO is sufficiently
`Therefore, if the frequency of the VCO is sufficiently
`high so that the instantaneous frequency follows the
`high so that the instantaneous frequency follows the
`input waveform, the total pulses accumulated in a
`input waveform, the total pulses accumulated in a
`counter is equal to a constant times the integral of the
`counter is equal to a constant times the integral of the
`input voltage over the interval a to b.
`input voltage over the interval a to b.
`PRESENT INVENTION
`PRESENT INVENTION
`Assume that instantaneous samples of amplitude
`Assume that instantaneous samples of amplitude e1
`are taken of the input voltage, e1B. Then the following
`are taken of the input voltage, e, •. Then the following
`mathematical operation is taken giving
`mathematical operation is taken giving
`
`10
`
`6
`6
`LSB/2. If Etn continues to increase, the output remains
`LSB/2. If E,. continues to increase, the output remains
`constant until the input exceeds 1.5 times LSB. Thus,
`constant until the input exceeds l.S times LSD. Thus,
`from inspection, the maximum resolution is +LSB/2.
`from inspection, the maximum resolution is +LSB/2.
`It will now be shown by example that the output of
`It will now be shown by example that the output of
`5
`divider 46 will contain greater resolution and therefore
`5 divider 46 will contain greater resolution and therefore
`greater accuracy if Gaussian noise is a dither to the
`greater accuracy if Gaussian noise is a dither to the
`input voltage and the output mathematical function is
`input voltage and the output mathematical function is
`calculated as done in the present invention.
`calculated as done in the present invention.
`EXAMPLE
`EXAMPLE
`As illustrated in FIG. 3, Gaussian noise having an en­
`As illustrated in FIG. 3, Gaussian noise having an en(cid:173)
`velope 51 is added to the input voltage. So that each bit
`velope 51 is added to the input voltage. So that each bit
`in the successive approximation is dependent on the
`. in the successive approximation is dependent on the
`previous bit, the input signal is sampled and held by
`previous bit, the input signal is sampled and held by
`unit 19 as shown in FIG. 1. If t