IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
`
`739
`
`500-MS/s 5-bit ADC in 65-nm CMOS With Split
`Capacitor Array DAC
`
`Brian P. Ginsburg, Student Member, IEEE, and Anantha P. Chandrakasan, Fellow, IEEE
`
`Abstract—A 500-MS/s 5-bit ADC for UWB applications has been
`fabricated in a 65-nm CMOS technology using no analog-specific
`processing options. The time-interleaved successive approximation
`register (SAR) architecture has been chosen due to its simplicity
`versus flash and its amenability to scaled technologies versus
`pipelined, which relies on operational amplifiers. Six time-in-
`terleaved channels are used, sharing a single clock operating at
`the composite sampling rate. Each channel has a split capacitor
`array that reduces switching energy, increases speed, and has
`similar INL and decreased DNL, as compared to a conventional
`binary-weighted array. A variable delay line adjusts the instant of
`latch strobing to reduce preamplifier currents. The ADC achieves
`Nyquist performance, with an SNDR of 27.8 and 26.1 dB for
`3.3 and 239 MHz inputs, respectively. The total active area is
`0.9 mm2, and the ADC consumes 6 mW from a 1.2-V supply.
`Index Terms—ADC, analog-to-digital conversion, deep-submi-
`cron CMOS, successive approximation register, ultra-wideband
`radio.
`
`I. INTRODUCTION
`
`ULTRA-WIDEBAND (UWB) radio is an emerging tech-
`
`nology for very-high-data-rate, short distance wireless
`communications. Both OFDM [1] and pulse-based [2] solu-
`tions are being developed to achieve data rates in excess of
`480 Mb/s. UWB receivers require high-speed but low-reso-
`lution analog-to-digital converters (ADCs), in the range of
`4–5 bits [3]–[5]. The ADC in this work is targeted for specifi-
`cations (5 bit, 500 MS/s) compatible with a custom pulse-based
`UWB transceiver [6], [7], where 100 Mb/s communication
`is achieved using BPSK-modulated 500-MHz-wide Gaussian
`pulses transmitted in one of 14 bands between 3.1–10.6 GHz.
`The flash topology, along with its interpolating and folding
`variants, has been the conventional choice for high-speed, low-
`resolution ADCs [8]–[12]. While flash can maintain the highest
`throughput, it requires an exponential growth in the number of
`comparisons with the resolution. The ensuing complexity moti-
`vates the use of other architectures.
`Pipelined ADCs are used for high-speed, medium-resolution
`applications [13], [14]. They can provide one conversion per
`clock period throughput and only a linear scaling in complexity
`with resolution; however, they rely on operational amplifiers at
`the heart of the multiplying digital-to-analog converter (MDAC)
`in each pipelined stage. Because it must be closed loop stable,
`
`Manuscript received August 25, 2006; revised December 19, 2006. This work
`was supported by the Defense Advanced Research Projects Agency (DARPA)
`and a National Defense Science and Engineering Graduate (NDSEG) Fellow-
`ship.
`The authors are with the Massachusetts Institute of Technology, Cambridge,
`MA 02139 USA (e-mail: bginzz@mit.edu).
`Digital Object Identifier 10.1109/JSSC.2007.892169
`
`this amplifier typically uses one or two high gain stages. Un-
`fortunately, in deep-submicron CMOS, the achievable gain per
`stage is limited because short-channel effects lower
`for
`a single transistor, and reduced voltage supplies restrict circuit
`techniques such as cascoding. Thus, there are significant chal-
`lenges for continued scaling of pipelined ADCs.
`Very recently, for the high-speed, low resolution converters
`necessary for UWB, the time-interleaved successive approxima-
`tion register (SAR) architecture has re-emerged1 as a low-power
`alternative to flash and pipelined ADCs [17]. At the required
`speeds, their major limitation is digital power; a SAR converter
`includes digital feedback in the critical path. A full custom logic
`controller with dynamic registers can reduce digital power sig-
`nificantly, but it still remains a dominant source of power con-
`sumption in a 0.18- m CMOS implementation [18]. Another
`approach uses dynamic registers with asynchronous operation
`to reduce clock power, and combined with a non-binary suc-
`cessive approximation algorithm, has led to a very energy ef-
`ficient design in 0.13- m CMOS [19]. Fortunately, technology
`scaling improves the digital power and speed without many of
`the issues plaguing pipelined converters. The only active analog
`component in a SAR ADC, the comparator, still requires large
`gain and bandwidth, but because it does not have to be linear,
`this gain can be achieved through cascaded stages and positive
`feedback.
`This paper presents a 500-MS/s 5-bit ADC fabricated in a
`65-nm CMOS technology [20]. At the maximum sampling rate,
`the ADC consumes 6 mW from a 1.2-V supply. This low power
`consumption is achieved through proper architecture selection,
`a new capacitor array, and careful timing allocation between the
`digital and analog circuits. The ADC has six time-interleaved
`SAR channels synchronized to a common clock. The split ca-
`pacitor array reduces switching energy, is robust to digital delay
`mismatches for overall improved settling time, and has a re-
`duction in peak static differential nonlinearity (DNL). In the
`comparator, a variable delay line adjusts the instant of strobing
`for the regenerative latches, minimizing idle time during each
`bit-cycle without sacrificing bit error rate (BER) performance.
`
`II. ADC ARCHITECTURE
`A SAR ADC requires one period for sampling and periods
`to resolve the
`digital output bits. To make the internal SAR
`clock synchronous to the overall sampling clock, six time-inter-
`leaved channels are used, as shown in Fig. 1. Thus, only a single
`500 MHz clock is required in the prototype, easing clock gen-
`eration and distribution. The channels synchronize by passing
`
`1Time-interleaved SAR was used as early as 1980 as a low area alternative
`to the flash ADC [15], and, more recently, for reduced comparator power in a
`medium resolution application [16].
`
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`
`0018-9200/$25.00 © 2007 IEEE
`
`Xilinx v. Analog
`IPR2020-01559
`Analog 2007
`
`

`

`740
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
`
`between the input and current digital estimate. The conventional
`DAC choice is a binary-weighted capacitor array [22], as
`shown in Fig. 3, which is insensitive to stray capacitance.
`As shown in [23], however, the conventional capacitor array
`uses charge inefficiently during a conversion. To demonstrate
`this, a conversion of a 2-bit capacitor array is presented here.
`During the first bit decision after sampling, the MSB capacitor
`with the remaining capacitors connected
`is connected to
`to ground (left circuit in Fig. 4). The output of the capacitor
`, is
`array,
`
`(1)
`
`is the input voltage sampled on the capacitor array
`where
`is the reference voltage. During the second bit-cycle,
`and
`, an “up” tran-
`the SAR does one of two transitions. If
`sition is performed, where
`is switched from ground up to
`, drawing
`
`Fig. 1. Top-level block diagram of the 6-way time-interleaved ADC.
`
`(2)
`
`, a
`from the reference voltage supply. Inversely, if
`switch
`and
`“down” transition is performed (Fig. 4);
`places. If they switch at the same time, the energy required is
`
`(3)
`
`than to raise it; this
`It takes 5 times more energy to lower
`is discharged to
`occurs because all of the charge initially on
`ground, and all the charge that ends up on
`must be delivered
`from the reference voltage supply.
`Ref. [23] analyzes three alternatives to the conventional ca-
`pacitor array and switching procedure. Of these alternatives, this
`work implements the split capacitor array because it has both
`the lowest switching energy and does not require an extra clock
`phase that would limit high speed operation. A -bit split capac-
`itor array is shown in Fig. 5; the MSB capacitor of the conven-
`tional array has been split into an identical copy (MSB subarray)
`of the rest of the array (main subarray). These arrays are placed
`in parallel (common top plate), not to be confused with the series
`connected capacitor arrays used in the sub-DAC approach.2 The
`, identical to
`total capacitance of the split capacitor array is
`the conventional case, and the area requirements are unchanged.
`The split capacitor switching algorithm is presented in Fig. 6.
`Here, the two-bit example from above is repeated for the split
`capacitor array to demonstrate the switching method and en-
`ergy savings. During the first bit-cycle (left side of Fig. 7), the
`and
`, is connected to
`, and the
`MSB subarray,
`,
`main subarray is connected to ground. Since
`(1) also represents the output of the split array. In the case of
`an “up” transition, the array transitions in the same method as
`switching to
`, consuming the same energy
`above, with
`calculated in (2). In the “down” transition (Fig. 7), half of the
`is lowered to ground, leaving both
`and
`MSB subarray,
`unchanged. By only switching one capacitor the energy
`
`2Historically, the combination of capacitive main- and sub-DACs had been
`called a “split array” [15], but this has not become common usage, and we have
`co-opted the term for the new structure.
`
`Fig. 2. Block diagram of the channel, which has a capacitive DAC, comparator,
`and digital logic.
`
`a token to cue their start of sampling, and all critical sampling
`edges are aligned to the same shared clock [18]. Timing skew
`between channels is thus limited to routing variations to the
`channels and the delay mismatch through a single register in
`each channel; both of these error sources can be kept suffi-
`ciently small such that digital timing correction (a complex,
`power hungry process [21]) is not necessary.
`The channel, shown in Fig. 2, consists of a capacitive dig-
`ital-to-analog converter (DAC), a comparator, and control logic
`(itself called the SAR). The control logic switches the DAC
`using a binary search algorithm to minimize the error between
`the digital output and the analog input. The split capacitor
`array and comparator, the two analog blocks, are discussed in
`Section III, followed by some of the considerations used in
`designing circuits for 65-nm CMOS.
`
`III. CIRCUIT DESIGN
`
`A. Split Capacitor Array
`it
`The DAC serves two purposes in a SAR converter:
`samples the input charge, and it generates an error voltage
`
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`

`GINSBURG AND CHANDRAKASAN: 500-MS/s 5-bit ADC IN 65-nm CMOS WITH SPLIT CAPACITOR ARRAY DAC
`
`741
`
`Fig. 3. Conventional b-bit binary weighted capacitor array.
`
`value and some error term:
`
`(5)
`
`Initially, consider only the case where all the errors are in the
`unit capacitors, whose values are independent identically-dis-
`tributed (i.i.d.) Gaussian random variables; later in this section,
`other non-idealities will be considered. Then the error terms
`and
`have zero mean, are independent, and have variance
`
`(6)
`
`where
`is the standard deviation of the unit capacitor.
`The linearity of a SAR ADC is limited by the accuracy of
`the DAC outputs, which are calculated here for the case of no
`. For a given DAC digital
`initial charge on the array
`input
`, with
`equals 0 or 1 represents the
`, the analog output for the conventional
`ADC decision for bit
`binary-weighted array is
`
`(7)
`
`will be
`The second term in the denominator
`neglected for this discussion. This will make the analysis sim-
`pler but will prevent a complete closed form solution for the in-
`tegral nonlinearity (INL). Subtracting the nominal value yields
`the error term
`
`with variance
`
`(8)
`
`(9)
`
`Fig. 4. “Down” transition of the conventional capacitor array.
`
`consumed is
`
`(4)
`
`identical to the “up” transition.
`The overall energy savings of the split capacitor array is input
`voltage (or output digital code) dependent. Where the relative
`frequency of “down” transitions is greater, the savings for the
`split capacitor array is enhanced, as seen in Fig. 8. Assuming a
`full swing sinusoidal input distribution, the split capacitor array
`is expected to have 37% lower switching energy than the con-
`ventional array.
`For this high-speed implementation, an additional advantage
`of considerable significance is related to the array’s settling
`time. During a “down” transition, two capacitors are required
`to switch for the conventional capacitor array; any mismatch,
`whether random or deterministic, in the digital logic driving
`these switches can cause the capacitor array to initially transition
`in the wrong direction, potentially exacerbating an overdrive
`condition for the preamplifiers. Only one capacitor in the
`split capacitor array transitions during any bit-cycle, providing
`inherent immunity to the skew of the switch signals. Simulation
`results comparing the settling times of the two arrays is shown
`in Fig. 9. For the simulation, the total width of the switches
`is identical for the split and conventional arrays. The split
`capacitor array settles up to 10% faster, which is used to reduce
`the bias currents in the preamplifiers by a similar amount.
`1) Linearity Performance: To compare the theoretical static
`linearity of the binary-weighted and split DACs, each of the
`capacitors is modeled as the sum of the nominal capacitance
`
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`

`742
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
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`Fig. 5. The b-bit split capacitor array, with the main subarray on top and the MSB subarray below.
`
`Fig. 7. “Down” transition of the split capacitor array. The “up” transition en-
`.
`tails switching C to V
`
`but only the total number.
`capacitors are connected to
`Thus, (9) holds for the case of the split capacitor array as well.
`This error is also directly related to the INL of the ADC, and
`thus there should be no difference between the maximum INLs
`of the two arrays.
`The DNL of the capacitive DAC is, neglecting gain errors, the
`difference between the voltage errors at two consecutive DAC
`outputs, as in
`
`The worst case DNL for the binary weighted capacitor array is
`expected to occur at the step below the MSB transition, where
`its variance is
`
`(10)
`
`Fig. 6. Switching procedure for split capacitor array. i represents the bit cur-
`rently being decided.
`
`This voltage error is simply the sum of the errors from unit
`. Because the errors in the unit
`capacitors connected to
`capacitors are assumed to be i.i.d., it does not matter which unit
`
`(11)
`
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`GINSBURG AND CHANDRAKASAN: 500-MS/s 5-bit ADC IN 65-nm CMOS WITH SPLIT CAPACITOR ARRAY DAC
`
`743
`
`Fig. 8. Normalized switching energies of the conventional and split capacitor
`arrays versus output code. The number of “down” transitions is greater on the
`left side of the plot.
`
`Fig. 10. Behavioral simulation comparing the linearity of the split and con-
`ventional capacitor arrays. 10 000 Monte Carlo runs were performed, with i.i.d.
`Gaussian errors in the unit capacitors ( =C = 3%). The standard deviation
`of the INL and DNL are plotted.
`
`in (12). This can be
`causing the cancellation of
`also be seen in the energy example above. In Fig. 4, the errors
`of the top capacitors are completely uncorrelated for the two
`contributes
`bit decisions; however, in Fig. 7, the error of
`equally to both bit decisions.
`A behavioral simulation of the SAR ADC, with both the bi-
`nary weighted and split capacitor arrays, was performed. The
`values of the unit capacitors are taken to be Gaussian random
`, and
`variables with standard deviation of 3%
`the ADC is otherwise ideal. Fig. 10 shows the results of 10 000
`Monte Carlo runs, where the standard deviation of the INL and
`DNL are plotted versus output code at the 5-bit level. As ex-
`pected, the conventional and split arrays have identical INL
`better DNL.
`characteristics, and the split capacitor array has
`This improvement in DNL is similar to that conferred at the
`MSB transition from using 1-bit of unary decoding in a seg-
`mented DAC [24].
`The above discussion assumes that the errors in the unit ca-
`pacitors are due to an i.i.d. random process. In practice, care
`must be taken during layout to ensure absence of systematic
`nonidealities. The unit capacitors are arranged in a common
`centroid configuration to eliminate the effect of first order gra-
`dients. Fringing effects at the edge of the array are reduced by
`using 32 dummy capacitors around the 32 active unit capacitors.
`The largest capacitors in the main subarray and MSB subarray
`are distributed so as to have equal numbers of edges next to the
`dummy capacitors to further reduce fringing errors. The split ca-
`pacitor array does have twice as many bottom plate signals that
`must be routed within the array. Coupling from these routes to
`the top plate routing can cause linearity errors and was avoided
`by routing the top and bottom plate signals distant from each
`other, which was sufficient at 5-bit resolution. For higher resolu-
`tions, electrostatic shielding may be necessary where the bottom
`
`Fig. 9. Simulation of the settling time of the split and conventional capacitor
`arrays under the presence of digital timing skew.
`
`For the split capacitor array, the worst case DNL also occurs at
`the step below the MSB transition, but its value is
`
`This error has a variance of
`
`(12)
`
`(13)
`
`Comparing (11) and (13) shows that the standard deviation of
`lower for the split capacitor array.
`the worst case DNL is
`and
`Conceptually, this occurs because the errors at
`are partially correlated for the split capacitor array,
`
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`744
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
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`Fig. 11. Comparator schematic showing preamplifier chain, latch, and VDL inserted in series with the latch strobe signal.
`
`plate routing is separated from the capacitors by grounded metal
`[25]. Shielding can also improve immunity to noise coupling
`from the substrate.
`
`B. Comparator With Adjustable Strobing
`
`The comparator, shown in Fig. 11, has a regenerative latch
`preceded by two stages of autozeroed preamplifiers, used to re-
`duce the input referred offset of the latch to below one quarter of
`the LSB voltage. The preamplifiers are linear amplifiers with an
`input NFET differential pair
`-
`and resistive loads, formed
`-
`operating in the linear region. The gain per
`by PFETs
`stage is selected to be 3–4 for ease of integration at both low
`voltages and with very short channel devices. The offset of the
`first preamplifier is cancelled using output offset storage. The
`sizing of the preamplifiers, autozeroing capacitors, and latch
`follows the offset/matching-limited optimization procedure de-
`scribed in [26].
`During bit-cycling, the clock period is divided into one phase
`for the settling of the DAC and preamplifiers and one phase for
`regeneration of the latch. The latch typically resolves, even for
`small inputs, in much less than the 1ns that is allocated assuming
`an even division of the period. The ADC sits idle after the latch
`settles until the start of the next bit-cycle. Self-timed bit-cycling
`uses this idle time to start the next bit-cycle early [18], [27]. This
`approach relaxes the preamplifier settling time requirement for
`all but the first bit-cycle (determining the MSB), as it has no
`prior bit-cycle from which to borrow. Instead, here a variable
`delay line (VDL) has been inserted in series with the latch strobe
`signal to extend analog settling time in the first half of every
`bit-cycle, including the first, “pre-borrowing” time from that
`bit-cycle’s own latch phase. The beginning of every bit period
`is synchronous with the sampling clock, and the latch strobing
`is determined by the setting of the VDL, which is tuned exter-
`nally to see tradeoffs between extended settling time and ADC
`performance.
`
`C. Technology Considerations
`
`The SAR architecture’s digital complexity directly benefits
`from the reduced feature sizes. Even though this ADC uses a
`fully static CMOS logic style, it still consumes less power than
`the highly customized logic, including dynamic registers, used
`
`in [18]. Care was taken throughout the digital logic to provide
`the maximum robustness in presence of delay variations.
`The two analog blocks are well suited for integration in 65-nm
`CMOS with the following design considerations. For the same
`absolute device size, transistor matching improves in successive
`technology generations, allowing smaller total device area and
`capacitance in the comparators [28]; however, the matching is
`not improved for minimum size devices. Also, due to the re-
`of the short channel
`duced power supplies and decreased
`devices, it is difficult to get high gain in a single analog stage.
`The preamplifiers and latch use non-minimum length transistors
`to improve both the matching and output impedance. While this
`, there is min-
`does increase device capacitance for the same
`imal power impact because wiring parasitics dominate the total
`capacitance in the comparator.
`The capacitor array is entirely passive, and its switching
`speed is improved with the shorter gate lengths. Because no
`analog-specific processing steps (e.g., a thin oxide for high
`density MiM capacitors) were used in fabrication the capacitors
`are formed using interdigitated metal comb capacitors. The
`capacitance is determined by fringing between adjacent metal
`lines, structures that have been shown to achieve similar den-
`sities to MiM capacitors with matching limits at greater than
`the 7-bit level [29]. The capacitance size is chosen according
`to the matching requirements discussed in Section III-A. The
`input voltage is constrained to between 0 and 400mV to allow
`NFET transistor without
`sampling with a single standard-
`exceeding the process voltage limit of 1.2 V.
`
`IV. MEASUREMENTS
`The ADC has been fabricated in a 65-nm CMOS technology;
`a die photograph is shown in Fig. 12. With a 91-kHz input
`0.16/0.15 and
`sampled at 500 MS/s, the INL and DNL are
`0.20/0.26 LSBs, respectively (Fig. 13). The split capacitor
`array suffers no linearity degradation as compared to a separate
`on-chip test channel with the conventional array. The split array
`uses 31% less power from the 400 mV reference voltage supply;
`the difference in energy savings from the theory presented above
`is due to the increased bottom-plate routing.
`The delay line was tested using an on-chip delay detection
`circuit and varying the input differential voltage. Due to an un-
`
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`

`

`GINSBURG AND CHANDRAKASAN: 500-MS/s 5-bit ADC IN 65-nm CMOS WITH SPLIT CAPACITOR ARRAY DAC
`
`745
`
`Fig. 12. Photograph of 1.9  1.4 mm die.
`
`Fig. 14. Dynamic performance versus input frequency.
`
`Fig. 13. Static linearity of ADC versus output code.
`
`derestimation of parasitics in the delay line, only the first two
`delay steps out of 16 provided sufficient time for latch regener-
`ation, and these extended the period available to the preampli-
`fiers by about 10%. At 250 MS/s, a 0.5–1 dB improvement in
`SNDR was achieved by properly tuning the delay.
`The dynamic performance of the ADC is shown in Fig. 14
`with the input frequency swept from DC to beyond Nyquist.
`The signal-to-noise-plus-distortion ratio (SNDR) does not drop
`by 3 dB until past the Nyquist frequency. A fast Fourier trans-
`form (FFT) of a 239.04-MHz input is shown in Fig. 15. Spurs
`(a)–(d) result from gain errors and skew between channels, and
`spurs (e)–(f) are due to offset mismatch. All of these spurs are
`below 39 dBFS, and their combined power is still less than
`the total noise power (excluding the spurs) at this near-Nyquist
`input. The gain mismatch between channels is 0.9%. The in-
`dividual channels have an effective number of bits (ENOB) be-
`tween 4.65 and 4.75 with low-frequency inputs, dropping by 0.4
`bits at Nyquist.
`The ADC consumes 2.86 mW and 3.06 mW, respectively,
`from 1.2-V analog and digital supplies at the maximum sam-
`pling frequency. The ADC was also tested at lower sampling fre-
`quencies. At 250 MS/s, the ADC consumes a total of 1.58 mW
`
`Fig. 15. FFT of 239.04-MHz sine wave sampled at 500 MS/s; dominant spurs
`are labeled.
`
`TABLE I
`SUMMARY OF PERFORMANCE
`
`from a 1 V digital and 0.8 V analog supply, while still main-
`taining Nyquist performance. A summary of the ADC is listed
`in Table I.
`
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`746
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007
`
`TABLE II
`COMPARISON OF STATE-OF-THE-ART ADCS
`
`V. COMPARISON AND DISCUSSION
`
`To enable a comparison to other ADCs operating at different
`speeds and resolutions, the figure of merit
`
`(14)
`
`is the power consumption, and ENOB is
`is used [17], where
`measured for input frequency
`, not to exceed Nyquist input.
`Table II compares state-of-the-art ADCs with sampling rates
`in excess of 100 MS/s and resolutions of 8 bits or less. From
`the results, this ADC has one of the best energy efficiencies of
`published work. In addition, as three out of the four best designs
`demonstrate, the time-interleaved SAR architecture can achieve
`very low power for these specifications. This work requires no
`linearity calibration or digital post-processing of the samples.
`
`VI. CONCLUSION
`
`An ADC targeted for UWB specifications has been presented.
`The time-interleaved SAR architecture provides superior en-
`ergy efficiency to a flash converter because of its linear growth
`in complexity with the resolution. Two new techniques have
`enabled high-speed,
`low-power SAR operation. The split
`capacitor array offers both lower switching energy and im-
`proved settling speed as compared to the conventional array.
`Joint timing design of the analog and digital portions of the
`chip, as demonstrated with the adjustable latch strobing instant,
`can ease settling time requirements and use otherwise wasted
`idle time during bit-cycling. State-of-the-art energy efficiency
`and performance have been demonstrated with robust operation
`in deep-submicron CMOS.
`
`ACKNOWLEDGMENT
`
`The authors would like to thank Texas Instruments for fabri-
`cating the chip. They would also like to thank C. Mangelsdorf
`of Analog Devices for feedback on the latch-delay circuit and
`N. Verma from MIT for many discussions throughout the design
`process.
`
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`[1] A. B. Batra et al., Multi-Band OFDM Physical Layer Proposal
`for IEEE 802.15 Task Group 3a IEEE, P802.15-04/0493r0 [On-
`line]. Available: http://grouper.ieee.org/groups/802/15/pub/04/15-04-
`0493-00-003a-multi-band-ofdm-cfp-document-update.zip
`
`[2] R. F. Fisher et al., DS-UWB Physical Layer Submission to 802.15
`Task Group 3a IEEE, P802.15-04/0137r3 [Online]. Available:
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`
`Anantha P. Chandrakasan (M’95–SM’01–F’04)
`received the B.S, M.S., and Ph.D. degrees in elec-
`trical engineering and computer sciences from the
`University of California, Berkeley, in 1989, 1990,
`and 1994, respectively.
`Since September 1994, he has been with the Mass-
`achusetts Institute of Technology, Cambridge, where
`he is currently the Joseph F. and Nancy P. Keithley
`Professor of Electrical Engineering. His research
`interests include low-power digital integrated circuit
`design, wi