2008 International Conference on Microelectronics
`
`A 10-bit Low-Power SAR ADC With a Tunable
`Series Attenuation Capacitor
`
`Lado Filipovic
`Department of Electronics
`Carleton University
`Ottawa, ON, Canada
`lfilipo2@doe.carleton.ca
`
`Leonard MacEachern
`Department of Electronics
`Carleton University
`Ottawa, ON, Canada
`leonard@ieee.org
`
`Abstract— A 10-bit successive approximation analog-to-digital
`converter (ADC), with offset correction circuitry and a tunable
`series attenuation capacitor is presented for implantable biosen-
`sor applications. The ADC is designed in a standard 0.13μm
`CMOS process technology and can operate with supply voltages
`down to 0.6 V. The ADC uses MOSFETs that are designed
`to operate in the sub-threshold region of operation. The ADC
`achieved sample rates of up to 500 kS/s with all 1024 codes
`present and an INL and DNL of 0.1009LSB and 0.1429LSB
`respectively. A power dissipation of 20.9 pJ/cycle was measured,
`while operating at 100 kS/s, with a 0.6 V supply voltage and an
`INL and DNL of 0.2585LSB and 0.2862LSB respectively, with all
`codes present. With a 1.0 V VDD, a 320 kS/s signal achieved an
`INL and DNL of 0.1623LSB and 0.2858LSB, respectively, with all
`codes present. A series attenuation capacitor is used to reduce
`the size of the circuit. Since processing variations can change
`the value of this capacitor and degrade the ADC operation, it
`was designed to vary between 401.7 fF to 487.5 fF using five
`digital input bits. Without process variations, the optimal variable
`capacitor code was designed to be the middle code, “10000”.
`
`I. INTRODUCTION
`A successive aproximation (SAR) analog-to-digital con-
`verter (ADC) often suffers from decreased performance due
`to variation in processing. These variations can cause voltage
`offset as well as capacitor ratio mismatch, leading to signif-
`icant degradation in performance [1]. An advantage to SAR
`ADCs is that they consume low power when high speed is
`not required, making them a good candidate for implantable
`biosensors. However, the SAR ADCs also require a large area
`when a high number of bits is used. The area can be reduced
`using an architecture containing a series attenuation capacitor,
`similar to [1] and [2]. The quality of operation of the ADC
`highly depends on an exact capacitor ratio between the series
`attenuation capacitor and the parallel capacitors. Any variation
`in processing of this series capacitor can severely degrade
`the operation of the ADC. One way to reduce the effects
`of processing variation is to implement a tunable attenuation
`capacitor.
`In this paper, we present a 10-bit SAR ADC, designed using
`a standard 0.13μm CMOS process, that can achieve sample
`rates up to 500 kS/s, while operating at low power dissipation.
`The comparator was designed to have its transistors operate in
`the sub-threshold regime, in order to reduce power dissipation.
`The series attenuation capacitor was created to have a tuning
`
`D DV
`2
`
`5 1 2 C
`
`2 5 6 C
`
`1 2 8 C
`
`6 4 C
`
`3 2 C
`
`1 6 C
`
`8C
`
`4C
`
`2C
`
`C
`
`C
`
`D DV
`2
`
`inV
`
`r e fV
`S a m p l e S w i t c h
`
`D DV
`2
`
`To SAR
`
`Fig. 1. Sampling phase of the SAR ADC.
`
`range from 401.7 fF to 487.5 fF, using five digital input bits.
`The ADC is functional with supply voltages as low as 0.6 V.
`Section II of this paper presents the circuit architecture of
`the ADC, while section III explains the design of each circuit
`component. Section IV provides the post-layout simulation
`results of the ADC with parasitic capacitors included in the
`design, while in Section V, some conclusions are drawn.
`
`II. CIRCUIT ARCHITECTURE
`The architecture used for the presented SAR ADC is based
`on charge redistribution in a sampling binary weighted capac-
`itor array, similar to that presented in [3]. Other similar low
`power SAR ADCs were demonstrated in [4], [5], [6]. The
`standard SAR architecture includes a sample-and-hold (SH)
`circuit, a capacitor array, a comparator, a digital-to-analog
`converter (DAC), and digital control logic. Since the intention
`of the presented ADC is operation in low-power applications,
`an architecture that does not require a sample-and-hold circuit
`is selected, thereby requiring a comparator, a capacitor array,
`low-power CMOS digital logic, and analog switches. The SAR
`ADC has an input range from 1
`2 VDD to VDD. The main
`phases of the conversion cycle are similar to those described
`in [3], [7]:
`(i) Analog data, Vin, is sampled onto the bottom plate
`of the capacitor array, while the top plate is set to 1
`2 VDD,
`as shown in Figure 1. (ii) Figure 2 shows that the bottom
`plate of the capacitor array is forced to 1
`2 VDD, causing the
`top plate to become VDD - Vin, since the charge across the
`capacitor is static.
`(iii)The next step is the approximation
`stage, as shown in Figure 3. This is where the digital SAR
`logic controls the switching, starting with the most significant
`bit (MSB), and working down to the least significant bit (LSB).
`The comparator determines if the voltage on top of the plate
`of the capacitor array is higher or lower than 1
`2 VDD and
`
`399
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`
`Xilinx v. Analog
`IPR2020-01559
`Analog 2010
`
`

`

`D DV - V
`
`in
`
`5 1 2 C
`
`2 5 6 C
`
`1 2 8 C
`
`6 4 C
`
`3 2 C
`
`1 6 C
`
`8C
`
`4C
`
`2C
`
`C
`
`C
`
`D DV
`2
`
`inV
`
`r e fV
`S a m p l e S w i t c h
`
`D DV
`2
`
`To SAR
`
`Fig. 2. Sampling phase of the SAR ADC where the top plate of the capacitor
`becomes VDD - Vin.
`
`D DV - Vin
`
`+
`
`r e fV
`2
`
`5 1 2 C
`
`2 5 6 C
`
`1 2 8 C
`
`6 4 C
`
`3 2 C
`
`1 6 C
`
`8C
`
`4C
`
`2C
`
`C
`
`C
`
`D DV
`2
`
`inV
`
`r e fV
`S a m p l e S w i t c h
`
`D DV
`2
`
`To SAR
`
`Fig. 4. Comparator circuit
`
`Fig. 3. Approximation phase of the SAR ADC, with the MSB approximation
`step shown
`
`outputs a 0 or 1 respectively. A full n-bit conversion will
`require n clock cycles, meaning that for the 10-bit SAR ADC
`presented, 10 clock cycles are required for this step. (iv) After
`completing the approximation for the least significant bit, a
`new conversion cycle begins, and the previous data is valid.
`An extra three clock cycles are required to sample the analog
`signal, force it negative, and output the digital data after it is
`found to be valid, resulting in a total of n+3 clock cycles for
`approximating one n-bit cycle.
`
`III. CIRCUIT SCHEMATICS
`
`A. Comparator
`The architecture of the comparator is similar to the one
`presented in [3]. The ADC was designed to function with its
`MOSFETs operating on the edge of the sub-threshold regime.
`We found that for operation in deep sub-threshold, the bias
`current had to be constant in order to keep the offset reduced.
`Therefore, it was concluded that operating near the edge of the
`sub-threshold region is a better option for the 10-bit ADC [8].
`The comparator was designed so that the MOSFETs would
`operate with a gate-to-source voltage of approximately 0.33V,
`while the process used has a typical threshold voltage of
`approximately 0.35V. The current in this region is defined by
`(cid:5)
`[9] as
`(cid:2)
`
`(cid:3)(cid:4)
`
`1−e
`
`−VD S
`vT
`
`Fig. 5. SAR circuit including shift registers
`
`or lower than 1
`2 VDD. This is the core of the comparator, as
`it is where the top of the capacitor array is compared to the
`V low ( 1
`2 VDD) voltage. The amplifier is designed such that the
`maximum gain is achieved when the input voltage is 1
`2 VDD.
`The second stage is the offset correction circuitry, which is
`required in order to correct some efects of mismatch and
`process variation. In [10], it is shown that one way to correct
`the offset is to store the offset voltage on a capacitor during
`a reset phase, followed by canceling it during the comparison
`stage. Transistor M12 is there in order to eliminate the need
`to pre-charge the capacitor to GND or VDD before storing the
`offset voltage. Instead, using M12 as a switch, the capacitor,
`C1 - implemented using a MIMCAP, is pre-charged to the
`value at the node connecting the gates of the active PFET
`loads of stage 1 [8]. With this architecture, the output of stage
`1 is compared to the stored output with the offset included.
`
`B. Successive Approximation Register
`The successive approximation register schematic is shown
`in Figure 5. The circuit uses static CMOS logic and is based
`on the control logic from [3] and [6].
`
`C. Binary Weighted Capacitor Array
`The binary weighted capacitor array was implemented with
`MIMCAPs from the process library as in Figure 6. Since
`the array shown in Figure 1 contains very large capacitors,
`it would require more time for them to charge, and they also
`require a large amount of chip area. This can be solved using
`a series attenuation capacitor given by [1], [2]. The capacitor
`is placed in series with the capacitor array split in two, each
`with its own top plate switch. This helps reduce the chip area
`significantly and allows for faster speeds, since the largest
`capacitor that requires charging is 16C as opposed to 512C.
`
`(1)
`
`μef f COX vT
`
`2 ∗ e
`
`VGS−VT H
`m∗vT
`
`IDS = W
`L
`where μef f is the effective mobility, vT is the thermal voltage,
`COX is the oxide capacitance, W and L are the width and
`length of the MOSFET device respectively, VGS and VDS are
`the gate-source and drain-source voltages respectively, m is the
`body effect coefficient and VT H is the threshold voltage of the
`MOSFET. The comparator schematic is shown in Figure 4, and
`it is shown that the comparator has two stages. The first stage
`is a differential amplifier with active PMOS loads (transistors
`M1 and M2), and NMOS transistors (M3 and M4) as the
`inputs.The voltage inputs to the gates of M3 and M4 determine
`the direction of current flow depending if CompareIn is higher
`
`400
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`
`

`

`
`
`INL
`DNL
`
`10010
`
`1
`
`0.8
`
`0.6
`
`0.4
`
`0.2
`
`Non−Linearity (LSB)
`
`
`01110
`
`01111
`
`10000
`Tunable Capacitor Code
`
`10001
`
`Fig. 6. Binary weighted capacitor array circuit including shift registers
`
`Fig. 8.
`
`INL and DNL plots for all codes at 500kS/s, VDD=1.2V, Vref=0.6V
`
`Fig. 7. Schematic of the digitally tunable attenuation capacitor, CAT T .
`
`(2)
`
`CAT T =
`
`The size of the attenuation capacitor, from [2] is:
`ΣLSBC apacitors
`ΣM SBC apacitors
`where the sum of the LSB capacitors is 32C, the sum of the
`MSB capacitors is 31C, and the size of the unit capacitor, C,
`is 440fF. Therefore, the MSB capacitors add up to 14.08pF
`and the LSB capacitors add up to 13.64pF. The resulting
`attenuation capacitor, CATT, should be approximately 454fF.
`A common centroid layout was used in order to reduce
`mismatch in the capacitors by reducing cross-chip gradients.
`There is a total of 63 unit capacitors required, which was laid
`out in an array of 8 x 8 capacitors, each designed using a
`MIMCAP with 15μm x 14μm dimensions. In order to avoid
`different processing and etching conditions for the capacitors
`on the outside of the array, a ring of dummy capacitors was
`used around the entire array. In addition, guard rings were used
`to surround the capacitor array in order to improve isolation
`from switching components.
`
`(cid:3)−1
`
`+ CAP3
`3C
`
`2C
`
`2C
`
`2C
`
`Equation 3 are all 1, resulting in an attenuation capacitance of
`CATT = 2.06C. The maximum capacitance occurs when the
`switches are open, or when the CAPx bits from Equation 3
`are all 0, resulting in an attenuation capacitance of CATT =
`2.5C. The circuit was optimized to perform with the capacitor
`select bits set to 10000 for CAP1, CAP2, CAP3, CAP4, and
`CAP5 respectively, which results in an attenuation capacitance
`of 2.33C. Therefore, in order to achieve the desired series
`attenuation capacitor of 454fF, each individual capacitor, C,
`needs to be 454fF/2.33 = 195fF. Since the switches add to
`the overall attenuation capacitance, this value is tuned using
`extracted simulations. It is found that the attenuation capacitor
`is allowed to vary between 401.7fF and 487.5fF by changing
`the tunable capacitors switch control inputs.
`
`IV. SIMULATION RESULTS
`The ADC was designed in a 0.13μm CMOS technology
`using 1.4mm2 of chip area, shown in Figure 12. The presented
`simulation results include the effects of parasitic capacitances
`and bond pads, extracted from the layout.
`
`A. ADC Attenuation Capacitor Tuning
`In order to find the optimal code for the tunable capacitor,
`INL and DNL measurements were taken for various capacitor
`ranges, and the results were recorded in Figure 8. Figure 8
`shows that ”10000“ is the optimal code, as the lowest INL
`and DNL were measured at this capacitor setting.
`
`B. ADC INL/DNL Simulation Results
`Figure 9 shows the INL and DNL results when the ADC
`is running at 100 kS/s, with a VDD of 0.6V. A slow ramp,
`from 0.3V to 0.6V was placed at the input in order to span
`the full 1024 codes. Figure 9 shows that INL is 0.2585LSB,
`while DNL is 0.2862LSB, with all codes present. Figure 10
`shows the INL and DNL results when the ADC is running at
`320 kS/s, with a VDD of 1.0V. A slow ramp, from 0.5V to
`1.0V was placed at the input in order to span the full 1024
`codes. Figure 10 shows that INL is 0.1623LSB, while DNL is
`0.2858LSB, with all codes present. Figure 11 shows the INL
`and DNL results when the ADC is running at 500 kS/s, with
`a VDD of 1.2V. A slow ramp, from 0.6V to 1.2V was placed
`at the input in order to span the full 1024 codes. Figure 11
`shows that INL is 0.1009LSB, while DNL is 0.1429LSB, with
`all codes present.
`
`D. Tunable Attenuation Capacitor
`The tunable capacitor schematic, shown in Figure 7, allows
`for 5-bit tuning of the series attenuation capacitor. This allows
`us to vary the capacitor value until an appropriate value is
`found to offset the mismatch due to process variation. The
`(cid:3)−1 +
`(cid:3)−1 +
`(cid:2)
`(cid:2)
`(cid:2)
`equation that governs the capacitance is
`(cid:3)−1 +
`(cid:3)−1
`(cid:2)
`(cid:2)
`+ CAP1
`+ CAP2
`CAT T =
`C
`2C
`+
`+ CAP4
`+ CAP5
`4C
`5C
`
`2C
`
`2C
`
`(3)
`Where C is the value of the individual capacitors and CAP1
`to CAP5 are binary values of 1 or 0 depending if the switch is
`open or closed, respectively. The minimum capacitance occurs
`when all the switches are closed, or when the CAPx bits from
`
`401
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`
`

`

`TABLE I
`SUMMARY OF POWER CONSUMPTION VS. VDD
`
`VDD
`(V)
`0.6
`1.0
`1.2
`
`Sample Rate
`(kS/s)
`100
`320
`500
`
`Power Consumption
`(μW)
`2.09
`16.34
`39.56
`
`Energy per Cycle
`(pJ/cycle)
`20.9
`51.07
`79.12
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`0.4
`
`0.2
`
`0
`
`−0.2
`
`−0.4
`0
`
`0.1
`
`0
`
`−0.1
`
`−0.2
`
`−0.3
`0
`
`INL Non−liearity (LSB)
`
`DNL Non−linearity (LSB)
`
`Fig. 9.
`
`INL and DNL plots for all codes at 100kS/s, VDD=0.6V
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`0.2
`
`0.1
`
`0
`
`−0.1
`
`−0.2
`0
`
`0.1
`
`0
`
`INL Non−liearity (LSB)
`
`Fig. 12. Layout of the complete ADC chip
`
`dissipation. The chip was designed using a standard 0.13μm
`CMOS technology, with an approximate chip area of 1.4mm2,
`as shown in Figure 12.
`
`REFERENCES
`[1] K Abdel-Halim, L. MacEachern, and S.A. Mahmoud, ”A nanowatt suc-
`cessive approximation adc with offset correction for implantable sensor
`applications”, in Circuits and Systems, 2007. ISCAS 07. Proceedings of
`the 2007 International Symposium on, 2007, vol. 1, pp. 235154
`[2] R. Jacob Baker, CMOS: Circuit Design, Layout, and Simulation, John
`Wiley and Sons, 2nd edition, 2005.
`[3] K. Abdel-Halim, L. MacEachern, and S.A. Mahmoud, “A nanowatt adc
`for ultra-low-power applications,” in Circuits and Systems, 2006. ISCAS
`’06. Proceedings of the 2006 International Symposium on, vol. 1, pp.
`617-20.
`[4] Jens Sauerbrey et. al, “A 0.5V, 1μm Successive Approximation ADC,”
`IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp. 1261-1265, July
`2003.
`[5] Louis S. Y. Wong et. al, “A Very Low-Power CMOS Mixed-Signal IC
`for Implantable Pacemaker Applications,” IEEE Journal of Solid-State
`Circuits, vol. 39, no. 12, pp. 2446-2456, December 2004.
`[6] Michael D. Scott et. al, “An Ultralow-Energy ADC for Smart Dust,” IEEE
`Journal of Solid-State Circuits, vol 38, no. 7, pp. 1123-1129, July 2003.
`[7] R. Gregorian, CMOS Op-Amps and Comparators, John Wiley and Sons,
`New York, NY, 1999.
`[8] K. Abdel-Halim, “Ultra low power adc for biomedical applications,” M.S.
`thesis, Carleton University, Ottawa, ON, Canada, 2007.
`[9] Chris Hyung-Il Kim et. al, “Ultra Low Power DLMS Addaptive Filter
`for Hearing Aid Applications,” IEEE transactions on Very Large Scale
`Integration (VLSI Systems), vol. 11, no. 6, pp. 1058-1067, December
`2003.
`[10] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John
`Wiley and Sons, 1997.
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`−0.1
`
`−0.2
`
`−0.3
`0
`
`DNL Non−linearity (LSB)
`
`Fig. 10.
`
`INL and DNL plots for all codes at 320kS/s, VDD=1.0V
`
`C. Power Consumption
`The minimum power consumption is 20.9 pJ/cycle, when
`the ADC is running at 100 kS/s, with a 0.6 V power supply.
`Table I summarizes the power consumption for the ADC.
`
`V. CONCLUSION
`A 10-bit ADC was designed for low power applications
`and for low sample rates, such as those required in biomedical,
`implantable devices. By using the sub-threshold regions of the
`MOSFET, the ADC is designed to operate at a few microwatts
`for sub 1-V power supplies and at low sample rates. Higher
`sample rates are acheived at the expense of increased power
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`100
`
`200
`
`300
`
`400
`
`600
`500
`Digital Output
`
`700
`
`800
`
`900
`
`1000
`
`0.2
`
`0.1
`
`0
`
`−0.1
`
`−0.2
`0
`
`0.2
`
`0.1
`
`0
`
`−0.1
`
`−0.2
`0
`
`INL Non−liearity (LSB)
`
`DNL Non−linearity (LSB)
`
`Fig. 11.
`
`INL and DNL plots for all codes at 500kS/s, VDD=1.2V
`
`402
`Authorized licensed use limited to: Karen Rutherfod. Downloaded on December 17,2020 at 21:26:20 UTC from IEEE Xplore. Restrictions apply.
`
`