1-2
`
`A Dual Low Power /2 LSB NL 16b/lMsample/s
`SAR A/D Converter with on-chip Microcontroller
`
`Ka Y. Leung, Kafai Leung, Douglas R. Holberg
`Silicon Laboratories Inc.
`7000 West William Cannon Drive
`Austin, Texas 78735 USA
`Email: ka.leung, kafai.leung, doug.holberg} @silabs.com
`
`Abstract - A 0.35um double-poly CMOS 16b SAR A/D converter
`uses self-calibration techniques to obtain l2 LSB INL.
`The
`differential and single-ended THD at lMsample/s are 101dB and
`Each ADC consumes 20mW at 3V and
`96dB, respectively.
`occupies 2.9mm2 active area, resulting in a 0.9pJ/b FOM. The
`chip includes 3 ADCs, 2 DACs, 8051-microcontroller, CAN
`controller, DMA controller, 64K flash memory and 4K RAM
`occupying 26mm2.
`
`I. Introduction
`
`The use of successive approximation and self-calibration
`techniques in mixed signal devices enable the implementation
`of a low power, small area, high resolution analog-to-digital
`converter (ADC). A mixed signal integrated circuit, shown in
`Figure 1, illustrates a System on a Chip (SOC), which contains
`the core of an 8051 microcontroller, a digital 1/0 and data
`conversion circuits for interfacing with analog input/output
`signals. The SOC contains two 16b, lMsample/s ADCs, one
`lOb auxiliary ADC, two 12b DACs, three comparators, a
`DMA controller, a CAN controller, a precision oscillator, 64K
`bytes of non-volatile (Flash) program memory and 4352 bytes
`of random access data memory. Such a configuration targets a
`wide range of applications,
`including industrial process
`control, instrumentation, portable data acquisition systems and
`intelligent
`One does not typically
`find high
`sensors.
`conversion speed and precision ADCs in
`this
`class of
`integrated circuits, due to the fact that the integration of mixed
`signal devices with high density Flash memory, static RAM,
`high-speed
`logic
`and
`controller
`introduces
`process
`compatibility and digital noise management issues. This paper
`describes an SOC incorporating dual-single/differential 16b
`IM sample/s SAR converter with on-chip calibration circuitry
`to achieve 1/2 LSB INL on a single 3V power supply.
`digital
`Performance limitations
`due to
`interference
`are
`presented along with techniques used to minimize its effect.
`Reduction of integral non-linearity (INL) errors caused by
`capacitor matching, charge injection, and comparator memory
`effect are discussed. An example of an application of the SOC
`incorporating such SAR converter is also presented.
`
`II. Design & Implementation
`
`Figure 2 shows the charge redistribution ADC that consists
`of a 16b primary DAC having a set of primary capacitors
`
`associated with, a calibration DAC for calibrating each of the
`primary capacitors in the primary DAC, an "LSB" reference
`capacitor, an offset-compensation DAC for compensating the
`offset of the ADC and a gain-compensation DAC for
`compensating the gain error of the ADC. Partitioning of the
`16b primary DAC into three capacitor arrays in a bridge
`configuration is a technique that limits the largest capacitor in
`each of the three arrays to a value of 32 unit capacitors, a unit
`capacitor having a unit capacitance value of "C," where the
`unit capacitance value C is the smallest value capacitor in the
`array(s).
`In order to provide adequate head room for
`calibration, each primary capacitor in the primary DAC has a
`nominal or initial capacitance that is 9400 of the sum of all of
`the lower order capacitors in the respective array, i.e., the 8C
`primary capacitor has a nominal value that is 9400 of the sum
`of 4C, 2C, C and the LSB reference capacitor.
`
`Figure 1 System block diagram
`
`calibration of each of the primary
`To provide for
`capacitors in the primary DAC, the calibration DAC provides
`13 individual calibration capacitor arrays, each calibration
`array
`capacitor
`associated with one of the primary
`is
`capacitors in the primary DAC. Each calibration capacitor
`
`0-7803-9735-5/06/$20.00 ©2006 IEEE
`
`51
`
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`
`Xilinx v. Analog
`IPR2020-01559
`Analog 2011
`
`

`

`array assigned to each bit has a nominal capacitance of 12% of
`the primary capacitor and a resolution of 1/4LSB to provide
`-
`6% of calibration for the associated primary capacitor.
`13 primary capacitors
`Calibration of the
`[1], using
`capacitance compensation techniques, results in 104 correction
`coefficients. Whenever a bit is used during conversion, the
`calibration capacitor array associated with that bit applies its
`correction value. This calibration method eliminates the need
`In an extremely
`for an accurate error-correction DAC [2, 3].
`noisy environment, such as during production test, a test
`program is loaded into the on-chip microcontroller, which then
`executes instructions to average multiple error measurements
`to reduce the effect of noise, and stores the coefficients in on-
`chip Flash memory. The test program is removed afterwards
`to free the memory space and the coefficients are preloaded
`into a calibration register during the boot-up sequence.
`
`Calibration
`DAC
`(13 Capacitor arrays)
`
`DACs
`
`Offset &
`Gain
`
`allows for removal of the wide-band noise contribution of the
`common-mode driver. Additionally, at the end of the tracking
`phase, an internal state-machine disconnects the bottom plate
`of the MSB capacitors in the primary DAC and ground-
`sensing capacitor from the analog input and starts a successive
`approximation routine to arrive at the 16b result.
`A conventional fully
`differential ADC requires two
`separate capacitor array, one for each differential input. This
`architecture facilitates differential operation by utilizing two
`separate virtual single ended ADCs, and then taking the
`difference between the outputs with a subtraction circuit. This
`provides a dual pseudo-differential design. Thus, this device
`consists of two identical capacitor arrays, two sets of analog
`switches and SAR logic.
`However, this dual pseudo-
`differential design does include two comparators.
`The input
`of each ADC samples both common-mode (CM) and
`differential-mode (DM) signals. A digital subtractor removes
`Thus, common-mode induced offset of the
`the CM signal.
`comparator does not degrade the ADC linearity performance.
`
`C CDC .. 2C
`
`32C1
`
`VBIAS
`
`SAP
`Control
`Logic
`
`VIN
`
`VREF
`
`Vin
`
`block
`
`.
`
`,
`
`auto-zero
`
`to next stage
`
`RI
`
`R2
`
`R3
`
`R4
`
`Figure 2 Analog-to-digital converter block diagram
`
`The analog input of the primary capacitor array is
`configured such that, during sampling, the input voltage VIN
`is only sampled on the five MSBs. By using this technique of
`sampling the analog input using only five MSB capacitors,
`bottom-plate parasitic capacitance loading on the voltage is
`minimized. As a result, the lower order LSBs equaling 2C do
`This is compensated by the Gain
`not have VIN sample on.
`DAC, which accounts for the missing charge on the array.
`A single capacitor connected to the non-inverting input of
`the comparator samples an external ground reference during a
`of ground-loop
`cycle
`conversion
`eliminate
`effects
`to
`impedance. This ground loop impedance results in an IR drop
`between the silicon and the external ground.
`During the tracking phase of a conversion cycle, the
`inverting and non-inverting inputs of the comparator are
`connected through switches to the output of a unity gain buffer
`driven by a common mode voltage. This also provides an auto
`During the subsequent conversion phase,
`zero operation.
`these switches are opened, such that the conversion cycle is
`initiated from the common mode voltage. This technique
`
`Figure 3 One stage of comparator
`
`illustrates an inter-stage of a high speed
`Figure 3
`comparator utilized in the ADC. The comparator consists of
`seven preamplifiers to provide gain to resolve ILSB. During
`phase I of a conversion clock, a blocking switch disposed
`between the two outputs of the respective gain stage allows
`any DAC transients that may exist due to the uneven time
`associated with the sampling capacitance and
`constants
`input nodes to the
`sampling switch resistance on the
`This also effectively enables the
`comparator to settle.
`comparator to recover from overdrive conditions on the input.
`During phase II, the blocking switch is disabled and the
`comparator amplifies the input signal.
`As long as the amplifier output is slewing in one direction,
`there is no need for additional bandwidth. All that is required
`is a regenerative latch in the final stage that provides final
`amplification and sampling to reduce the potential
`for
`metastablity in the comparator when the differential input
`level is reduced to ILSB.
`Each amplifier of the comparator consists of a p-channel
`differential pair to reduce the memory effect due to trapped
`
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`
`52
`
`

`

`channel charge when the input of the stage is stressed [4].
`Two load resistors, R2 and R3, are provided which are
`ratiometric to a reference bias resistor, RI, and the bias
`resistor is driven by a common bias voltage, VBIAS. This
`results in a constant common-mode output voltage of the
`preamplifier over process and temperature variations.
`During the tracking phase or the auto zero phase, two auto
`zero switches are closed, connecting the two outputs of the
`stage to one side of a resistor, R4, which is ratiometric to
`resistor RI. This provides an auto-zero voltage on the output
`of the stage. Each of these outputs is connected to the internal
`amplifier through individual
`differential
`outputs of the
`capacitors.
`When the auto zero switches are opened,
`error of the amplifier
`common-mode induced offset
`is
`Further, the latch in the final stage and the
`eliminated.
`preceding preamplifier stages are isolated before the end of
`phase II, the latch phase, to reduce potential kickback noise at
`the comparator input.
`The self-calibration techniques utilizing the calibration
`arrays reduce the effects of component mismatch, but digital
`circuitry and on-chip
`crosstalk
`due to
`the
`correction
`microcontroller
`still
`ruin
`the
`linearity and noise
`can
`performance of the converter.
`Additional techniques for
`reducing digital interference include:
`(1) a unified clock
`circuitry for analog and digital blocks, (2) analog ground
`shields between critical analog components and substrate, (3)
`separated analog and digital power buses, and (4) analog
`guard rings
`physical
`separation
`of noisy
`digital
`and
`components.
`
`III. Result
`
`Figures 4 and 5 compare DNL and INL before and after
`calibration. Measured un-calibrated INL and DNL are 9 and 7
`LSB, respectively.
`After calibration, the measured INL and
`DNL are improved to 0.5 and 0.6 LSB, respectively. Figure 6
`shows two frequency spectrums of data taken at 500k and IM
`sample/s while the microcontroller is running program at
`25MHz. Calibration improves the second harmonic to 114dB
`and the third harmonic to 109dB. The measured ENOB is
`differential and single-ended 100kHz
`15.3b and 15b for
`inputs, respectively. The ADC exhibits excellent performance
`over the temperature range of -40 to 85C.
`The ADC is fabricated in a 0.35um, 4M2P CMOS process
`The active die size of each ADC is 2.9mm2.
`(Figure 7).
`When the supply is 3V and reference is 2.5V, the power
`consumption of each ADC, including a bandgap reference, a
`reference buffer and a common-mode buffer, is 20mW (3mW
`for reference circuits). The figure of merit (FOM), given by
`equation 1, indicates that related power consumption to speed
`and accuracy of the ADC is 0.9pJ/b.
`
`FOM Power / (2
`
`x fS)
`
`(1)
`
`IV. Measured Performance
`
`5Vpp differential
`Full-scale input range ..................
`............ lMSample/s
`Conversion rate ......
`Resolution ..................
`16bit
`0.5LSB
`INL ..................
`0.6LSB
`DNL ..................
`Noise ...................1.OLSB
`......... 101dB
`THD (differential-ended) .........
`............. 96dB
`THD (single-ended) .....
`Power dissipation per ADC ...........
`....... 20mW
`Supply ..................
`3V
`Channel isolation .................. 100dB
`86dB
`CMRR ..................
`Area per ADC .................. 2.9mm2
`26mm2
`SOC area (Figure 7) ..................
`Technology ..................
`0.35um (2-p, 4-m) CMOS
`
`V. Applications
`
`One application of the above SOC with the enhanced ADC
`in pulse oximeter which monitors the percentage of
`is
`hemoglobin that is saturated with oxygen [5]. A pulse
`oximeter works by passing light at two different wavelengths
`through body tissue (finger tips, ear lobe, or nose) and
`measuring the ratio of the absorption at the two wavelengths.
`This ratio indicates the percentage of hemoglobin which is
`oxygenated. The components that make up a pulse oximeter
`include a peripheral probe, ADC, MCU, Flash memory, and
`DAC as shown in Figure 8.
`The probe includes two light
`emitting diodes (LEDs) at different wavelengths, visible red
`(660nm) and near infrared (940nm), and photodiodes which
`sense the light passing through the tissue.
`The LEDs are
`alternately turned on and transmitted through the body tissues
`to photodiodes. The two DACs drive the LEDs, and the ADC
`oversamples and digitizes the received signal from the
`photodiode to a resolution of 18b. With 18b resolution, signal
`amplification and conditioning become unnecessary. Using a
`digital-filter algorithm implemented in firmware, the MCU
`captured
`digitized
`signal,
`eliminating
`high-
`filters
`the
`frequency noise due to ambient light and motion artifacts, and
`calculates the ratio of light absorption.
`This result
`is
`compared with a saturation lookup table stored in flash
`memory. The proportion of hemoglobin that is oxygenated is
`calculated, and the result is communicated to the monitoring
`station through the on-chip UART interface.
`The entire
`process from scheduling LEDs, converting photodiodes output
`voltage to formatting the data to the serial interface for
`transmission is controlled by the MCU.
`
`V. References
`
`[1] Miller, G. et al., "An 18b Self-Calibrating ADC," ISSCC
`Digest of Technical Papers, pp. 168-169, Feb., 1990.
`[2] Tan, K. et al., "Error correction techniques for high
`performance differential A/D converters," IEEE J. Solid-
`State Circuits, Vol. SC-25, p1318-1327, Dec. 1990.
`
`Authorized licensed use limited to: Karen Rutherfod. Downloaded on December 17,2020 at 21:29:02 UTC from IEEE Xplore. Restrictions apply.
`
`53
`
`

`

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`Figure 6 Measured FFT at 500k and lMsample/s.
`
`04
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`
`Figure 7 Chip micrograph.
`
`co
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`
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`
`[3] Lee, H et al., "A Self-Calibrating 15 Bit CMOS A/D
`Converters," IEEE J. Solid-State Circuits, Vol. SC-19,
`p813-819, Dec., 1984.
`[4] Kerth, D. et al., "An oversampling converter for strain
`gauge transducers," ISSCC Digest of Technical Papers,
`pp. 42-43, Feb., 1992.
`[5] Webster, J., "Design of pulse oximeters," Institute of
`Physics Publishing, 1997.
`
`Before calibration
`
`2
`
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`After calibration
`
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`
`-
`
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`
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`
`-
`
`-
`
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`
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`
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`
`4915
`
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`
`Figure 4 Measured DNL before and after calibration.
`
`65!
`(1l
`
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`
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`
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`
`After calibration
`
`........... -
`
`---------
`
`----.......
`
`....
`
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`Figure 5 Measured INL before and after calibration.
`
`Figure 8 Block diagram of pulse oximeter
`
`Authorized licensed use limited to: Karen Rutherfod. Downloaded on December 17,2020 at 21:29:02 UTC from IEEE Xplore. Restrictions apply.
`
`54
`
`