Copyrighted Material
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`Edited by
`STEVEN R. NORSWORTHY
`
`
`
`
`
`RICHARD SCHREIER
`
`GABORC. TEMES
`
`
`
`filter
`
`
`2nd-stage
`decirnation
`
`Delta-Sigma
`Data Converters
`Theory, Design, and Simulation
`
`Copyrighted Material
`
`Xilinx v. Analog
`IPR2020-01559
`Analog 2013
`
`Xilinx v. Analog
`IPR2020-01559
`Analog 2013
`
`

`

`Delta-Sigma
`Data Converters
`
`

`

`IEEE Press
`
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`Piscataway, NJ 08855-1331
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`Editorial Board
`John B. Anderson, Editor in Chief
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`P. M. Anderson
`M. Eden
`M. E. El-Hawary
`S. Furui
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`A. H. Haddad
`R. Herrick
`G. F. Hoffnagle
`R. F. Hoyt
`S. Kartalopoulos
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`R. S. Muller
`W. D. Reeve
`D. J. Wells
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`
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`
`Also of Interest from IEEE Press...
`
`Oversampling Delta-Sigma Data Converters: Theory, Design and Simulation
`edited by James C. Candy, AT&T Bell Laboratories and Gabor C. Temes, Oregon State University
`1992
`Hardcover
`512 pp
`ISBN 0-87942-285-8
`
`Clock Distribution Networks in VLSI Circuits and Systems
`edited by Eby G. Friedman, University ofRochester
`1995
`Hardcover
`544 pp
`
`ISBN 0-7803-1058-6
`
`Nonvolatile Semiconductor Memories: Technologies, Design, and Applications
`edited by Chenming Hu, University of California, Berkeley
`1991
`Hardcover
`496 pp
`
`ISBN 0-87942-269-6
`
`Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design
`edited by Behzad Razavi, AT&T Bell Laboratories
`1996
`Hardcover
`512 pp
`
`ISBN 0-7803-1149-3
`
`Routing in the Third Dimension: From VLSI Chips to MCMs
`Naveed A. Sherwani, Siddharth Bhingarde, and Anand Panyam, Microprocessor Division, Intel
`Corporation
`1995
`Hardcover
`
`ISBN 0-7803- 1089-6
`
`376 pp
`
`Circuits and Systems Tutorials
`Chris Toumazou, Editor; Nick Battersby and Sonia Porta, Assistant Editors
`1996
`Softcover
`700 pp
`ISBN 0-7803-1170-1
`
`

`

`Delta-Sigma
`Data Converters
`
`Theory, Design,
`and Simulation
`
`Edited by
`
`Steven R. Norsworthy
`Motorola
`
`Richard Schreier
`Oregon State University
`
`Gabor C. Temes
`
`Oregon State University
`
`IEEE Circuits & Systems Society, Sponsor
`
`IEEE
`
`The Institute of Electrical and Electronics Engineers, Inc., New York
`
`WILEY-
`INTERSCIENCE
`
`A JOHN WILEY & SONS, INC., PUBLICATION
`
`

`

`© 1997 THE INSTITUTE OF ELECTRICAL AND ELECTRONICS
`ENGINEERS, INC.
`3 Park Avenue, 17th Floor, New York, NY 10016-5997
`All rights reserved.
`
`Published by John Wiley & Sons, Inc., Hoboken, New Jersey.
`
`Nopart of this publication may be reproduced, stored in a retrieval system, or
`transmitted in any form or by any means, electronic, mechanical,
`photocopying, recording, scanning, or otherwise, except as permitted under
`Section 107 or 108 of the 1976 United States Copyright Act, withouteither the
`prior written permission of the Publisher, or authorization through payment of
`the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222
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`on the web at www.copyright.com. Requests to the Publisher for permission
`should be addressed to the Permissions Department, John Wiley & Sons,Inc.,
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`For general information on our other products and services please contact our
`Customer Care Departmentwithin the U.S. at 877-762-2974, outside the U.S.
`at 317-572-3993 or fax 317-572-4002.
`
`10 9
`
`Library of Congress Cataloging-in-Publication Data
`
`Delta-sigma data converters : theory, design, and simulation / edited
`by Steven R. Norsworthy, Richard Schreier, Gabor C. Temes ; IEEE
`Circuits & Systems Society, sponsor.
`p.
`cm.
`Includes index.
`ISBN 0-7803-1045-4
`2. Digital-to-analog converters.
`1. Analog-to-digital converters.
`3. Modulators (Electronics)--Design.
`I. Norsworthy, Steven R.
`(date)
`. I. Schreier, Richard (date)
`. III. Temes, Gabor C.
`(date)
`. IV. IEEE Circuits & Systems Society.
`TK7887.6.D45
`1996
`621.3815’322--de20
`
`96-14774
`CIP
`
`

`

`Contents
`
`Preface xv
`Introduction xvii
`
`Chapter 1 An Overview of Basic Concepts 1
`J. C. Candy
`
`1.2.3
`
`1.1 Introduction 1
`1.2 Digital Modulation 3
`1.2.1
`Quantization 3
`1.2.2
`Delta-Sigma Modulation 5
`1.2.2.1 First-Order Feedback Quantizer 5
`1.2.2.2 Modulation Noise in Busy Signals 7
`1.2.2.3 Pattern Noise from AX Modulation with dc Inputs 8
`1.2.2.4 Dead Zones in AZ Modulation 10
`1.2.2.5 Influence of Circuit Parameters on AX Modulation 11
`High-Order Modulation 14
`1.2.3.1 Predicting In-Band Values of Quantization Error 14
`1.2.3.2 Noise in High-Order AZ Modulation 14
`1.2.3.3 Dynamic Range of the Modulators 16
`1.2.3.4 Influence of Circuit Parameters on Second-Order Modulators 19
`1.2.3.5 Limit Cycles in Third-Order AX Modulators 20
`1.2.3.6 Noise Shaping Using Filters with Nonmonotonic Transfer Functions 22
`Some Alternative Modulator Structures 23
`1.2.4.1 Error Feedback 23
`1.2.4.2 Cascaded Modulators 24
`1.2.4.3 Delta Modulation 26
`
`1.2.4
`
`

`

`vi
`
`Contents
`
`1.3
`
`1.4
`
`16
`
`Decimating the Modulated Signal 28
`1.3.1 Multistage Decimation 28
`1.3.2 Design of the First-Stage Decimator 29
`1.3.3
`implementing sinc Decimators 32
`1.3.4 The Low-Pass Filter 35
`Oversampling D/A Converters 36
`1.4.1 Demodulating Signals at Elevated Word Rates 36
`1.4.2
`Interpolating with sinc-ShapedFilter Functions 37
`1.4.3 Demodulator Stage 38
`1.4.3.1 Quantizing the Digital Signal 38
`1.4.3.2 Quantization with Error Feedback 38
`1.4.3.3 Cascaded Demodulators 40
`1.4.3.4 Circuit Design for AZ Demodulation 40
`Conclusion 41
`References 41
`
`Chapter 2
`
`Quantization Noise in A> A/D Converters 44
`Robert M. Gray
`
`2.1
`2.2
`
`2.3
`2.4
`2.5
`2.6
`
`27
`2.8
`2.9
`2.10
`
`2.14
`
`Introduction 44
`Uniform Quantization 45
`Additive White-Noise Approximation 46
`Characteristic Function Method 53
`Pulse Code Modulation Quantization Noise 55
`Dithered PCM 58
`Single-Loop AZ Modulation 59
`Two-Stage (Cascade or MASH) AX Modulation 64
`Second-Order AX Modulation 66
`Some Extensions 68
`2.10.1 Dithered Single-Loop AX Modulation 68
`2.10.2 Multistage and Higher Order AX Modulation 68
`2.10.3 Leaky Integrating AZ Modulation 69
`2.10.4 Multibit Quantizer, Single-Bit Feedback 69
`2.10.5 Related Work 69
`Conclusion 70
`Acknowledgments 70
`References 70
`
`Chapter 3
`
`Quantization Errors and Dithering in A> Modulators 75
`Steven R. Norsworthy
`
`3.1
`
`3.2
`
`Introduction 75
`3.1.1
`Problems with Empirically Based Reports on AZ Modulators 77
`3.1.2
`Steps Taken to Ensure Accuracy of Results 77
`Basic Structures and Terminology 78
`
`

`

`Contents
`
`vii
`
`3.3
`3.4
`
`3.9
`3.6
`
`3.7
`
`3.8
`
`3.9
`
`3.10
`3.11
`
`3.12
`3.13
`
`3.14
`
`3.15
`3.16
`3.17
`
`Observability of Periodic Sequences 80
`Tones in Single-Stage AX Modulators 84
`3.4.1
`Second-Order Modulator 85
`3.4.2 Third-Order Modulator 88
`3.4.3
`Fifth-Order Modulator 92
`3.4.4 Baseband Demodulation of Tones Near f,/2 95
`3.4.5 Higher-Order and Multibit Single-Stage Modulators 97
`Tonesin Multistage AX Modulators 98
`Tones in AX Converter Hardware 100
`3.6.1
`Third-Order Digital Modulator Test 101
`3.6.2
`Fifth-Order Digital Modulator Test 102
`3.6.3 Multistage Modulator Test 104
`Dither in PCM Quantizers 104
`3.7.1 Nonsubtractive Dither 104
`3.7.2
`Subtractive Dither 105
`Dither Topologies for AZ Modulators 107
`3.8.1 Dither Topologies for Single-Stage Modulators 107
`3.8.2 Dither Topologies for Multistage Modulators 109
`Empirical Studies of Noise-Shaped Dithering 112
`3.9.1
`Second-Order Modulator 112
`3.9.2 Third-Order Modulator 116
`3.9.3
`Fifth-Order Modulator 118
`3.9.4
`Effect of Dither on Tones Near f,/2 119
`3.9.5 Multistage Modulators 120
`Dither Generation 121
`Dither in A/D Modulators 121
`3.11.1 Single-Stage A/D Modulator Example 121
`3.11.2 Multistage A/D Modulators 121
`Subtractive Noise-Shaped Dithering 123
`Dynamic Noise-Shaped Dithering 124
`3.13.1 Theory of Dynamic Dither 124
`3.13.2 Implementation Considerations of Dynamic Dither 127
`Dithered Multibit Noise-Shaping Coders 130
`3.14.1 Stability Test with Dither 130
`Chaos versus Noise-Shaped Dither 131
`Other Techniques 134
`Conclusion 135
`References 136
`
`Chapter 4
`
`Stability Theory for AX Modulators 141
`Robert W. Adams and Richard Schreier
`
`41
`42
`
`Introduction 1414
`Linear Analysis 142
`4.2.1
`The Linear Model 142
`4.2.2 Root Locus of a High-Order Modulator 144
`4.2.3 Describing Function Method 145
`
`

`

`viii
`
`Contents
`
`43
`
`4.4
`
`4.5
`46
`47
`
`First- and Second-Order Modulators 147
`4.3.1 First-Order Modulator 148
`4.3.2 Second-Order Modulator 149
`Practical Design Methodology 152
`4.4.1 Cookbook Design Procedure 152
`4.4.2 SNR Limits 153
`4.4.3 Sixth-Order NTF 154
`4.4.4 Design Trade-Offs 156
`Continuous-Time Design 158
`Nonlinear Stabilization Techniques 162
`Conclusion 163
`Acknowledgments 163
`References 163
`
`Chapter 5
`
`The Design of High-Order Single-Bit AX ADCs 165
`Robert W. Adams
`
`Bil
`5.2
`5.3
`5.4
`
`5.9
`
`5.6
`
`5.7
`5.8
`5.9
`
`Introduction 165
`Motivation for Using High-Order Single-Bit Loops 166
`Design Choices: SC or Active-RC? 167
`Stability 170
`5.4.1 Stability and the Uncontrolled Input Signal:
`A Practical Guide to Safe Operation 170
`5.4.2 Transient Input Signals and Stability:
`The Case for Mild Prefiltering 170
`Choices for the NTF 172
`5.5.1 nth-Order Pure Differentiation 172
`5.5.2 Butterworth High-Pass Response 173
`5.5.3 Complex Zeros on the Unit Circle (Inverse Chebyshev) 174
`Comparison of Loop Topologies 174
`5.6.1 Chain of Integrators with Weighted Feedforward Summation 176
`5.6.2 Chain of Integrators with Feedforward Summation and Local
`Resonator Feedbacks 177
`5.6.3 Chain of Integrators with Distributed Feedback 178
`5.6.4 Chain of Integrators with Distributed Feedback and Distributed
`Feedforward Inputs 179
`5.6.5 Error Feedback Only 180
`Nonlinear Global Stabilization Techniques 183
`Practical Measures for Preventing Idle Tones 185
`Practical Implementation of a Stereo 18-Bit AX ADC IC 186
`5.9.1 Noise-Shaping Modulator IC 186
`5.9.2 Switched-Capacitor Loop Filter Design 186
`5.9.3 Circuit Noise Considerations 189
`5.9.4 Stabilization Using Integrator Reset 190
`5.9.5 Op-Amp Design 190
`5.9.6 Results and Comments 191
`References 192
`
`

`

`Contents
`
`Chapter6 The Design of Cascaded A> ADCs 193
`Mike Rebeschini
`
`6.1
`6.2
`
`6.3
`
`6.4
`
`6.5
`6.6
`6.7
`6.8
`
`Introduction 193
`System Design 195
`6.2.1 Comparison of Single-Loop and Cascaded Designs 195
`6.2.1.1 Single-Loop Designs 195
`6.2.1.2 Cascaded Designs 196
`6.2.2 Analytical Linearized Modeling 196
`6.2.3 Software Simulations 197
`Analysis of Specific Cascaded Architectures 199
`6.3.1 Third-Order (1-1-1) Modulator 199
`6.3.2 Third-Order (2-1) Modulator 203
`Circuit Topologies for Third-Order (1-1-1) Cascade 204
`6.4.1 Autozeroed Integrator 204
`6.4.2 First Modulator of Third-Order (1-1-1) Cascade 206
`6.4.3 Second and Third Modulators of Third-Order (1-1-1) Cascade 207
`Sourcesof Error for the Third-Order (1-1-1) Cascade 209
`Experimental Results for the Third-Order (1-1-1) Cascade 211
`Continuous-Time Cascaded AX Modulators 213
`Conclusion 217
`References 218
`
`Chapter 7
`
`High-Speed Cascaded A> ADCs 219
`Brian Brandt
`
`Gal
`7.2
`
`7.3
`
`74
`
`75
`7.6
`l7
`
`Introduction 219
`AX Modulation at Low Oversampling Ratios 220
`A Cascaded Muitibit AZ Modulator 222
`7.3.1 Interstage Coupling 225
`Implementation of the Cascaded Multibit Modulator 229
`7.4.1 Gain Error 230
`7.4.2 Incomplete Settling 232
`7.4.3 Integrator Leakage 232
`Design of the Cascaded Multibit Modulator 233
`Experimental Results 239
`Summary 242
`References 242
`
`Chapter 8
`
`Delta-Sigma ADCs with Multibit Internal Converters 244
`Richard L. Carley, Richard Schreier, and Gabor C. Temes
`
`8.1
`8.2
`8.3
`
`Introduction 244
`Multibit Noise-Shaping Modulator Architectures 245
`DAC Architectures for Improved Linearity 247
`
`

`

`Contents
`
`8.3.1 internal DAC Topology 247
`8.3.2 Element-Trimming Approaches 249
`8.3.2.1 One-Time Trimming Methods 249
`8.3.2.2 Repeated Trimming Methods 251
`8.3.2.3 Other Element-Matching Methods 251
`8.3.3 Dynamic Element Matching 251
`8.3.3.1 Dynamic Element Randomization 253
`8.3.3.2 Dynamic Element Rotation—Barrel Shifter 256
`8.3.3.3 Individual Level Averaging 259
`8.3.3.4 Noise-Shaped Element Usage 260
`Digital Correction Techniques 264
`8.4.1 AX ADC Architectures with Error-Storing Random-Access Memory 264
`8.4.2 The Calibration of the Digitally Corrected AX ADC 265
`8.4.3 An Improved Digital Correction System 267
`8.4.4 Cascade AX ADC SystemsUsing Digital Correction 269
`8.4.5 Digitally Corrected AZ ADC with Companding Quantizer 270
`Dual-Quantizer ADC Architectures 273
`8.5.1 The Leslie-Singh Architecture 273
`8.5.2 Dual-Quantization Cascade ADC Architectures 275
`8.5.3 Dual-Feedback Single-Path ADC Architecture 276
`Conclusion 277
`References 278
`
`8.4
`
`8.5
`
`8.6
`
`Chapter 9
`
`The Design of Bandpass AX ADCs 282
`Stephen Janizi, Richard Schreier, and Martin Snelgrove
`
`9.1
`8.2
`
`9.3
`
`9.4
`
`Introduction 282
`Bandpass A> Transfer Function Design 284
`9.2.1 The Linear Model 285
`9.2.2 Band Location 285
`9.2.3 Low-Pass Prototype Method 286
`9.2.4 Design by Generalized Filter Approximator 287
`9.2.4.1 The Design of H(z) 287
`9.2.4.2 The Design of G(z) 288
`9.2.4.3 An Example Modulator 288
`9.2.5 Modulator Performance 289
`9.2.5.1 Linear Model Predictions 289
`9.2.5.2 Simulations 290
`9.2.5.3 SNR versus Modulator Order and Oversampling Ratio 291
`Bandpass AX Modulator Design 292
`9.3.1 Standard Switched-Capacitor Design 292
`9.3.2 Switched-Capacitor V-Path Design 294
`9.3.3 Practical Considerations in Discrete-Time Systems 296
`9.3.3.1 Capacitor and 1/fNoise 296
`9.3.3.2 Op-amp Speed 297
`9.3.3.3 Sample-and-Hold Circuits 297
`9.3.4 Continuous-Time Design 297
`Decimation for Bandpass Modulators 300
`
`

`

`Contents
`
`xi
`
`9.5 Experimental Results 301
`9.5.1 Reported Implementations of Bandpass AX Modulators 301
`9.5.1.1 September 1990 301
`9.5.1.2 September 1991 301
`9.5.1.3 May 1992 302
`9.5.1.4 June 1992 302
`9.5.1.5 February 1993 303
`9.5.1.6 May 1994 304
`9.5.2 Performance Summary 304
`9.5.3 Comments on Bandpass AZ Modulator Performance 304
`96 The Future of Bandpass AX Modulation 305
`9.6.1 High-Frequency Converters 305
`96.2 Bandpass AX DACs 306
`97 Conclusion 306
`References 306
`
`Chapter 10 Architectures for AX DACs 309
`Gabor C. Temes, Shaofeng Shu, and Richard Schreier
`
`10.1
`10.2
`
`10.3
`
`10.4
`
`10.5
`
`introduction 309
`Architecturesfor the Noise-Shaping Loop 311
`10.2.1 Delta-Sigma Loop 311
`10.2.2 Error Feedback Structure 313
`10.2.3 Cascade Structure 315
`10.2.4 Multibit Quantizer Loops 316
`Design Example 1: A Fifth-OrderSingle-Bit Noise-Shaping Loop 321
`10.3.1 The Noise Transfer Function 321
`10.3.2 The Modulator Structure 322
`Design Example 2: A Third-Order (2+1) Multibit Cascade
`Noise-Shaping Loop 324
`Conclusion 331
`References 332
`
`Chapter 11
`
`Analog Circuit Design for A> ADCs 333
`Brian Brandt, Paul F. Ferguson, and Mike Rebeschini
`
`11.1
`11.2
`11.3
`
`11.4
`
`Introduction 333
`Architectural Considerations 334
`Building Blocks 336
`11.3.1 Input Integrator 336
`11.3.2 Specifications 337
`11.3.3 Fully Differential SC Integrator 337
`11.3.4 Op-Amp 343
`Circuit Nonidealities 348
`11.4.1 Effects of Component Nonidealities on the Integrator Performance 348
`11.4.2 Nonlinear Effects 350
`11.4.3 Intrinsic Noise 353
`
`

`

`xii
`
`Contents
`
`14
`
`11.6
`
`T12
`
`11.8
`
`11.9
`
`Modulator Component Design Considerations 356
`11.5.1 The Feedback DAC 356
`11.5.1.1 Reference Nonidealities 356
`11.5.1.2 Charge-Taking Nonidealities 357
`11.5.1.3 Charge-Delivery Nonidealities 358
`11.5.2 The Comparator 360
`11.5.3 The Clock Generation Circuitry 361
`System-Level Considerations 361
`11.6.1 Dynamic Range Considerations 361
`11.6.2 Clock Jitter 363
`11.6.3 Input Impedance 363
`Layout Considerations 365
`11.7.1 Signal Paths 365
`11.7.2 Busses 365
`11.7.3 RF Coupling 366
`11.7.4 Interfacing to the ADC 367
`Design Examples 369
`11.8.1 Second-Order Single-Stage AZ Modulator 369
`11.8.2 Second-Order Cascaded Modulator (1-1) 373
`Conclusion 378
`References 378
`
`Chapter 12
`
`Analog Circuit Design for AX DACs 380
`Mike Rebeschini and Paul F. Ferguson, Jr.
`
`12.1
`T22
`
`12.3
`
`12.4
`
`Introduction 380
`Building Blocks 381
`12.2.1 The Low-Resolution Input DAC 382
`12.2.2 Voltage References 384
`12.2.3 Reconstruction Filter 386
`12.2.3.1 Specifications 386
`12.2.3.2 Switched-Capacitor Reconstruction Using Biquads 387
`12.2.3.3 Noise-Shaping Filter 389
`12.2.3.4 Analog Decimation Filters for AZ DACs 390
`12.2.3.5 Effect of Nonideal Integrator Transfer Function 394
`12.2.4 Discrete-Time/Continuous-Time Interface 395
`12.2.4.1 Final Discrete-Time Stage 395
`12.2.4.2 Continuous-Time Reconstruction Filter 396
`12.2.5 Other Nonideal Effects 397
`12.2.5.1 Intrinsic Noise 397
`12.2.5.2 Dynamic Range Considerations 398
`Layout Considerations 398
`12.3.1 Differences from the ADC 398
`12.3.2 LayoutInfluences on the Architecture 399
`Design Examples 399
`12.4.1 A One-Bit High-Order AX DAC 399
`12.4.2 AMASH DAC 403
`12.4.3 Recent Developments 404
`References 404
`
`

`

`Contents
`
`xiii
`
`Chapter 13 Decimation and Interpolation for AX Conversion 406
`Steven R. Norsworthy and Ronald E. Crochiere
`
`13.1
`13.2
`13.3
`
`13.4
`Tei
`
`13.6
`
`13.8
`
`Introduction 406
`Scope of Design Trade-Offs and Alternatives 408
`Basic Principles of Sampling Rate Conversion—Algorithm Issues 408
`13.3.1 Decimation by M 410
`13.3.2 Interpolation by £ 411
`13.3.3 Duality 411
`13.3.4 Fractional Rate Changing 413
`Multistage Conversion 413
`Filter Design Considerations 416
`13.5.1 sincFilters 416
`13.5.2 Half-BandFilters 418
`13.5.3 Ternary-EncodedFIR Filters 419
`13.5.4 Combining sincFilters with FIR and IIR Filters 420
`13.5.5 Minimum-Phase FIR Filters 421
`13.5.6 Compensation Techniques 421
`Digital Filter Structures 422
`13.6.1 Direct-Form and Transpose Direct-Form Decimators and Interpolators
`424
`13.6.2 Polyphase Architectures for Decimators and Interpolators 426
`13.6.3 Multistage Architectures 429
`Hardware Implementation—Architectural Issues 432
`13.7.1 Historical Background 432
`13.7.2 Architectural Features and Styles 432
`13.7.3 Arithmetic Processing Issues 433
`13.7.3.1 Bit-Serial and Digit-Serial Arithmetic 433
`13.7.3.2 Parallel Multiplication 435
`13.7.3.3 Combined Bit-Serial and Bit-Parallel Architectures 435
`13.7.3.4 Single-Multiplier Architectures 436
`13.7.4 DSP and Programmable Implementations 438
`13.7.4.1 Multirate Filtering Efficiency on DSPs 440
`13.7.4.2 Multistage Implementation Including sinc'Filters 441
`13.7.4.3 Data Transfers and Buffering Between the Stages 441
`13.7.5 Mixed Analog and Digital Implementations 443
`Conclusion 443
`Acknowledgments 444
`References 444
`
`Chapter 14
`
`CAD for the Analysis and Design of A> Converters 447
`Christopher Wolff, John G. Kenney, and L. Richard Carley
`
`14.1
`14.2
`
`Introduction 447
`Multibit Converter Design 447
`14.2.1 Accumulation of Quantization Error 448
`14.2.2 Formulation and Solution of the Optimization Problem 449
`
`

`

`xiv
`
`Contents
`
`14.2.2.1 Quantization Noise 450
`14.2.2.2 Constraints 450
`14.2.2.3 Representation of Closed-Loop Poles for the Optimizer 451
`14.2.3 Example Results 4514
`14.3 Simulation Based on Difference Equations 452
`14.4 Simulation Based on the Quantizer Transfer Function 453
`14.4.1 Statistical Average Quantizer Transfer Function 453
`14.4.2 Distortion 455
`14.5 Simulation Approaches 458
`14.5.1 Overview 458
`14.5.2 Model Comparison 459
`14.5.3 Efficient Macromodel Simulation 460
`14.6 Conclusion 463
`References 464
`For Further Reading 466
`
`Index 469
`
`About the Editors 475
`
`

`

`Preface
`
`This book hasthe distinction of being thefirst original text on the subject of delta-sigma
`data conversion. Because of this, we thought our readers might appreciate a little back-
`ground on howthis book came into being. In 1992, the IEEE Press approached us about
`authoring a book on this subject. At the time, we felt that in order to do the job right, it
`would be necessary to enlist a number of authors renowned for their expertise in areas
`related to delta-sigma modulation. Afterall, the field of delta-sigma modulation encom-
`passes many diverse disciplines: systems and control theory, digital and analog signal
`processing, VLSI integrated circuit design, and knowledge of consumer and communica-
`tions applications. We did not feel qualified by ourselves to write about all of these.
`Therefore, we quickly concluded that we should gatheradditional experts who could join
`us in thoroughly covering these specialties and then treat the chapters more or less inde-
`pendently. With this style of book, there is always a tendency for the authors to overlap
`material, but we tried to orchestrate the overall effort to minimize overlap and to maxi-
`mize original content. Nevertheless,if the book comesacross to the readersas a collection
`of chapters, we confessthatit really is just that! Nonetheless we hopethat this text is use-
`ful and authoritative, and that it will quickly become a standard for both industry and aca-
`demiain this important area.
`Weare grateful to the contributing authors for their excellent material, and to the
`reviewers (Professors Ian Galton and Stanley Lipshitz, Dr. David Rich, and others) for
`their valuable comments and suggestions.
`
`Steven R. Norsworthy
`Richard Schreier
`Gabor C. Temes
`
`xv
`
`

`

`y.c.cany|An Overview
`of Basic Concepts *
`
`Chapter 7
`
`1.1 INTRODUCTION
`
`This chapter reviews the main properties of oversampling techniques that are useful for
`converting signals between analog and digital formats. Oversampling has become popular
`in recent years because it avoids many of the difficulties encountered with conventional
`methodsfor analog-to-digital and digital-to-analog (A/D, D/A) conversion, especially for
`those applications that call for high-resolution representation of relatively low-frequency
`signals.
`Conventional converters,illustrated in Figure 1.1, are often difficult to implementin
`fine-line very large scale integration (VLSI) technology. These difficulties arise because
`conventional methods need precise analog componentsin their filters and conversioncir-
`cuits and becausetheir circuits can be very vulnerable to noise and interference. The virtue
`of the conventional methodsis their use of a low sampling frequency, usually the Nyquist
`rate of the signal (i.e., twice the signal bandwidth).
`A low-passfilter at the input to the encoder of Figure 1.1 attenuates high-frequency
`noise and out-of-band components ofthe signal that alias into the signal when sampled at
`the Nyquist rate. Propertiesof this filter are usually specified for each application. The A/D
`circuit can take a numberof different forms, such as flash converters for fast operation,
`successive-approximation converters for moderate rates, and ramp converters for slow
`ones. At the decodera filter smooths the sampled output of the D/A circuit; the amount of
`smoothing required is usually part of the specification of the system. Thecircuits of these
`conventional converters require high-accuracy analog componentsin order to achieve high
`overall resolution.
`
`*This chapteris a rewrite of material from reference[1].
`
`

`

`1 An Overview of Basic Concepts
`
`Nyquist
`sampling
`clock
`
`v A
`
`digital Low-pass
`nalog to
`filter —
`
`
`
`Clock
`
`PCM ——>
`
`
`
`
`
`Low-pass
`Digital
`filter
`to analog
`
`
`
`
`
`Analog
`output
`
`Figure 1.1 Conventional pulse code modulation (PCM), including analogfil-
`ters for curtailing the aliasing noise in the encoder and for smooth-
`ing the output from the decoder.
`
`Oversampling converters, illustrated in Figure 1.2, can use simple and relatively
`high-tolerance analog components to achieve high resolution, but they require fast and
`complexdigital signal processing stages. These converters modulate the analog signal into
`a simple code, usually single-bit words, at a frequency muchhigherthan the Nyquistrate.
`
`High-speed
`clock
`
`|
`Analog
`“(ioe
`
`input
`
`‘i
`
`;
`Nyquist
`clock
`
`|
`
`PCM
`
`Encoder
`
`.
`Nyquist
`clock
`
`PCM
`——P| Register
`
`Digital
`filter
`
` Analog
`
`
`High-speed
`clock
`
`Demodulator
`
`output
`|[=-———>
`
`Decoder
`
`Figure 1.2 Oversampling pulse code modulation. The modulation and demod-
`ulation occur at sufficiently high sampling rate that digital filters
`can provide mostfor the antialiasing and smoothing functions.
`
`

`

`Digital Modulation
`
`3
`
`Weshall show that the design of the modulator cantrade resolution in time forresolution
`in amplitude in such a waythat imprecise analog circuits can be tolerated. The use of high-
`frequency modulation and demodulation eliminates the need for abrupt cutoffs in the ana-
`log antialiasing filter at the input to the A/D converter, as well as in the filters that smooth
`the analog outputof the D/A converter. Digitalfilters are used instead as illustrated in Fig-
`ure 1.2. A digital filter smooths the output of the modulator, attenuating noise, interfer-
`ence, and high-frequency components of the signal before they can alias into the signal
`band whenthe code is resampled at the Nyquist rate. Anotherdigital filter interpolates the
`code in the decoderto a high word rate beforeit is demodulated to analog form.
`Oversampling converters make extensive use of digital signal processing, taking
`advantageofthe fact that fine-line VLSI is better suited for providing fast digital circuits
`than for providing precise analog circuits. Because their sampling rate usually needsto be
`several orders of magnitude higher than the Nyquist rate, oversampling methodsare best
`suited forrelatively low-frequency signals. They have found use in such applications as
`digital audio, digital telephony, and instrumentation. Future applications in video and
`radar systems are imminentas faster technologies becomeavailable.
`An important difference between conventional converters and oversampling ones
`involve testing and specifying their performance. With conventional converters there is a
`one-to-one correspondence between input and output sample values, and hence one can
`describe their accuracy by comparing the values of corresponding input and output sam-
`ples. In contrast there is no similar correspondence in oversampling converters because
`they inherently include digital low-pass filters, and hence each input sample value contrib-
`utes to a whole train of output samples. Consequently, it has been useful to borrow tech-
`niques from communication technology to describe the performance of oversampling
`converters. Thus we measure their root-mean-square (rms) noise under various conditions,
`the distortion they introduce into sinusoidal signals, and their frequency responses. An
`important task in designing an oversampling converteris therefore the calculation of rms
`values of modulation noise and its spectral density. Examples of such calculations will be
`given in following sections.
`This chapter is organized into four main sections. Following this introduction, Sec-
`tion 1.2 describes some basic properties of the quantization noise. It then introduces delta-
`sigma modulation as a technique for shaping the spectrum of quantization noise, moving
`mostof the noise powerto high frequencies, well outside the band of the signal, whereit is
`removed bydigital filtering. A number of other modulators are also described. Section 1.3
`discusses the design of digital filters that decimate the modulated signal, converting it
`from a sequence ofshort digital words occurring at a high rate into long words occurring
`at the Nyquist rate. Section 1.4 describes oversampling D/A converters.
`
`1.2 DIGITAL MODULATION
`
`1.2.1. Quantization
`
`Quantization of amplitude and sampling in timeare at the heart of all digital modu-
`lators. Periodic sampling at rates more than twice the signal bandwidth need not intro-
`duce distortion, but quantization does, and our primary objective in designing modulators
`is to limit this distortion. We begin our discussion by describing some basic properties of
`
`

`

`1 An Overview of Basic Concepts Input range
`
`(b)
`
`Input range = + 6
`
`(a)
`
`Figure 1.3
`
`(a) An example of a uniform multilevel quantization characteristic
`that is represented by linear gain G and anerrore. (b) For two-
`level quantization the gain G is arbitrary.
`
`quantization that will be useful for specifying the noise from modulators. Figure 1.3(a)
`shows a uniform quantization that rounds off a continuous amplitude signal x to odd inte-
`gers in the range +5. In this example the level spacing A is 2. We will find it useful to
`represent the quantized signal y by a linear function Gx with anerror e: that is,
`
`y = Gxt+e
`
`(1.1)
`
`The gain G is the slope ofthe straight line that passes through the center of the quantiza-
`tion characteristic so that, when the quantizer does notsaturate (i.e., when —6 <x <6), the
`error is bounded by +A/2. Notice that the above consideration remains applicable to a two-
`level (single-bit) quantizer, as illustrated in Figure 1.3(b), but in this case the choice of
`gain G is arbitrary.
`The error is completely defined by the input, but if the input changes randomly
`between samples by amounts comparable with or greater than the threshold spacing,
`without causing saturation, then the error is largely uncorrelated from sample to sample
`and has equal probability of lying anywhere in the range +A/2. If we further assumethat
`the errorhasstatistical properties that are independentof the signal, then we can represent
`
`

`

`Digital Modulation
`
`5
`
`it by a noise, and some important properties of modulators can be determined. In many
`cases experiments have confirmed these properties, but there are two importantinstances
`where they may not apply: when the input is constant, and when it changes regularly by
`multiples or submultiples of the step size between sample times, as can happen in feed-
`back circuits.
`Whenwetreat the quantization error e as having equal probability of lying anywhere
`in the range +A/2, its mean square value is given by
`
`I
`
`nN
`
`%
`
`a _—,
`
`-A/2
`
`NR
`
`%
`
`>
`
`ul
`
`nlPe
`
`(1.2)
`
`For the ensuing discussion of spectral densities of the noise, we shall employ a one-sided
`representation of frequencies: that is, we assumethatall the poweris in the positive range
`of frequencies. When a quantized signal is sampled at frequency f, = 1/7, all of its
`powerfolds into the frequency band 0 <f</,/2. Then,if the quantization noise is white,
`the spectral density of the sampled noise is given by
`
`E(f) = ensP = CrmgN2T
`
`(1.3)
`
`Wecan use this result to analyze examples of oversampling modulators. Considerfirst
`ordinary pulse code modulation (PCM). A signal lying in the frequency band 0 <f<fo, to
`whicha dither signal contained in the band fp <f< f,/2 is added,is pulse code modulated
`at f,. The oversampling ratio (OSR), definedas the ratio of the sampling frequency f, to
`the Nyquist frequency 2fp, is given by the integer
`1
`Je _
`2fo fol
`
`(1.4)
`
`OSR =
`
`If the dither is sufficiently large and busy to whiten and decorrelate the quantizationerror,
`the noise powerthat falls into the signal band will be given by
`
`2
`No =
`
`fo
`
`0
`
`2
`
`_ ems
`2
`w=
`uid
`e (f) af — a = OSR
`
`(1.5)
`
`Thus we have the well-known result that oversampling reduces the in-band rms noise
`from ordinary quantization by the square root of the oversampling ratio. Therefore each
`doubling of the sampling frequency decreases the in-band noise by 3 dB, increasing the
`resolution by only half a bit.
`
`1.2.2 Delta-Sigma Modulation
`
`1.2.2.1 First-Order Feedback Quantizer. A more efficient oversampling
`quantizeris the delta-sigma (AZ) modulator shownin Figure 1.4(a). Although AX modu-
`lators usually employ two-level quantization, we commenceour discussion by assuming
`the modulator contains a multilevel, uniform quantizer with unity gain G = 1. The input
`
`

`

`1 An Overview of Basic Concepts
`
`Clock,f,
`
`Integrator
`Quantization
`
`(a)
`
`Accumulation
`
`(b)
`
`Figure 1.4 A block diagram of a AE quantizer and its sampled-data equivalent
`circuit.
`
`to the circuit feeds to the quantizer via an integrator, and the quantized output feeds back
`to subtract from the input signal. This feedback forces the average value of the quantized
`signal to track the average input. Any persistent difference between them accumulatesin
`the integrator and eventually corrects itself. Figure 1.5 illustrates the response ofthe cir-
`cuit to a ramp input; it shows how the quantized signal oscillates between two levels that
`are adjacentto the input value in such a mannerthatits local average equals the average
`input value [2].
`
`Quantized output
`
`
`
`
`Input
`
`Figure 1.5 The response of a multilevel AZ quantizerto a ramp input. A two-
`level response is obtained by curtailing input amplitude to a range
`of values that lies between two adjacent quantization levels.
`
`

`

`Digital Modulation
`
`7
`
`1.2.2.2 Modulation Noise in Busy Signals. We analyze the modulator by
`meansof the equivalent circuit shown in Figure 1.4(b). Here an added signal e represents
`the quantization error in accordance with Eq. (1.1) and the quantization gain G set to
`unity. Because this is a sampled-data circuit, we represent the integration by accumula-
`tion, also with unity gain. It can easily be shownthat the output of the accumulatoris
`
`and the quantized signalis
`
`Wy ep yo eed
`
`dy = X_, Fle;—2;_))
`
`(1.6)
`
`(1.7)
`
`Thusthis circuit differentiates the quantizatio