USOO7719452B2
`
`(12) United States Patent
`(10) Patent No.:
`US 7,719,452 B2
`
`Bardsley et al.
`(45) Date of Patent:
`May 18, 2010
`
`(54) PIPELINED CONVERTER SYSTEMS WITH
`ENHANCED LINEARITY
`
`(75)
`
`Inventors: Scott Gregory Bardsley, Gibsonville,
`NC (US); Bryan Scott Puckett,
`Stokcsdalc, NC (US); Michael Ray
`_
`_
`E1110“: Summerfields NC (Us); 13“
`Klshore KummaraguntlasAuSUns TX
`(US); Ahmed Mohamed AbdelattyAli,
`Oak Ridge, NC (US); Carroll Clifton
`Speir, Pleasant Garden, NC (US); James
`Carroll Camp, Greensboro, NC (US)
`
`(73) Assignee: Analog Devices, Inc., Norwood, MA
`(US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 118 days.
`
`(21) APPL N0~1 12/284,672
`
`(22)
`
`(65)
`
`Filed:
`
`Sep. 23: 2008
`_
`_
`_
`Prior Publication Data
`US 2010/0073210 A1
`Mar. 25, 2010
`
`(51)
`
`Int. Cl,
`(2006.01)
`H03M 1/20
`(52) US. Cl.
`....................... 341/131; 341/118; 341/120;
`341/155; 341/161; 341/162
`(58) Field of Classification Search ......... 341/1187122,
`341/131, 155, 161, 162
`See application file for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`6,404,364 B1*
`6,456,223 B1 *
`6,734,818 B2 *
`
`6/2002 Fetterman etal.
`........... 341/131
`9/2002 Yu et al .................. 341/161
`
`5/2004 Galton ............. 341/161
`
`8/2004 Nair et 31
`~~~~~ 341/118
`6,784,814 B1 *
`
`2/2006 Galton ............. 341/155
`7,006,028 B2:
`
`4/2006 A11 ....... . .................. 341/162
`7,034,736 B1 *
`4/2006 Malobeiti et al.
`........... 702/126
`7,035,756 B2
`9/2006 Malobeiti et al.
`........... 702/126
`7,107,175 B2 *
`3/2007 El-Sankary etal.
`......... 341/120
`7,187,310 B2 *
`5/2009 Newman etal.
`............ 341/131
`7,535,391 B1*
`7,602,324 B1 * 10/2009 Huang et a1.
`................ 341/131
`2006/0227052 A1* 10/2006 Tavassoli
`............. 343/700 MS
`* cited by examiner
`
`Primary ExamineriLinhV Nguyen
`(74) Attorney, Agent, or FirmiKoppel, Patrick, Heybl &
`Dawson
`
`(57)
`
`ABSTRACT
`
`Signal converter system embodiments are provided to sub-
`stantially reduce symmetrical and asymmetrical conversion
`errors. Signal-processing stages of these embodiments may
`include a signal sampler in addition to successively-arranged
`signal converters. 1n system embodiments, injected analog
`dither signals are initiated in response to a random digital
`code. They combine with a system’s analog input signal and
`the combined signal is processed down randomly-selected
`signal-processing paths of the converter system to thereby
`realize significant improvements in system linearity. Because
`these linearity improvements are realized by simultaneous
`processing ofthe input signal and the injected dither signal, a
`combined digital code is realized at the System’s O1111311193
`first portion of this combined digital code corresponds to the
`analog input signal and a second portion corresponds to the
`injected analog dither Signal. The final system digital code is
`realized by subtracting out the second portion with a back-
`end decoder that responds to the random digital code.
`
`6,373,424 B1*
`
`4/2002 Soenen ....................... 341/161
`
`20 Claims, 11 Drawing Sheets
`
` 80
`RANDOM
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`“/DIGITAL CODE\’
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`DIGITAL CODE
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`+ (90
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`Xilinx Exhibit 1001
`
`Page 1
`
`

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`U.S. Patent
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`May 18, 2010
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`May 18, 2010
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`US 7,719,452 B2
`
`1
`PIPELINED CONVERTER SYSTEMS WITH
`ENHANCED LINEARITY
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present disclosure relates generally to pipelined signal
`converters.
`
`2. Description of the Related Art
`Pipelined analog-to-digital signal converter systems are
`often used in high-speed, high-resolution conversion appli-
`cations. These systems generally realize a desired number of
`conversion bits with a cascade (i.e., a pipeline) of lower-
`resolution converter stages and thus achieve high resolution at
`sampling speeds that are difficult to realize with other con-
`verter systems. Each stage of a pipelined system quantizes
`that stage’s input signal to a predetermined number of digital
`bits and forms an analog output signal which is presented to a
`succeeding stage for further signal processing.
`The advantages of sampling speed may, however, be
`negated if conversion linearity is insufficient. For example,
`the multistage structure ofpipelined converter systems causes
`certain portions of the converter structure to be used repeti-
`tively as an analog input signal is swept over the system’s
`input range and converter nonlinearity in these portions can
`significantly degrade the conversion of low-level dynamic
`signals.
`Conversion linearity is generally characterized with a vari-
`ety of linearity parameters such as differential nonlinearity
`(DNL),
`integral nonlinearity (INL), signal-to-noise ratio
`(SNR), signal-to-noise-and-distortion ratio (SINAD), and
`spurious free dynamic range (SFDR). DNL error indicates the
`difference between an actual step width of a least-significant
`
`bit and the ideal value while INL error measures the deviation
`
`
`
`of an actual transfer function from a straight line. SNR is
`computed by taking the ratio ofthe rms signal to the rms noise
`wherein the noise includes all spectral components minus the
`fundamental, the first four harmonics, and the DC offset.
`SINAD is the ratio (in dB) ofthe signal power to the power of
`all spectral components minus the fundamental and the DC
`offset. Finally, SFDR is the ratio of the fundamental compo-
`nent to the rms value of the next-largest spurious component
`(excluding DC offset).
`Although a variety of linearizing techniques have been
`proposed for pipelined converter
`systems,
`increasing
`demands on these systems continue to exert a need for further
`improvements in linearity.
`
`BRIEF SUMMARY OF THE INVENTION
`
`The present disclosure is generally directed to pipelined
`converter systems with enhanced linearity. The drawings and
`the following description provide an enabling disclosure and
`the appended claims particularly point out and distinctly
`claim disclosed subject matter and equivalents thereof.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagram of a pipelined converter system;
`FIG. 2 is a diagram ofa signal converter embodiment in the
`system of FIG. 1;
`FIG. 3 is a diagram of clock signals for use in the signal
`converter of FIG. 2;
`FIG. 4 is a reference signal generator which may be used in
`the system of FIG. 1;
`FIG. 5 is a transfer-function diagram that corresponds to
`the signal converter of FIG. 2;
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`FIG. 6 is a diagram of a converter system embodiment of
`the present disclosure;
`FIG. 7A illustrate transfer functions of signal-processing
`stages in the system of FIG. 6 and possible dither levels in
`these stages;
`FIG. 7B is similar to FIG. 7A and illustrates preferred
`dither levels;
`FIG. 7C illustrates comparator levels in a back-end stage
`that succeeds the stages of FIGS. 7A and 7B;
`FIGS. 8A, 8B and 8C are diagrams of a signal sampler
`embodiments for use in the system of FIG. 6;
`FIG. 9 is a diagram of a signal converter embodiment for
`use in the system of FIG. 6;
`FIG. 10 is a diagram of another converter system embodi-
`ment; and
`FIG. 11 is a diagram of a frontend signal converter embodi-
`ment for use in the system of FIG. 10.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`FIGS. 1-11 introduce signal converter system embodi-
`ments which substantially enhance conversion linearity. Sig-
`nal-processing stages of these embodiments may include an
`initial signal sampler in addition to successively-arranged
`signal converters. Typically, the signal sampler provides a
`respective analog output signal in the form of successive
`samples of a system’s analog input signal and all but a back-
`end one of the signal converters processes an analog output
`signal from a preceding one ofthe stages into a corresponding
`digital code and a respective analog output signal (i.e., a
`gained-up residue signal). The back-end signal converter pro-
`cesses an analog output signal from a preceding one of the
`stages into a corresponding digital code but has no need to
`provide a respective analog output signal.
`In different system embodiments of the disclosure, at least
`a selected one ofthe signal-processing stages is configured to
`simultaneously process two combined analog signalsithe
`system’s analog input signal and an injected analog dither
`signal. The combined signal is thus processed down ran-
`domly-selected signal-processing paths of the converter sys-
`tem to thereby induce different magnitudes and signs of INL
`errors. The errors of these processing paths are averaged to
`thereby provide significant improvements in system linearity.
`This processing, however, provides a combined digital code
`in which a first portion corresponds to the analog input signal
`and a second portion corresponds to the injected analog dither
`signal. The final system digital code is realized by subtracting
`out the second portion.
`In particular, system embodiments of the present disclo-
`sure are directed to analog-to-digital converter systems such
`as the system 20 of FIG. 1 which is formed with M succes-
`sively-arranged signal-processing stages 22 that include a
`signal sampler 24 followed by M—l successive signal con-
`verters 25. Except for a back-end signal converter 25B, each
`of the stages 22 generates a respective analog output signal
`and passes this signal to a succeeding stage for further pro-
`cessing.
`Signal conversion begins with the signal sampler 24 which
`captures samples of an analog input signal from a system
`input port 26 at a sample rate. These samples form the signal
`sampler’s respective analog output signal which is passed to
`the successive signal converters 25. All but the back-end one
`of these signal converters processes an analog output signal
`from a preceding one of the stages into a corresponding
`digital code Cdgfl and a respective analog output signal which
`is passed to the succeeding converter stage. The back-end
`signal converter 25B processes an analog output signal from
`
`Page 13
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`

`

`US 7,719,452 B2
`
`3
`a preceding one ofthe stages into a corresponding digital code
`C01th but does not form a respective analog output signal.
`The system 20 includes an aligner/corrector 27 which
`receives and temporally aligns the digital codes Cdgfl. Each
`sample from the signal sampler 24 is successively processed
`through the signal converters at the sample rate and, only after
`the aligner/corrector 27 has received the digital codes C01th
`from all of the signal converters 25, does it provide a system
`digital code at an output port 28 that corresponds to the
`original sample. The signal converters 25 are generally con-
`figured to provide redundant code bits and the additional
`conversion information in these redundant code bits is used
`
`by the aligner/corrector 27 to correct conversion errors which
`may occur when the analog input signal is near transition
`points between analog regions that correspond to adjacent
`digital codes.
`Example arrow 29 points to an exemplary embodiment 30
`of the signal converters 25. In this embodiment, an analog-
`to-digital converter (ADC) 31 converts the respective analog
`output signal of a preceding one of the stages 22 to a corre-
`sponding digital code Cdgfl. A digital-to-analog converter
`(DAC) 32 converts this digital code to a corresponding analog
`signal which is differenced with the respective analog output
`signal in a summer 33 to provide a residue signal. The residue
`signal is then “gained up” in an amplifier 34 to provide the
`respective analog output signal of the present stage. The gain
`ofthe amplifier 34 provides an analog window to the succeed-
`ing stage that substantially matches the analog window pre-
`sented to the current stage.
`Because of the above-described operation, a portion 36 of
`the signal converter embodiment 30 is generally referred to as
`a multiplying digital-to-analog converter
`(MDAC). An
`embodiment 40 of one of the signal converters of FIG. 1 is
`shown in FIG. 2. Although this embodiment could be
`arranged to convert an input signal to various numbers of
`digital bits, the embodiment 40 is shown as an 2.5 bit stage for
`illustrative purposes. It should be understood that the con-
`cepts disclosed below may be applied to signal converters that
`provide different numbers of digital bits.
`The signal converter 40 includes a switched-capacitor
`MDAC embodiment 42 and also includes a switched-capaci-
`tor signal comparator embodiment 41. The signal converter
`40 is arranged to process an analog output signal S00.) of a
`preceding one of the signal-processing stages at an input port
`44 into a corresponding digital code Cdgfl and a respective
`analog output signal So(i+1) at an output port 45.
`The signal comparator portion 41 couples a (1)1 switch and
`a signal capacitor C5 between the input port 44 and one ofa set
`of signal comparators 46. A ladder 48 (e. g., a resistive ladder)
`provides one of a plurality of comparator threshold levels to
`the signal capacitor C5 through a (1)2 switch and another (1)2
`switch couples the other side ofthe signal capacitor to ground
`(similar switch, capacitor and ladder structures are provided
`for each of the signal comparators 46 but are not shown to
`enhance drawing clarity). Finally, a decoder 49 (e.g., a latch-
`able array of digital gates) provides the corresponding digital
`code Cdgfl and a set of decision signals Dl-D4 in response to
`the set of signal comparators 45. It is noted that the signal
`comparator 41 is sometimes referred to as a flash comparator
`because all of the signal comparators operate in a common
`operational phase.
`The signal converter 40 operates at a sample rate which is
`defined by the number of clock periods that occur over an
`exemplary time interval. The timing diagram 55 of FIG. 3
`shows that the signal converter 40 of FIG. 2 operates in first
`and second operational phases (1)1 and (1)2 in each clockperiod.
`With respect to the stage of FIG. 2, the operational phases of
`
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`a preceding stage and a succeeding stage are shifted as shown
`in FIG. 3. For example, (1)1 switches of the signal comparator
`41 and (1)2 switches of preceding and succeeding stages close
`at the same times. Although clock edges are shown to tem-
`porally coincide in FIG. 3, this is for simplicity of illustration
`as these edges may be somewhat offset in various converter
`embodiments to facilitate proper operation.
`During each (1)2 operational phase of the signal converter
`40, the signal capacitor C5 is switched to charge to a ladder
`comparator level (supplied by the ladder 48 as indicated by a
`broken-line arrow) and during each succeeding (1)1 opera-
`tional phase, the signal capacitor C5 is switched to receive the
`analog output signal S00.) from a preceding one of the signal-
`processing stages. The signal at the input of the signal com-
`parator 46 thus represents a comparison ofthe signal 80(1) and
`the comparator level. In an early portion ofthe (1)1 operational
`phase, the state of the signal comparator is latched in accor-
`dance with this comparison. In response to all of the latched
`signal comparators 46, the decoder 49 thus converts the ther-
`mometer code of the comparators into the corresponding
`digital code C01th and the set of decision signals Dl-D4.
`The MDAC portion 42 ofthe signal converter 40 includes
`an amplifier 50 that provides the respective analog output
`signal S00.+ 1) ofthis stage at the output port 45 and four signal
`capacitors C1-C4 which are coupled to the amplifier. A feed-
`back capacitor Cfis coupled about the amplifier 50 and (1)1
`switches ground the input and output ofthe amplifier. A set of
`(1)1 switches couple the signal capacitors to the input port 44.
`In addition, a set of (1)2 switches couple the signal capacitors
`C1-C4 to respectively receive subrange signals D lVr-D4V,
`wherein the decision signals Dl-D4 take on values +1, 0 and
`—1 and V, is a reference voltage.
`In converter systems, it is generally advisable to use a set of
`stable reference signals throughout the system and these are
`preferably supplied by a single MDAC rcfcrcncc such as the
`reference 56 of FIG. 4. This reference provides stable and
`accurate signals Vtop and Vbot which may, for example, be 1.5
`and 0.5 volts. As shown in equations 58 in FIG. 4, these basic
`signals may be used throughout the system (20 in FIG. 1) to
`form the reference signals +V, and —V, wherein a full scale
`voltage st is the difference between these reference signals.
`The graph 60 of FIG. 5 illustrates a transfer function 62 of
`the MDAC portion 42 ofthe signal converter 40 of FIG. 2 and
`a corresponding transfer function 63 ofthe signal sampler (24
`in FIG. 1) that precedes the signal converter. To better under-
`stand the converter transfer function, attention is now directed
`to operation ofthe MDAC portion 42 ofFIG. 2. It is first noted
`that the (1)1 switches close in the (1)1 operational phase so that
`the signal capacitors C1-C4 receive charges from the analog
`output signal S00). In the (1)2 operational phase,
`the (1)2
`switches close and charges are transferred (via the gain ofthe
`amplifier 50) to the feedback capacitor Cfto thereby develop
`the analog output signal S00.+ 1) at the output port 45.
`Assuming the gain of the amplifier 50 is sufiiciently high
`and that the signal capacitors C1-C4 are sized equally to the
`feedback capacitor C], the gain of the MDAC portion 42 is
`four since the charges of four signal capacitors are transferred
`into a single feedback capacitor. This stage gain is indicated
`by an ideal reconstruct line 64 which coincides with the
`transfer function portion in a first converter subrange 65 in
`FIG. 5.
`
`As the analog output signal 80(1) of FIG. 2 decreases, the
`decision signals D 1'134 in FIG. 2 successively change from 0
`to +1 in response to the decoder 49 in the comparator portion
`41. Accordingly,
`the transfer function 62 is successively
`urged upward (away from the ideal reconstruct line 64) by the
`reference signal V, and this process generates the sawtooth-
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`

`US 7,719,452 B2
`
`5
`shaped portion of the transfer function 62 at the left side of
`FIG. 5. A similar sawtooth-shaped portion is generated in a
`similar manner at the right side of FIG. 5 as the analog output
`signal 800') increases and the decision signals Dl-D4 succes-
`sively change from 0 to —1. Thus, the MDAC portion 42 of
`FIG. 2 generates the transfer function 62 which, as shown in
`FIG. 5, has an MDAC gain of four and (as labeled in FIG. 5)
`varies over an output-signal window in each of a plurality of
`converter subranges.
`
`As the analog output signal 800') of the preceding stage
`varies from a negative maximum to a positive maximum, the
`corresponding digital code C01th from the signal comparator
`portion 41 of FIG. 2 will change accordingly as the operating
`point passes into each converter subrange of FIG. 5. If no
`processing errors occur in the MDAC portion 42 ofFIG. 2, the
`analog output signal So(i+1) plus the corresponding ones ofthe
`subrange signals D lVr-D4V, should exactly equal the analog
`output signal 800') ofthe preceding stage when it is multiplied
`by the MDAC gain of four. That is, the sum of the analog
`output signal S00.+ 1) and corresponding ones of the subrange
`signals D lVr—D4V, should produce the ideal reconstruct line
`64 which is initially formed by the analog output signal 800')
`multiplied by the MDAC gain of four.
`Fabrication errors in the MDAC portion 42 will, however,
`cause the actual reconstruct line to differ from the ideal recon-
`
`struct line 64. If the feedback capacitor Cfis smaller than
`intended, for example, MDAC charge transfer will be altered
`and the gain in each ofthe converter subranges will be greater
`than their ideal value. This gain error is indicated in FIG. 5 by
`broken lines 66 which show how the transfer function sym-
`metrically tilts in each converter subrange. The sum of the
`analog output signal 800.“) and corresponding ones of the
`subrange signals DIVV-D4V, now produce an actual recon-
`struct line 68 in which symmetrically differs from the ideal
`reconstruct line 64 in each converter subrange (for clarity of
`illustration in FIG. 5, the actual reconstruct line 68 is only
`shown in two of the converter subranges).
`The difference between the ideal reconstruct line 64 and
`
`the actual reconstruct line 68 are indicated by the integral
`nonlinearity (INL) 70 of the signal converter (40 in FIG. 2)
`which is a measure of symmetrical errors (e.g., errors due to
`the fabrication-error in the feedback capacitor C). If the
`feedback capacitor Cfis greater than intended or the gain of
`the amplifier 50 is significantly less than ideal, a similar INL
`will be introduced except that the slope in each converter
`subrange will be reversed from that shown.
`In either case, the signal converter 40 of FIG. 2 will intro-
`duce undesirable symmetrical INL errors (e.g., as exempli-
`fied by segments 74 of the INL 70) into the transfer function
`of the converter system 20 of FIG. 1. Although these sym-
`metrical transfer function errors have been described above to
`
`originate from incorrect feedback capacitor Cfsize and insuf-
`ficient amplifier gain, they can also originate from other sys-
`tem errors (e.g., signal setting errors).
`In another type of typical MDAC error that is often termed
`“DAC error”, the signal capacitor C 1 may be smaller than the
`other signal capacitors C2-C4 so that, for example, the transfer
`function in a converter subrange on the left side of the sub-
`range 65 is not urged upward as far as intended. This is
`indicated in FIG. 5 by the broken line 71 in this converter
`subranges. These asymmetrical types of MDAC errors will
`cause segments in the INL 70 to be urged up and down in
`different converter subranges so that both types of errors
`(symmetrical DAC errors and asymmetrical errors) combine
`to produce the INL 72. For example, the segment 74 in the
`
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`INL 70 has been urged downward to the segment 75 in the
`INL 72 because of the transfer function error indicated by the
`broken line 71.
`
`To substantially reduce INL errors such as those indicated
`in FIG. 5, the converter system 20 of FIG. 1 is altered to the
`system 80 of FIG. 6 which includes elements of FIG. 1 with
`like elements indicated by like reference numbers. In contrast
`to the system 20, however, the system 80 couples a pseudo-
`random (PN) generator 81, a DAC 82 and at least one asso-
`ciated dither capacitor 83 to the signal sampler 24 for injec-
`tion of dither signals.
`The PN generator 81 provides a random digital code
`wherein the number of codes is sufficient to command the
`
`DAC 82 and the dither capacitor 83 to inject a corresponding
`number of analog dither signals into an entry point A of the
`sampler 24. These injected dither signals combine with the
`input signal received at the input port 26 and. Accordingly, the
`combined signal is processed down randomly-selected sig-
`nal-processing paths of the converter system which induce
`different magnitudes and signs of INL errors. The average
`error of these processing paths is reduced to thereby provide
`significant improvements in system linearity.
`these linearity
`It
`is important
`to note, however,
`that
`improvements are realized by simultaneous processing oftwo
`combined analog signalsithe input signal at the input port
`26 and the injected dither signal. As shown in FIG. 6, this
`processing provides a combined digital code at the output of
`the aligner/corrector 27. A first portion of this combined
`digital code at the digital back-end of the signal converter
`corresponds to the analog input signal
`that was earlier
`received into the input port 26 but a second portion of the
`combined digital code corresponds to the injected analog
`dither signal. In the converter system 80, the final system
`digital code at the output port 28 is realized by subtracting out
`thc sccond portion in a diffcrcnccr 90.
`As shown in FIG. 6, the second portion is provided by a
`back-end decoder 84A which responds to the random digital
`code that was generated by the PN generator 81. The transfer
`function ofThe back-end decoder 84A has a transfer function
`which is obtained from the transfer function of the DAC 82,
`the size of the dither capacitor 83, and the transfer function of
`the system 80 between the entry pointA and the output of the
`aligner/converter 27.
`linearity
`similar
`In a different system embodiment,
`improvements are realized with dither signals that are
`injected in a selected downstream signal converter. For
`example, FIG. 6 also shows a PN generator 85, a DAC 86 and
`at least one associated dither capacitor 87 for insertion of
`analog dither signals into a signal comparator portion of a
`selected one of the signal converters. This figure also shows
`another DAC 88 and at least one associated dither capacitor
`89 for insertion of dither signals into an MDAC portion ofthe
`selected signal converter.
`The residue signal from the preceding signal converter and
`the injected dither signal are simultaneously processed along
`randomly-selected signal-processing paths that begin at the
`selected converter stage. As previously described, this pro-
`cessing provides a combined digital code. A secondportion of
`this combined digital code is removed in the differencer 90
`wherein the secondportion is provided in this embodiment by
`a back-end decoder 84B that responds to the random digital
`code of the PN generator 85. The transfer function of the
`back-end decoder 84B is determined by the transfer function
`of the DACs 86 and 88, the sizes of the dither capacitors 87
`and 89, and the transfer function ofthe system 80 between the
`selected signal converter and the output ofthe aligner/correc-
`tor 27.
`
`Page 15
`
`

`

`US 7,719,452 B2
`
`7
`Advantageous operation of these additional structures is
`investigated in FIGS. 7A-7C. In FIG. 7A, it is assumed that
`the signal converters 25 of FIG. 6 comprise an initial 2.5 bit
`stage followed by successive 1.5 bit stages and, accordingly,
`this figure shows a graph 100 which plots the analog output
`signal 101 of the 2.5 bit stage followed by plots of the analog
`output signals 102-105 of the 1.5 bit stages. It is important to
`observe that this is an exemplary embodiment as other system
`embodiments may include stages that convert various other
`combinations of code bits.
`
`As shown, a converter subrange of the 2.5 bit stage spans
`one of the converter subranges ofthe succeeding 1.5 bit stage
`and one half of each adjacent converter subrange. Similarly,
`each converter subrange of one of the 1.5 bit stages spans one
`ofthe converter subranges of the succeeding 1.5 bit stage and
`one half of each adjacent converter subrange. As exemplified
`in FIG. 5, the output-signal window ofeach stage spans VfJ2.
`The transfer function of each succeeding stage is thus limited
`to this span which leads to the arrangement of stage transfer
`functions shown in FIG. 7A.
`
`In FIG. 7A, it is assumed that the analog input signal at the
`input port 26 ofFIG. 6 is positioned so that the current analog
`output signal is at the middle point 113 ofanalog output signal
`101. It is further assumed that the PN generator 81, DAC 82
`and at least one capacitor 83 are configured to dither this
`operating point over five operating points 111, 112, 113, 114
`and 115 (in FIG. 8A, each operating point is indicated by an
`oblong marker) wherein operating points 111 and 115 coin-
`cide with the ends of the converter subrange.
`Because the analog output signal ofthis converter subrange
`spans one ofthe converter subranges ofthe succeeding 1.5 bit
`stage and one half of each adjacent converter subrange, the
`corresponding operating points in this stage lie directly below
`the operating points in the first stage. This relationship fol-
`lows through succccding stagcs so that thc dithcrcd opcrating
`points are positioned as shown in FIG. 7A (visualization of
`this relationship is facilitated by vertical broken lines 116).
`Inspection of the central converter subranges observes that
`the operating point in stage 1 is dithered over this subrange to
`thereby establish different signal processing paths through
`this stage and a lesser number of different signal processing
`paths through stage 2. Signal processing randomly flows
`along these different signal processing paths in stages 1.
`These paths will induce different magnitudes of INL errors
`having one sign and similar magnitudes of INL errors having
`a different sign. The average error of these processing paths
`will thus be substantially reduced to thereby realize signifi-
`cant
`improvements in system linearity and substantially
`improve the system’s INL. As subsequently described, the
`disturbing effects of the dither signal are removed at the
`summer 90
`
`It is apparent from FIG. 7A, however, that the operating
`point in subsequent stages 3-5 remains at the operating point
`prior to application of dither. In the third stage, for example,
`operating points such as the point 118 remain at the center of
`the converter subrange. Thus, the dither fails to alter the signal
`processing path through these latter stages. This failure is
`removed in the dither arrangements exemplified in FIGS. 7B
`and 7C.
`
`The graph 120 of FIG. 7B is similar to the graph 110 of
`FIG. 7A with like elements indicated by like reference num-
`bers. In FIG. 7B, however, it is assumed that the PN generator
`81, DAC 82 and at least one capacitor 83 have been reconfig-
`ured so that the five dithered operating points are now
`arranged so that they span substantially 4/5 of the output-
`signal window, i.e., the span between operating points 111
`and 115 is substantially 4/5 of the output-signal window.
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`At this point, attention is temporarily redirected to FIG. 5 to
`thereby better review the definition of some important trans-
`fer function terms. The five dithered operating points (of FIG.
`7B) are shown collectively as a set 122 in one ofthe converter
`subranges of FIG. 5. As mentioned previously, the transfer
`function of this stage moves over an output-signal window in
`each of a plurality of converter subranges. The output-signal
`window is sufficiently reduced (e. g., it spans VfS/2) from the
`full scale voltage st to establish correction ranges which
`accommodate extensions of the transfer function when its
`
`amplide alters because of various conversion errors (e.g.,
`threshold errors in flash comparators). As shown in FIG. 5, the
`total span of the set 122 of operating points is now slightly
`reduced from the output