1904
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL, 33, NO. 12, DECEMBER 1998
`
`A Digital Background Calibration Technique for
`Time—Interleaved Analog-to-Digital Converters
`
`Daihong Fu, Kenneth C. Dyer, Student Member, IEEE,
`Stephen H. Lewis, Senior Member, IEEE, and Paul J . Hurst, Senior Member, IEEE
`
`two-channel parallel
`40—Msample/s
`Abstract— A 10—bit
`pipelined ADC with monolithic digital background calibration
`has been designed and fabricated in a 1- pm CMOS technology.
`Adaptive signal processing and extra resolution in each channel
`are used to do digital background calibration. Test results show
`that the ADC achieves a signal-to—noise-and—distortion ratio of 55
`dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity
`of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB,
`both at a 10-bit level. The active area is 42 mmz, and the power
`dissipation is 565 mW from a 5-V supply.
`
`
`
`2
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`Index Terms—Adaptive systems, analog—digital conversion, cal-
`ibration, CMOS analog integrated circuits.
`
`1.
`
`INTRODUCTION
`
`HE throughput rate of digital signal processing sys-
`Ttems operating on analog inputs is often limited by the
`speed of the analog-to-digital (A/D) interface. To increase
`the speed beyond the technological limit, the A/D interface
`can consist of more than one component analog-to-digital
`converter (ADC) interleaved in time. The performance of time-
`interleaved ADC’s, however, is degraded by mismatches in the
`transfer characteristics of the component ADC’s [1]—[8]. These
`mismatches include offset, gain, and aperture mismatches that
`would not limit linearity without interleaving. Trimming or
`calibration are traditionally used to overcome this problem.
`Trimming has the advantage of being transparent to the user
`but the disadvantage of being unable to track variations over
`time. On the other hand, while calibration can be used to
`track variations over time, traditional calibration techniques are
`applied in the foreground; that is, the calibration interrupts the
`conversion of the input. Foreground calibration is inconvenient
`for ADC users and cannot be used in applications where
`the converter is always in service. Also, calibration in the
`foreground may generate interference that disappears during
`normal converter operation, resulting in calibration errors.
`This paper presents a time-interleaved pipelined ADC that
`uses monolithic digital background calibration techniques to
`overcome the effects of the offset and gain mismatches be-
`tween channels without
`interrupting the conversion of the
`input. Monolithic background calibration is not a new concept.
`
`Manuscript received April 5, 1998; revised July 25, 1998. This work was
`supported by UC MICRO Grant 96-008 and by NSF Grant MIP-921007l.
`D. Fu was with the University of California, Davis, CA 95616 USA. She
`is now with Maxim Integrated Products, Sunnyvale, CA 94086 USA.
`K. C. Dyer, S. H. Lewis, and P. J. Hurst are with the Solid-State Circuits
`Research Laboratory, Department of Electrical and Computer Engineering,
`University of California, Davis, CA 95616 USA.
`Publisher Item Identifier S 0018-9200(98)08860-X.
`
`
`
`Fig. 1. Block diagram of M time-interleaved ADC’s.
`
`M
`
`It has been used to linearize multistage ADC’s using CMOS
`[9] and bipolar technologies [10]. Also,
`the “skip-and-fill”
`algorithm has been proposed [ll], [12] to allow background
`calibration by occasionally skipping the conversion of an
`input sample and substituting a sample of a calibration signal
`instead. Then the missing ADC output is filled in through
`nonlinear interpolation. The main contributions in this paper
`are the use of digital background calibration to overcome
`the offset-mismatch and gain-mismatch errors arising in time-
`interleaved ADC’s and the implementation of these techniques
`in conjunction with the ADC’s on one CMOS integrated
`circuit. This paper is divided into five additional sections.
`Section II gives a brief review of time-interleaved ADC’s and
`their limitations. Section III shows how the mismatch problem
`can be overcome by using a digital background calibration
`technique. In Section IV, the implementation of the prototype
`is described. Experimental results are given in Section V, and
`Section VI presents a summary.
`
`11. REVIEW OF TIME-INTERLEAVED ADC’s
`
`shows a simplified block diagram of a time-
`Fig. 1
`interleaved ADC. It consists of M ADC’s in parallel, an
`analog demultiplexer at the input, and a digital multiplexer at
`the output. Each ADC operates at the overall sampling rate
`fS divided by M. During operation, the analog demultiplexer
`selects each ADC in turn to process the input signal. The
`corresponding digital multiplexer selects the digital output of
`each ADC periodically and forms a high-speed ADC output.
`With interleaving, the overall sampling rate is f,, which is
`M times higher than the sampling rate of the ADC in each
`channel. The required die area and power dissipation are also
`increased by a factor of about M.
`Unfortunately, the performance of interleaved ADC’s is sen-
`sitive to mismatches between the individual channels [l]—[8].
`Channel offset mismatches cause additive tones at
`integer
`
`001879200/98$10.00 © 1998 IEEE
`
`
`Xilinx Exhibit 1005
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from IEEE Xplore. Restrictions apply.
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`FU et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE
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`multiples of the channel sampling rate fS/M. Channel gain
`mismatches result in amplitude modulation of the input sam-
`ples, causing scaled copies of the input spectrum to appear
`centered around integer multiples of the channel sampling rate.
`Errors in the sample times result in phase modulation of the
`input samples, which also causes scaled copies of the input
`spectrum to appear centered at the same frequencies as the
`spurious components stemming from gain mismatch. All these
`mismatches increase the noise floor of the ADC system and
`degrade the signal-to-noise ratio [6].
`Extensive work at the board level has been done to over-
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`1905
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`Fig. 2. The gain calibration loop.
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`multiplier with variable gain G determined by the adaptive
`loop, and a digital accumulator. The sequence N generated
`by the pseudo-RNG is binary and approximately white. It has
`zero mean and is uncorrelated with the input signal S. During
`calibration, the random number is converted to an analog noise
`through the 1-bit DAC and is added to the input of the ADC.
`The same random number is then subtracted at the output, and
`the difference 6 is taken as the ADC final output. Then 6 is
`multiplied by N, scaled by a small negative number (—Mgain),
`and accumulated to determine the gain G through feedback.
`In practice, again > 0; therefore, the feedback is negative.
`To simplify the analysis, a linear model is used in which
`the ADC and DAC are represented as amplifiers with gains
`GA and GD, respectively. Consider the two paths from the
`RNG to the inputs of the subtracter that computes e. If the
`random-number gain in one path (which is GD X GA times
`the variable gain G) does not equal the random-number gain in
`the other path (which is one), the subtraction of the calibration
`signal is not complete at the output, leaving a random-number
`residue in 5. In general, 5 includes the sum of two parts: one
`is related to the input signal S, the other is related to the
`random-number residue. When 5 is multiplied by the random
`number N, the term that contains the product of S and N
`is averaged out by the accumulator since the random number
`is uncorrelated with the input signal. However, the term that
`contains N 2 : 1 has a nonzero mean value and will produce
`a nonzero output from the digital accumulator. The key of
`the scheme is that the adaptive algorithm updates the variable
`gain G through negative feedback. If the digital accumulator
`is ideal, its dc gain is infinite and the negative feedback will
`force its input to be zero mean. This occurs when the average
`random-number residue in e is driven to zero, or equivalently
`when the average gain applied to the random number in the
`path through the ADC (GD >< GA times the average G) equals
`one.
`
`In the above adaptive system, the least-mean square (LMS)
`algorithm is applied [19]. The equations that are used to
`compute the variable gain G are
`
`Gin + 1] = Gin} — Mgaianan]
`
`(1)
`
`and
`
`E[7‘L] : GAG[71]S[71] —l— GDGAG[71]N[71] — N[n]
`
`(2)
`
`where n is a discrete-time index and again is the update step
`size. Substituting (2) into (1) and using N 2[n] = 1 because
`
`come the effects of offset, gain, and aperture mismatches
`in time-interleaved ADC’s [l3]—[l6]. At a monolithic level,
`in addition to the traditional
`techniques of trimming and
`foreground calibration, digital filtering [7] and interleaving of
`least-significant bits (LSB’s) [8] have been used. The concept
`of interleaving LSB’s is that only the hardware for the LSB’s
`is interleaved, eliminating potential mismatch in the most-
`significant bit (MSB) hardware. The main limitation of this
`approach is that the MSB hardware must operate at the fill]
`conversion rate of the entire ADC system, potentially limiting
`the maximum conversion rate. Although digital filtering over-
`comes this limitation, it poses a new limitation on the input
`bandwidth. When digital filtering is applied to two ADC’s in
`parallel, a digital low-pass filter with a single zero at fS / 2
`is used to process the outputs of the interleaved ADC’s [7].
`This filter not only eliminates the offset mismatch tone, but
`also reduces the timing and gain mismatch tones. The main
`disadvantage of this approach is that it reduces the maximum
`input frequency by a factor equal to the number of channels
`that are interleaved. To overcome the limitations of all these
`
`techniques, background calibration can be used so that the
`calibration runs all the time without interrupting the conversion
`of the input.
`
`III. DIGITAL BACKGROUND CALIBRATION
`
`One way to do background calibration in a time-interleaved
`ADC is to add an extra parallel channel so that one channel
`can be calibrated while the others operate in a time-interleaved
`fashion [17]. The channel undergoing calibration at any given
`time can be rotated so that all channels are periodically
`calibrated. This approach requires (M +1) channels to increase
`the conversion rate by a factor of M. To eliminate the need
`for an extra parallel channel
`to do the calibration in the
`background, background calibration is done here by adding
`a calibration signal to the ADC input and processing both
`simultaneously [18].
`First, consider a technique that allows background calibra-
`tion of the gain of each channel in a time-interleaved ADC.
`The concept is as follows: if the channel gain of one ADC
`can be forced to equal a desired value by some method, then
`this method can be applied to every ADC in the parallel array
`to force all the ADC channels in the array to have the same
`desired gain value (and therefore to match each other). Fig. 2
`shows the adaptive system used to calibrate the gain of one
`ADC. The key blocks are: a pseudorandom number generator
`(RNG), a 1-bit DAC, the ADC under calibration, a digital
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from lEEE Xplore. Restrictions apply.
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`

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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
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`Analog
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`Digital
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`Fig. 3. Gain calibration system for two time-interleaved ADC’s.
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`1906
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`G[7l + 1] = G[7'L] + ”gain _ MgainGAGDG[n]
`
`— ugamGAGlnlNlnlSlnl-
`
`(3)
`
`Taking the expected value of both sides of (3) causes the last
`term in (3) to go to zero because the noise N [n] and the input
`signal S [n] are uncorrelated and N [n] is zero mean. Therefore
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`m = Mgain + Ganl — ugamGAGD).
`
`(4)
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`If the mean of the variable gain G [n] converges, then
`
`12am: .122. W
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`Substituting (5) into (4) gives
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`fl =
`
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`1
`GD GA
`
`.
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`<s>
`
`(6)
`
`— l
`GAGI:OO] I G—D .
`
`(7)
`
`In practice, (4), (6), and (7) are approximate because pseudo-
`RNG’s produce repeating binary sequences with odd lengths
`and therefore only approximately zero mean. Because the
`mean output of the RNG used on the prototype is very small
`(2’39), however, these equations are nearly exact. Note that
`the gain G is not constant in steady state. Instead, it contains
`a random fluctuation around its mean of 5 caused by the
`term involving the product of the input and the calibration
`signal in (3). Because this term is accumulated, however, it
`can be made arbitrarily small by reducing the step size again.
`Although reducing the step size increases the time required
`to reach convergence [20], a small step size also assures the
`stability of the gain calibration loop [19].
`A potential advantage of processing the calibration signal
`and the ADC input simultaneously in the gain calibration
`scheme is that the RNG signal added to the ADC inputs acts
`as dither and improves the linearity of the system [10].
`Applying the above gain calibration scheme directly to each
`ADC in the time-interleaved array with two channels gives the
`gain calibration system shown in Fig. 3. The system contains
`two identical loops. As shown in (7), the top loop forces the
`gain of the first ADC channel equal to 1 / GD in the mean.
`Likewise, the bottom loop forces the gain of the second ADC
`channel equal to 1 / GD in the mean. So in steady state, the
`gains of the two ADC channels match each other. In this
`implementation, however, two multibit digital multipliers are
`needed for scaling by G1 and G2 in the two ADC paths. The
`implementation can be simplified by pushing one multiplier
`from the ADC path to the RNG path.
`Fig. 4 shows the modified gain calibration system. The
`multibit digital multiplier that was in the first ADC path in
`Fig. 3 is pushed to the RNG path here. As a result, one
`
`
`Therefore, as n —> 00, the average path gain in steady state
`(GDGAG[oo]) is unity, and the average noise power added
`at the input is completely removed at the output. Finally, the
`average steady-state gain of the calibrated ADC path is
`
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`Fig. 4. Modified gain calibration system for two time-interleaved ADC’s.
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`Fig. 5. Offset calibration system for two time-interleaved ADC’s.
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`input of the G1 multiplier is 1 bit wide here, simplifying the
`implementation of this multiplier. Therefore, the modified gain
`calibration system needs only one multibit digital multiplier to
`operate on two multibit ADC outputs. The average gains, 51
`and 52, converge to values that remove the calibration signal
`deliberately injected into the ADC inputs; that is
`
`(8)
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`61 = GDGAl
`GAl
`—
`a1
`9
`G =— = —.
`( )
`2
`GA2GD
`GA2
`A disadvantage of the modification in Fig. 4 is that it increases
`the time required to reach convergence because G2 can only
`converge after G1.
`Fig. 5 shows the block diagram of the adaptive offset
`calibration hardware for a case with two interleaved channels.
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from IEEE Xplore. Restrictions apply.
`
`

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`FU et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE
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`Analog
`Input
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`Output
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`D'
`lgltal
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`Fig. 7.
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`Fig. 6. Block diagram of prototype with two channels.
`
`The sequences 51 and 52 are the outputs of the gain calibration
`system shown in Fig. 4. Each sequence contains the input
`signal and the offset of the associated ADC, but the gain-
`mismatch terms are eliminated by the calibration shown in
`Fig. 4. Let V051 and V052 represent the output-referred offset
`codes of the two ADC’s, respectively. A variable offset 0 is
`added to the gain-corrected output of ADCQ, and the result
`is subtracted from the ADCl output. The difference is scaled
`by Home, and accumulated to determine 0. If the step size
`Monset
`is small, the average offset correction 5 converges to
`a value that makes the average accumulator update equal to
`zero; that is
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`O : l/osl _ l/OSQ-
`
`(10)
`
`the average offsets of the interleaved
`After convergence,
`channels are equalized. Again, the random component of the
`offset arising from noise in the adaptive system can be made
`arbitrarily small by reducing the step size uofiset.
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`IV.
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`IMPLEMENTATION OF THE PROTOTYPE
`
`Fig. 8. Opamp schematic.
`
`the system per-
`Since digital noise coupling may limit
`formance when digital calibration techniques are used, a
`meaningful study of these digital background calibration tech-
`niques requires a monolithic implementation. Therefore,
`to
`demonstrate the capabilities and limitations of the digital
`background calibration techniques, a prototype of two ADC’s
`in parallel with monolithic digital background calibration was
`designed and fabricated in a 1-/.Lm CMOS technology.
`Fig. 6 shows the block diagram of the adaptively calibrated
`time-interleaved ADC prototype. It consists of a front-rank
`sample-and-hold amplifier (SHA), an analog demultiplexer,
`two ADC’s in parallel, the gain and offset calibration systems,
`a digital multiplexer, an RNG, and a 1-bit DAC. The front-
`rank SHA operates at
`the system sampling rate f,.
`It
`is
`used to reduce the sample-time mismatch between the two
`ADC channels [13]. The offset-calibration and gain-calibration
`systems force the offset and gain of the second ADC channel to
`match the offset and gain of the first ADC channel. Although
`any type of ADC can be used in the parallel array,
`the
`pipelined structure is used on the prototype because of its
`high throughput rate and small hardware cost. It also has large
`tolerance to nonidealities when digital redundancy is used.
`Fig. 7 shows a block diagram of one pipelined ADC. Each
`stage has a resolution of 1.5 bits [21]. The goal was to achieve
`lO-bit performance in the parallel ADC. The amplitude of
`the background calibration signal is one quarter of the full-
`scale reference level for the converter. Therefore, to detect
`errors that occur at
`the 10-bit
`level,
`the A/D converters
`must have at least 12-bit resolution. Although system-level
`
`simulations showed that 12-bit resolution would be adequate,
`each pipelined converter on the prototype was designed so
`that it could be programmed to operate with 13-bit or 14-
`bit resolution to decrease the sensitivity to digital truncation
`errors. Testing reveals that 13-bit resolution in each ADC is
`adequate. Capacitor matching to a 10.5-bit level is required to
`reach a signal-to-distortion ratio of 60 dB.
`The design of the operational amplifiers (opamps) in a
`pipelined ADC is critical because they limit the speed and
`the accuracy of the ADC. If all the stages are identical, the
`loop gain in each interstage amplifier should be more than
`210 or about 1000 to keep the peak integral and differential
`nonlinearities less than 0.5 LSB at a 10—bit
`level. If the
`
`the required open-loop gain in the
`feedback factor is 1/3,
`Opamp is about 3000. Also, to reach a conversion rate of 40
`Msample/s with two interleaved channels, the opamps must
`settle to 0.05% accuracy in less than 25 ns. Therefore, the
`Opamp needs both high gain and bandwidth, and a telescopic
`cascode configuration is used to meet these objectives [22].
`Fig. 8 shows a schematic of the double-cascode Opamp. Input
`source followers are used to reduce the input capacitance and
`increase the feedback factor and the closed-loop bandwidth
`[23]. Although the input buffer introduces an extra pole, it can
`be pushed well beyond the unity-gain frequency of the Opamp
`by design.
`To minimize die area and power dissipation, the opamps
`in a pipelined ADC can be scaled down in each stage [24],
`[25]. However, this approach requires a long design time to
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from IEEE Xplore. Restrictions apply.
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`1908
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`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
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`Digital
`16b 81
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`Fig. 9. Adaptive digital background calibration system.
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`Fig. 10. Die photo of the prototype.
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`optimize each stage. To reduce design time, only two opamp
`sizes are used on the prototype. According to simulation, in
`the first three stages of each pipelined ADC, each opamp has
`a gain of 83 dB and a settling time of 22 ns to 0.05% accuracy
`with a 4-V differential output change into a 3-pF load. In the
`last 10 stages of each pipelined ADC, each opamp has a gain
`of 78 dB and its output settles in 22 us to 0.1% accuracy
`with 4-V differential output into a 1.8-pF load. Designing an
`opamp with a higher open-loop gain than is needed assures
`that capacitor mismatch limits the ADC linearity.
`Another important circuit cell in a pipelined ADC is the
`comparator. With digital correction and 1.5-bit resolution per
`stage, a low-offset comparator is not required. As a result,
`a dynamic comparator with built-in mismatch to set
`the
`threshold is used [24]. This comparator has zero dc power
`dissipation and eliminates the need for sampling capacitors in
`front of each comparator.
`A key block in the gain-calibration system is the pseudo-
`RNG. At a rate fS/Z it generates a binary sequence that is
`white and uncorrelated with the input signal. The RNG is
`implemented on chip and uses a maximum-length shift-register
`structure with 39 stages in the shift register [26].
`Fig. 9 shows the digital background calibration system with
`details on the digital blocks. The multiplier, adders, and
`accumulators use parallel structures. They consume most of
`the digital area and digital power. Some fairly big digital
`cells are used. For example, a 14 X 9 digital multiplier,
`a 43-bit accumulator, and a 38-bit accumulator are used in
`the gain-calibration system. In the offset-calibration system, a
`44-bit accumulator is used. The need for wide accumulators
`
`is created by the large number of bits in the ADC outputs
`and the need to use small step sizes again and uoqset. Small
`step sizes are required to keep the variation of the gain and
`offset correction terms small enough to avoid performance
`limitations in steady state. The smallest step size is 2’28. In
`the prototype, the values of the step size used in the calibration
`system are programmable. Any four step sizes out of the eight
`values {241, 2‘22, ---, 2‘28} can be used during operation
`of the system. M1-M4 are the step sizes that are used during the
`calibration, and t, (i : 1, 2,3) is the time that the step size
`changes from [.L, to M44. The four u,’s that are selected and
`the three t,’s are set externally. This programmability allows
`
`the prototype to start calibration with a relatively big step size
`and end up with a very small one in steady state to improve
`the convergence time while maintaining high accuracy after
`convergence. The convergence time of the calibration system
`is about 3 s when only the smallest step size is used and
`can be about half of that
`time when using variable step
`sizes.
`
`An important cell in the digital calibration system is the
`full adder. It is the basic cell in the adders, accumulators, and
`multipliers and uses the schematic shown by Suzuki et a]. [27].
`The logic gates in the full adder are implemented by using the
`differential-cascode voltage-switch-with-pass-gate (DCVSPG)
`logic family [28]. DCVSPG logic has the advantages of being
`fast and small while consuming little power. Parallel structures
`are used for the adders and accumulators in the digital system
`[29]. For an N-bit adder, N full adders are used. Also, the
`14 X 9 multiplier in the gain calibration loop uses a parallel
`structure [30] that uses 84 full adders.
`Fig. 10 shows the die photo of the prototype. It is fabricated
`in a 1-/.Lm CMOS technology that has poly-over—diffusion
`capacitors and two layers of metal. The dimensions of the
`prototype are about 9 mm X 6 mm. The die area is 54 mm2,
`and the active area is 42 mm2. The digital calibration circuits
`occupy 20 m2, which is about half of the active area. To
`reduce the digital noise coupling, the front-rank SHA, the bias
`network, and the two ADC’s are on one side of the chip and
`the digital calibration circuits are on the other side, so the
`analog and digital parts are separated from each other. The
`middle triangular-shaped block is used to program the step
`sizes used in the calibration loops. When the step sizes are
`constant, the signals in the step-size programming block are
`all do signals, so this block further isolates the analog and the
`digital sections on the prototype.
`
`V. EXPERIMENTAL RESULTS
`
`Fig. 11 shows the ADC output spectrum before calibration.
`The sampling rate is 40 Msample/s. The input signal frequency
`is 0.8 MHz. The input signal amplitude is 3 Vp-p, which is
`75% of the full scale. The other 25% of the full scale is saved
`
`for the calibration signal, which is not applied in the case of
`Fig. 11. The y-axis in Fig. 11 is normalized so that the input
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from IEEE Xplore. Restrictions apply.
`
`

`

`FU et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE
`
`
`
`
`
`
`
`
`
`
`
`20 \ Input Signal OdB
`
`Offset Mismatch Tone —46dB
`‘
`Gain Mismatch Tone —62dB\
`_
`nd
`-40
`2 HD 64dB
`Amp
`3rd HD —68dB
`\
`-60 6/
`
`1909
`
`Conversion Rate = 4OMsample/s
`Input Sine Wave Amplitude = 3Vp—p
`
`60
`
`-3—dB Threshold
`
`55
`
`SNDR
`(dB) so
`
`45
`
`40 35
`
`Fig. 13.
`
`Signal-to-noise-and-distortion ratio versus input frequency.
`
`Input Frequency (MHz)
`
`the offset calibration loop. The SNDR in Fig. 13 is decreased
`by 3 dB from its maximum value when the input frequency is
`8 MHz. In contrast, the SNDR of another time-interleaved
`ADC with an identical front-rank SHA is decreased by 3
`dB from its maximum value when the input frequency is
`21 MHz [31]. This difference is believed to be caused by
`digital noise from the calibration circuits coupling through
`the substrate in the prototype described in this paper. (In
`the related project, the calibration circuits operate mostly in
`the analog domain, reducing the noise [31].) The substrate
`noise-coupling mechanism is described next.
`The front-rank SHA operates at a 40-Msample/s clock
`rate. The input
`is sampled in the front-rank SHA on the
`falling edge of the sampling clock. Since two ADC’s are
`interleaved, each ADC channel produces outputs at a rate
`of 20 Msample/s, and the digital calibration circuits operate
`on the ADC outputs at this rate. All the digital circuits are
`clocked by one edge of a 20-MHz clock. Therefore,
`the
`digital calibration circuits are clocked at a time that is closer
`to the sampling time of one of the ADC’s than the other.
`As a result, digital noise has a greater impact on the exact
`sampling instant of one of the ADC’s, and therefore causes
`sample-time jitter between consecutive sampling instants. Any
`resulting mismatch between the two consecutive sampling
`times introduces sample-time jitter between ADC]L and ADC2.
`Such jitter increases the slope at which the SNDR falls in
`Fig. 13. Reducing this digital noise coupling is a topic for
`future research.
`
`Figs. 14 and 15 show the differential nonlinearity and
`integral nonlinearity (DNL and INL) of the prototype, respec-
`tively. The maximum DNL is 0.14 LSB, and the maximum
`INL is 0.34 LSB, both at a 10-bit level. Only three quarters of
`the input range is tested because the calibration signal occupies
`the other one quarter of the input range.
`Table I summarizes the measured performance.
`
`VI.
`
`SUMMARY
`
`This paper shows that digital background calibration is of
`potential interest to reduce the effects of mismatch in time-
`interleaved A/D converters.
`
`—120 -140
`
`O
`
`5
`
`10
`
`20
`15
`Frequency (MHz)
`
`Fig. 11. ADC output spectrum without calibration.
`
`0
`
`\Input Signal OdB
`
`‘20
`
`Offset Mismatch Tone -87dB
`
`40
`Amp
`
`2nd HD _73dB Gain Mismatch Tone -72dB
`d
`
`(dB) / 3r HD ~72dB
`
`—60 /
`—80
`
`—140 15
`
`-100
`
`—120 l
`
`20
`
`Fig. 12. ADC output spectrum with calibration.
`
`Frequency (MHZ)
`
`amplitude is 0 dB. The tone caused by offset mismatch is
`at the channel sampling rate 20 MHz and is 46 dB below
`the fundamental. The tone caused by gain mismatch is at the
`channel sampling rate 20 MHz minus the input frequency 0.8
`MHz and is 62 dB below the fundamental. The second-order
`
`harmonic distortion is 64 dB below the fundamental, and the
`third-order harmonic distortion is 68 dB below the fundamen-
`
`tal. The signal-to-noise-and-distortion ratio (SNDR) is 45 dB,
`and the spurious-free dynamic range (SFDR) is 46 dB.
`Fig. 12 shows the ADC output spectrum with calibration
`active (after convergence). The input signal is the same as
`in Fig. 11. The offset-mismatch tone is 87 dB below the
`fundamental, which is reduced by 41 dB compared to Fig. 10.
`The gain mismatch tone is 72 dB below the fundamental,
`which is reduced by 10 dB. The second and third harmonic-
`distortion tones are also reduced because of the dither effect of
`
`the calibration signal. The SNDR is 55 dB, which is increased
`by 10 dB, and the SFDR is 72 dB, which is increased by 26 dB.
`Fig. 13 is a plot of SNDR versus input frequency. Testing
`was not done near 20 MHz because this frequency appears
`as an offset mismatch between the two ADC channels and
`
`is removed by the calibration system. The width of the gap
`around 20 MHZ is proportional to the step size uofiset used in
`
`Authorized licensed use limited to: Benjamin Nise. Downloaded on April 01,2020 at 21:47:37 UTC from lEEE Xplore. Restrictions apply.
`
`

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`1910
`
`05
`
`025
`
`DNL(LSB) o
`
`—0.25
`
`-0.5
`0.5
`
`Vin/Vref
`
`IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998
`
`of area and power dissipation to implement monolithic back-
`ground calibration is expected to scale dramatically in scaled
`technologies.
`
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