UNITED STATES PATENT AND TRADEMARK OFFICE
`_____________________________________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________________________________
`
`XILINX, INC. and XILINX ASIA PACIFIC PTE. LTD.,
`Petitioner,
`v.
`ANALOG DEVICES, INC.,
`Patent Owner.
`_____________________________________
`
`Case No. IPR2020-01561
`Patent No. 7,719,452
`____________________________________
`
`DECLARATION OF UN-KU MOON, PH.D.
`U.S. PATENT NO. 7,719,452
`SUPPORTING THE VALIDITY OF CLAIMS 1–4, 8-9, 12-16, and 19-20
`
`Xilinx v. Analog
`IPR2020-01561
`Analog 2002
`
`

`

`TABLE OF CONTENTS
`INTRODUCTION ........................................................................................... 4 
`I. 
`II. 
`QUALIFICATIONS AND PROFESSIONAL EXPERIENCE ...................... 4 
`III.  MATERIALS CONSIDERED ........................................................................ 7 
`IV.  LEVEL OF ORDINARY SKILL IN THE ART ............................................. 7 
`V. 
`TECHNICAL BACKGROUND ..................................................................... 8 
`A. 
`Pipelined ADC Architecture ................................................................. 8 
`B. 
`Linearization Dither in a Pipelined ADC ............................................ 15 
`VI.  THE CLAIMED INVENTION ..................................................................... 19 
`A.  Overview of the Invention ................................................................... 19 
`B. 
`The Problem of Dither Exhaustion ..................................................... 19 
`C. 
`The ’452 Solution ................................................................................ 29 
`VII.  CLAIM CONSTRUCTION .......................................................................... 35 
`A. 
`“Said Samples Thus Processed Along Different Signal-
`Processing Paths of Said Signal Converters” [claims 1 and 13] ......... 35 
`VIII.  PETITIONER HAS NOT ESTABLISHED THAT CLAIMS 1-2, 8-9,
`AND 13-16 ARE OBVIOUS OVER CESURA (GROUND A) ................... 37 
`A. 
`Cesura Overview ................................................................................. 38 
`B. 
`Cesura does not teach or suggest processing dither through all
`the signal converters in an ADC system ............................................. 42 
`1. 
`Cesura does not teach or suggest a “digital to analog
`converter configured to … inject corresponding analog
`dither signals… to enable said selected signal converter
`and succeeding signal converters to successively process
`said analog dither signals” [Limitations 1D and 13C] .............. 42 
`Cesura does not teach or suggest “said samples thus
`processed along different signal-processing paths of said
`signal converters.” [Limitations 1G and 13F] .......................... 43 
`Cesura does not teach or suggest “an aligner/corrector . . . to
`process said plurality of digital codes into a combined digital
`code” [Limitations 1E and 13D] ......................................................... 44 
`Cesura does not teach or suggest “a decoder having a transfer
`function configured to convert said random digital code to said
`
`D. 
`
`2. 
`
`C. 
`
`1
`
`

`

`2. 
`
`3. 
`
`X. 
`
`second portion for differencing with said combined digital
`code” [Limitations 1F and 13E] .......................................................... 46 
`1. 
`Petitioner takes inconsistent positions regarding what it
`asserts is the claimed “second portion” .................................... 48 
`Cesura does not determine a “differenc[e]” between the
`alleged “combined digital code” and the alleged “second
`oortion” ..................................................................................... 50 
`Cesura does not teach a decoder having a transfer
`function “to convert said random digital code to said
`second portion” ......................................................................... 52 
`Claims 2 and 14 ................................................................................... 53 
`E. 
`Claims 8, 9, 15, and 16 ........................................................................ 54 
`F. 
`IX.  PETITIONER HAS NOT ESTABLISHED THAT CLAIMS 12 AND
`19-20 ARE OBVIOUS OVER CESURA IN VIEW OF LEWIS AND
`BJORNSEN (GROUND B) ........................................................................... 54 
`PETITIONER HAS NOT ESTABLISHED THAT CLAIMS 1-4, 8-9,
`AND 13-16 ARE OBVIOUS OVER FU IN VIEW OF LEWIS
`(GROUND C) ................................................................................................ 55 
`A. 
`Fu Overview ........................................................................................ 56 
`B. 
`Lewis Overview .................................................................................. 59 
`C. 
`Fu in view of Lewis does not teach or suggest “digital to analog
`converter configured to … inject corresponding analog dither
`signals… to enable said selected signal converter and
`succeeding signal converters to successively process said
`analog dither signals” [Limitations 1D and 13C] ............................... 60 
`Fu in view of Lewis does not teach or suggest “said samples
`thus processed along different signal-processing paths of said
`signal converters.” [Limitations 1G and 13F] ..................................... 61 
`Fu in view of Lewis does not teach or suggest “inject[ing]
`corresponding analog dither signals into at least a selected one
`of said signal converters” [Limitation 13C] ........................................ 62 
`Claims 2-4, 8-9, and 14-16 .................................................................. 65 
`F. 
`XI.  PETITIONER HAS NOT ESTABLISHED THAT CLAIMS 12 AND
`19-20 ARE OBVIOUS OVER FU IN VIEW OF LEWIS AND
`BJORNSEN (GROUND D) .......................................................................... 65 
`
`D. 
`
`E. 
`
`2
`
`

`

`XII.  AVAILABILITY FOR CROSS EXAMINATION ....................................... 65 
`XIII.  RIGHT TO SUPPLEMENT .......................................................................... 66 
`XIV.  CONCLUSION .............................................................................................. 66 
`
`
`3
`
`

`

`I, Un-Ku Moon, declare as follows:
`
`I.
`
`INTRODUCTION
`1. My name is Un-Ku Moon. I am a Professor in the School of Electrical
`
`Engineering and Computer Science, Oregon State University.
`
`2.
`
`I have been retained as an expert in this proceeding by counsel for
`
`Analog Devices, Inc. As this stage in the proceeding, I have been asked for my
`
`expert conclusions only with respect to the specific issues set forth herein that
`
`relate to the prior art references cited by Petitioner in its Petition challenging the
`
`validity of claims 1–4, 8-9, 12-16, and 19-20 of U.S. Patent No. 7,719,452 (Ex.
`
`1001 (the “ʼ452 patent”)).
`
`II. QUALIFICATIONS AND PROFESSIONAL EXPERIENCE
`3. My qualifications are stated more fully in my curriculum vitae, which
`
`is attached as Exhibit A. Below is a summary of my education, work experience,
`
`and other qualifications..
`
`4.
`
`I received a bachelor’s degree in electrical engineering from
`
`University of Washington in 1987. I then received an M.Eng. degree in Electrical
`
`Engineering from Cornell University in 1989, and I went on to receive a Ph.D. in
`
`Electrical Engineering from University of Illinois, Urbana-Champaign in 1994
`
`5.
`
`Throughout the course of my education, including my B.S., M.Eng.,
`
`4
`
`

`

`and Ph.D. degrees, I was involved in designing and implementing analog circuits.
`
`For example, during my Ph.D., I designed highly linear and tunable continuous
`
`time filters.
`
`6.
`
`After completing my Ph.D. in 1994, I joined Bell Laboratories as a
`
`Member of Technical Staff, where I continued to focus on designing and
`
`implementing analog circuits. For example, at Bell Laboratories, I designed metal-
`
`oxide-semiconductor (MOS) telecommunications circuits. I subsequently joined
`
`the faculty of Oregon State University in 1998 as an assistant professor. I was
`
`promoted to the tenured position of associate professor in 2003, and in 2005, I was
`
`promoted to my current role as a full professor.
`
`7.
`
`At Oregon State University, I lead a research group focused on the
`
`design and implementation of analog and mixed-signal integrated circuits,
`
`including high-frequency switched-capacitor filters, low-voltage switched-
`
`capacitor circuits, high-resolution and oversampling data converters, and highly
`
`linear continuous-time filters.
`
`8.
`
`A major focus of my research has been on analog-to-digital converters
`
`(ADCs). I have authored or co-authored about 300 technical papers in
`
`international journals and conferences and have been named an inventor or co-
`
`inventor on seven patents. Many of these publications cover aspects of analog
`
`circuits, and I estimate that more than half of them specifically relate to ADCs.
`
`5
`
`

`

`9. My contributions to the field of analog circuits have been recognized
`
`in a variety of ways. For example, from 2010-2013, I served as editor-in-chief of
`
`the IEEE Journal of Solid-State Circuits, which is recognized as the most
`
`prestigious journal in the field of integrated circuits. I previously served as an
`
`associate editor of the journal from 2005-2008. I have also received four best
`
`paper awards at international conferences and was twice awarded the Best Project
`
`Award from the NSF Center for Design of Analog-Digital Integrated Circuits.
`
`10.
`
`In 2009, I was elected a Fellow of the Institute of Electrical and
`
`Electronics Engineers (“IEEE”) in recognition of my contributions to low voltage
`
`complementary metal-oxide-semiconductor (CMOS) mixed-signal technology.
`
`The IEEE is a worldwide professional body consisting of more than 300,000
`
`electrical and electronic engineers. Fellow is the highest grade of membership of
`
`the IEEE, with only one-tenth of one percent of the IEEE membership being
`
`elected to the Fellow grade each year.
`
`11.
`
`I am being compensated for my time at my ordinary hourly rate of
`
`$500. My compensation is not dependent on the outcome of these proceedings or
`
`the content of my opinions. To the best of my knowledge, I have no financial
`
`interest in either party or in the outcome of this proceeding.
`
`6
`
`

`

`III. MATERIALS CONSIDERED
`12.
`In preparing this declaration, I have reviewed and understand the
`
`following papers and exhibits cited herein:
`
`1005
`
`Exhibit Description
`
`Petition for Inter Partes Review No. IPR2020-01561 (“Petition”)
`1001
`U.S. Patent No. 7,719,452 (“’452 patent”)
`Declaration of Dr. Douglas Holberg in support of Petition for Inter
`1002
`Partes Review No, IPR2020-01561
`1003
`Prosecution File History for U.S. Patent No. 7,719,452
`1004
`U.S. Patent No. 6,970,125 (“Cesura”)
`Fu, Daihong et al., “A Digital Background Calibration Technique for
`Time-Interleaved Analog-to-Digital Converters,” IEEE Journal of
`Solid-State Circuits, Vol. 33, No. 12 (1987) (“Fu”)
`Lewis, Stephen et al., “A Pipelined 5-Msample / s 9-bit Analog-to-
`Digital Converter,” IEEE Journal of Solid-State Circuits, Vol. SC-22,
`No. 6 (1988) (“Lewis”)
`U.S. Patent No. 7,129,874 (“Bjornsen”)
`Allen, Philip E., and Douglas R. Holberg, CMOS Analog Circuit
`Design (2002) (“Allen”)
`U.S. Patent No. 7,602,324 (“Huang”)
`Wiley Electrical and Electronics Engineering Dictionary (2004)
`
`1006
`
`1007
`1008
`2001
`2004
`
`
`
`IV. LEVEL OF ORDINARY SKILL IN THE ART
`13.
`I have reviewed Petitioner’s proposed level of education and
`
`experience for a person of ordinary skill in the art (“POSITA”) at the time of the
`
`alleged invention of the ’452 Patent, and think it is reasonable. I have applied that
`
`level of skill for the purposes of this declaration.
`
`7
`
`

`

`V. TECHNICAL BACKGROUND
`A.
`Pipelined ADC Architecture
`14. Figure 1 of the ’452 patent shows a conventional pipelined analog-to-
`
`digital converter consisting of a sampler and multiple successive signal converters
`
`25 (also called stages). Each of the stages produces a digital code Cdgtl from the
`
`analog input signal received from the immediately previous stage (or from the
`
`signal sampler, in the case of the first stage). Ex. 1001, 3:17-21.
`
`
`
`’452 patent, Fig. 1.
`
`15.
`
`In this example, the first converter stage 24 produces a digital code
`
`Cdgtl representing the most significant bits of the system digital code 28; the second
`
`
`
`8
`
`

`

`stage produces a code representing the next most significant bits, and so on1. Each
`
`stage, other than the last, also generates an analog residue, representing the
`
`portion of the analog signal not yet quantized into a digital code, and presents this
`
`as the analog input signal to the next stage for further processing. Ex. 1001,
`
`2:25-34, 2:49-66, 3:2-10.
`
`16. One of the stages, marked with the arrow 29, is shown in further
`
`detail at the top of Figure 1. The analog output signal from the preceding stage is
`
`received as V0n (denoting it is an output of a prior stage “n”) and converted by
`
`ADC 31 to yield a digital code, Cdgtl. Id., 3:18-21. That digital code is converted
`
`back to analog by DAC 32 and subtracted from V0n by summer 33. Id., 3:21-24.
`
`The resulting residue signal (i.e., the remaining, unconverted analog signal) is then
`
`amplified (i.e., “gained up”) by residue amplifier 34 and passed to the next stage.
`
`Id., 3:24-29. In this way, each stage converts part of an incoming analog signal
`
`into a digital code and passes the remainder of the analog signal that was not
`
`converted (i.e., the residue) on to the next stage for additional processing. The
`
`digital codes from all the stages are passed to an aligner/corrector 27 and, “after
`
`the aligner/corrector 27 has received the digital codes Cdgtl from all of the signal
`
`
`1 This explanation is simplified and ignores redundant code bits provided by each
`
`stage.
`
`9
`
`

`

`converters 25, [it provides] a system digital code at an output port 28 that
`
`corresponds to the original sample.” Id., 3:4-10.
`
`17. Figure 5 of the patent depicts the “transfer function” of an exemplary
`
`stage, and shows the analog output voltage of a stage (i.e., the residue) as a
`
`function of the analog voltage input to the stage. The figure has been excerpted
`
`and annotated below to illustrate the operation of each converter stage of an ADC
`
`pipeline.
`
`10
`
`

`

`18. The function resembles a sawtooth, with each “tooth” representing a
`
`different digital code output by the stage. For example, in the figure above, the
`
`
`
`11
`
`

`

`three sawtooths represent three digital codes Cdgtl: -1, 0, and +1.2 If the converter
`
`represented by this transfer function receives an input voltage in the leftmost
`
`region (the leftmost sawtooth), the converter stage outputs a digital code Cdgtl of -
`
`1. For higher input voltages, the residual voltage output by the stage is also
`
`higher, starting at a low point of 0 volts. When the input voltage is at the tip of the
`
`leftmost sawtooth, it transitions to the middle region. At that point, the converter
`
`stage outputs a digital code Cdgtl of 0, and the residual voltage resets back to 0. At
`
`still higher voltages, the converter stage eventually reaches the rightmost region,
`
`in which it outputs a digital code Cdgtl of +1 and again reset the residual voltage
`
`back to 0.
`
`19. Below is an illustrative example of a 1.5 bit converter stage, which
`
`resolves an input voltage V0n into a digital code Cdgtl and a residue signal V0n+1.
`
`On the right is a transfer function of the 1.5 bit stage showing the mapping of the
`
`input voltage V0n (horizontal axis) to the residue signal V0n+1 (vertical axis). The
`
`transfer function maps the input voltage V0n to three regions—a leftmost region
`
`(Cdgtl = -1), an rightmost region (Cdgtl = +1), and a middle region (Cdgtl = 0)—
`
`depending respectively on whether the input voltage V0n is less than a lower
`
`
`2 The specific digital codes output by a converter stage may vary based on the
`
`specific architecture of the stage.
`
`12
`
`

`

`voltage VL, greater than an upper voltage VU, or between (and including) the lower
`
`and upper voltages.
`
`20.
`
`In the 1.5 bit stage, the ADC compares input voltage V0n to the upper
`
`voltage VU and lower voltage VL using upper and lower comparators, respectively.
`
`Based on the comparator outputs, the decoder determines the value the digital code
`
`
`
`Cdgtl.
`
` When V0n is in the leftmost region (i.e., V0n < VL), neither
`
`comparator is triggered, causing the decoder to output a digital code
`
`Cdgtl of “-1”.
`
` When V0n is in the middle region (i.e., VL ≤ V0n ≤ VU), only the
`
`lower comparator is triggered, causing the decoder to output a digital
`
`code Cdgtl of “0”.
`
`13
`
`

`

` When V0n is in the rightmost region (i.e., VU < V0n), both
`
`comparators are triggered, causing the decoder outputs a digital code
`
`Cdgtl of “+1”.
`
`21. The digital code Cdgtl represents a quantized portion of the input
`
`voltage V0n. The DAC generates an analog signal (i.e., VDAC= ½ VREF × Cdgtl)
`
`equal to this quantized portion, and subtracts it from the voltage V0n. The stage
`
`then multiplies this difference by 2 to generate the residue, i.e., V0n+1 = 2 *
`
`(V0n-VDAC). For example, in rightmost region ½ VREF is subtracted from V0n
`
`before multiplying by 2, whereas, in the leftmost region, ½ VREF is added to V0n
`
`before multiplying by 2.3
`
`
`3 The vertical portion of the sawtooth transfer function show a voltage drop of
`
`VREF, not ½ VREF, due to the fact that the converter stage multiplies the output
`
`of the difference by 2 before outputting the voltage to the next stage.
`
`14
`
`

`

`
`
`22. To illustrate, consider the case where VREF is 1 volt, and stage 2
`
`receives an input voltage V02 of 0.4 volts. Because 0.4 volts is greater than the
`
`upper voltage VU both comparators in the flash ADC are triggered, causing the
`
`encoder to generate the digital code Cdgtl of “+1”. The DAC generates an output
`
`analog signal VDAC of 0.5 volts, which is then subtracted from the input voltage V02
`
`and the difference is then multiplied by 2 to generate a residue V03 of -0.2 volts.
`
`B.
`Linearization Dither in a Pipelined ADC
`23. Dither and dithering have long been known to POSITAs as method
`
`for enhancing linearity. For example, the Wiley Electrical and Electronics
`
`Engineering Dictionary (2004) defines dither/dithering as the “incorporation of a
`
`small perturbation or a little noise, for instance to minimize the effects of minor
`
`nonlinearities.” Ex. 2004.
`
`15
`
`

`

`24. The patent explains that fabrication errors impacting the components
`
`of the digital-to-analog converter portion of an ADC can result in non-linear
`
`operation of the ADC. See Ex. 1001, 5:25-38. For example, a capacitor used in
`
`the system may have smaller or larger actual capacitance than its nominal,
`
`designed-for value. Id., 5:39-47. Dither is intended to address these errors—not
`
`by correcting or accounting for root causes of a particular component’s error—but
`
`instead by randomizing which components are used to process a series of input
`
`signals so that, on average, the errors in the different components of the ADC
`
`counteract each other, reducing the overall error in the conversion.
`
`25. As the patent further explains, when dither signals are combined with
`
`the sampled input signal, the signal “randomly flows along different signal
`
`processing paths” in the stages, and these paths “will induce different magnitudes
`
`of INL [integral nonlinearity] errors having one sign and similar magnitudes of
`
`INL errors having a different sign. The average error of these processing paths
`
`will thus be substantially reduced to thereby realize significant improvements in
`
`system linearity and substantially improve the system’s INL.” Id., 7:42-49.
`
`26. While adding dither to the analog signal improves the linearity of a
`
`converter, it also results in a digital value (a “combined digital code”) that
`
`represents the sum of the original analog signal and the added dither signal, and the
`
`dither signal must be removed to obtain a correct digitized version of the original
`
`16
`
`

`

`signal. Ex. 1001, 6:26-28. The dither signal is generated by converting a
`
`randomly generated digital code into a corresponding analog voltage. Id., 6:12-15.
`
`That same random code (which is known to the system) is decoded and subtracted
`
`(i.e., differenced) from the combined digital code generated by the system, so that
`
`the remaining digital code correctly represents the original analog signal. Id., 6:23-
`
`35.
`
`27. As one example, U.S. Patent No. 7,602,324 to Huang et al. (Ex. 2001
`
`(“Huang”)), cited on the face of the ’452 patent, discloses a pipelined ADC that
`
`adds a dither signal to the analog input signal, and subsequently removes the
`
`dither signal from the combined digital signal:
`
`Ex. 2001, Fig. 1. The steps disclosed in Huang are spelled out clearly in its Figure
`
`
`
`4:
`
`17
`
`

`

`
`
`Id., Fig. 4.
`
`28. As Huang confirms, it was known that adding a dither signal to the
`
`sampled analog input signal could increase the overall linearity of the converter.
`
`See Ex. 2001, 3:10-15 (“Since the dither value OD is an intentionally applied
`
`form of noise and used to randomize quantization error (difference between actual
`
`analog value and quantized digital value), the non-linearity in the A/D converter
`
`100 can be reduced based on the dither value OD, thus generating the digital
`
`signal with better quality.”).
`
`18
`
`

`

`VI. THE CLAIMED INVENTION
`A. Overview of the Invention
`29. The ’452 patent discloses improved systems and techniques for
`
`applying dither in a pipelined ADC. The ’452 inventors discovered that the
`
`linearization effect of dithering could be frustrated, or limited, in pipelined
`
`converters, due to certain aspects of their multistage structure. For example, the
`
`pipeline’s interstage gain in relation to the dither values’ amplitude, the relative
`
`spacing of the dither voltage levels, and the number of possible dither values could
`
`cause the effects of dithering to prematurely exhaust, so that not all pipeline stages
`
`would benefit from the randomizing and error-averaging effects of dithering.
`
`30. To address this problem, the ’452 patent’s inventors created novel
`
`modifications to the otherwise conventional digital-to-analog (“DAC”) component
`
`in a pipelined ADC to create analog dither values that were ensured to not
`
`prematurely exhaust and instead would propagate through all the downstream
`
`pipelined converter stages. Injecting the improved dither into the sampler or first
`
`converter stage, for example, would thus cause all converter stages, not just some,
`
`to process samples utilizing random “different signal-processing paths,” thereby
`
`enhancing the linearity of the system.
`
`B.
`The Problem of Dither Exhaustion
`31. The ’452 inventors demonstrate the problem addressed by the
`
`patent—dither exhaustion—in Figures 7A and B of the patent. As backdrop to this
`
`19
`
`

`

`discussion, Figure 10 of the ’452 Patent has been annotated to illustrate how dither
`
`might be exhausted in a system that applies prior art dithering techniques in an
`
`ADC pipeline (i.e., using conventional dither values agnostic of the pipeline’s
`
`structural details). In the figure, only the first two pipeline stages receive and
`
`benefit from the randomizing effects of dither injected into the first stage in the
`
`pipeline. A pseudo-random (PN) generator 85 (highlighted yellow in the Figure)
`
`provides a random digital code to DACs 86 and 88, which convert the random
`
`code to an analog voltage. The analog voltage is then applied as an analog dither
`
`signal to the first signal converter stage in the pipeline via dither capacitors 87 and
`
`89. See Ex. 1001, 6:47-53. Adding the analog dither signal in Figure 10 to the
`
`first stage creates a combined analog signal that is converted by the first stage into
`
`a digital code Cdgtl, which includes a first component corresponding to the analog
`
`input signal and a second component corresponding to the analog dither signal.
`
`Additionally, the first stage outputs an analog residue, which also includes not-yet-
`
`quantized analog components corresponding to the analog input signal and the
`
`analog dither signal.
`
`20
`
`

`

`
`
`32. The second converter stage is similar to the first converter stage in
`
`that it also generates a digital code Cdgtl that includes first component and a
`
`second component that respectively derive from the analog input signal and the
`
`analog dither signal. But unlike the residue from the first converter stage, the
`
`residue from the second converter stage does not contain a second component
`
`corresponding to the analog dither signal. Thus, in this example, the dither is
`
`exhausted by the third converter stage (and for all subsequent converter stages),
`
`and from the perspective of these stages, it is as though dither was never injected
`
`into any stage of the pipeline.
`
`21
`
`

`

`33. The ’452 inventors illustrated in Figure 7A of the ’452 patent, below,
`
`how dither was exhausted in the downstream stages of pipelined ADC converters
`
`as a natural consequence of the operation of the pipeline.
`
`
`
`34. Figure 7A shows the exemplary transfer functions for five converter
`
`stages in a pipelined ADC. The transfer functions map the input voltage Vin
`
`(horizontal axis) provided to the first converter stage, to the residue voltage
`
`(vertical axis) generated by each stage (e.g., stage 1 generates residue V01, stage 2
`
`generates residue V02, etc.). Because converter stages 2-5 each multiply their
`
`residue output signals by 2 before passing it to the next stage, the slope of each
`
`successive transfer function is twice that of the previous transfer function. See Ex.
`
`1001, 3:24-26 (describing “gaining up” the residue).
`
`22
`
`

`

`35. Figure 7A shows three regions for converter stage 1, with boundaries
`
`demarcated by sawtooth transitions. When the input voltage Vin to converter
`
`stage 1 is in the middle region (i.e., -0.125 volts ≤ Vin ≤ +0.125 volts) 4, the stage
`
`outputs a digital code Cdgtl of “0”, and outputs a residue voltage that is proportional
`
`to the input voltage Vin. When the input voltage Vin is in the rightmost region
`
`(i.e., 0.125 volts < Vin ≤ 0.375 volts), stage 1 outputs a digital code Cdgtl of “1” and
`
`generates a residue voltage by subtracting 0.25 volts from the input analog signal
`
`and then multiplying the result by 4. And when the input voltage Vin is in the
`
`leftmost region (i.e., -0.375 volts ≤ Vin < -0.125 volts), stage 1 outputs a digital
`
`code Cdgtl of “-1” and generates a residue voltage by adding 0.25 volts to the input
`
`analog signal and then multiplying the result by 4.5
`
`36.
`
`In Figure 7A, the dashed vertical lines represent five conventional
`
`dither levels 111, 112, 113, 114, and 115 (in this example, -0.125 volts, -0.0625
`
`volts, 0 volts, +0.0625 volts, and +0.125 volts) that could be applied to the input of
`
`converter stage 1 in this exemplary system, resulting in the different depicted
`
`
`4 It is assumed that the full-scale voltage range is 2 volts.
`
`5 Shown in the transfer function as a drop of 1.0 volts (0.25 * 4).
`
`23
`
`

`

`residue values.6 As shown, adding these different amounts of dither to the input
`
`analog signal to stage 1 (as reflected by a shift to the left or right on the horizontal
`
`axis) results in five different values of the residue signal at the output of stage 1 (as
`
`reflected by a shift up or down on the vertical axis). However, those same five
`
`different amounts of dither at the input to stage 1 result in only three different
`
`residue signals at the output of stage 2 (i.e., the five dither values occupy only
`
`three different locations on the vertical axis). This reduces the amount of
`
`randomness in the signal processing paths of the next stage (stage 3). And as
`
`further shown below, in stage 3, the number of different output residue signals has
`
`been further reduced down to one – i.e., the randomness in the output of stage 3
`
`has been completely eliminated and the dither injected into stage 1 has been
`
`exhausted.
`
`37.
`
`Indeed, the residue is the same as if no dither at all were injected in
`
`stage 1 (see, e.g., vertical point 113). Since the residue is the same as if no dither
`
`at all were applied, “the dither fails to alter the signal processing paths through
`
`these latter stages.” Ex. 1001, 7:56-57.
`
`38. This dither exhaustion arises from the fact that the amount of dither
`
`injected in converter stage 1 is exactly equal to the voltage subtracted/added to the
`
`
`6 A dither level of 0 indicates that no dither voltage is applied.
`
`24
`
`

`

`input analog voltage in one of the subsequent stages. Consider for example dither
`
`level 115, in which an analog dither amplitude of 0.125 volts is added to an input
`
`voltage Vin of zero volts. Because the combined voltage (0.125 volts) is in the
`
`middle region of stage 1 (i.e., -0.125 volts ≤ 0.125 ≤ +0.125 volts), converter
`
`stage 1 outputs a digital code Cdgtl of “0” and outputs a residue voltage VO1 of 0.5
`
`volts (generated by subtracting 0 volts from 0.125 volts and multiplying the result
`
`by 4)7. This value is passed to converter stage 2.
`
`
`
`
`7 Stage 1 is a 2.5 bit stage, which means that the output would be “gained up” by a
`
`factor of 4, rather than a factor of 2. See ’452 patent, 7:2-4.
`
`25
`
`

`

`39. The stage 2 transfer function shown in FIG. 7A above maps the input
`
`voltage Vin (not the output of stage 1 V01) to the residue VO2 of stage 2, showing
`
`that for dither level 115, the residue V02 is 0 volts. The middle region of converter
`
`stage 2 spans from -0.0625 volts to +0.0625 volts of Vin. Although the stage 2
`
`transfer function maps Vin to V02, and not the output of stage 1 (V01) to V02, one
`
`can apply the transfer function in 7A to show the mapping of V01 to V02 by
`
`accounting for the fact that the output of stage 1 was “gained up” by a gain of 4.
`
`Accordingly, to use Figure 7A to determine the residue V02 from stage 2 based on
`
`Vin, one must divide the output V01 of stage 1 by 4. In the example using dither
`
`level 115, the output of stage 1 is 0.5 volts, which means that the residue VO2 from
`
`stage 2 corresponds to a Vin signal of 0.125 volts (0.5 / 4). The input residue signal
`
`to stage 2 therefore falls within the rightmost region of converter stage 2,
`
`resulting in a digital code Cdgtl of “1”. Because the input residue signal to stage 2
`
`is in the upper range of stage 2, stage 2 calculates an output residue signal of 0
`
`volts by subtracting 0.5 volts from the input residue signal (of 0.5 volts) and
`
`multiplying the result by 2.8 That is, the voltage subtracted in stage 2 perfectly
`
`cancels the dither signal for level 115, as shown by the fact that output residue is
`
`located exactly in the middle of the sawtooth waveform – in the same position as if
`
`
`8 Stages 2-5 have a “gain-up” of 2.
`
`26
`
`

`

`no dither had been added at all. The same result occurs when dither level 111 is
`
`initially input into converter stage 1, except for level 111 the dither signal is
`
`perfectly canceled by adding an analog amplitude of 0.5 volts in stage 2 to a
`
`residue signal received from stage 1, which has an amplitude of -0.5 volts.
`
`40. A similar analysis can be applied to dither level 114. For dither level
`
`114, an analog dither amplitude of 0.0625 volts is added to an input voltage of
`
`zero volts. This combined voltage of 0.0625 volts is in the middle region of
`
`converter stage 1. The residue signal output from stage 1 is therefore 0.25 volts,
`
`calculated by subtracting 0 volts from 0.0625 volts and multiplying the result by 4.
`
`41. Converter stage 2 receives the 0.25 volts signal V01, which is in the
`
`middle region of stage 2. This is shown in Figure 7A by dividing the 0.25 volts
`
`signal V01 by 4 (to reflect the input voltage scale used by the input to stage 1) and
`
`mapping the resulting 0.0625 voltage level to the stage 2 transform function.
`
`Because the input to stage 2 is in the middle region, stage 2 calculates a residue
`
`signal of 0.5 volts, by subtracting 0 volts from the 0.25 volts input signal and
`
`multiplying the result by 2.
`
`42. Converter stage 3 then receives the 0.5 volts signal, which falls within
`
`the rightmost region of stage 3. This is shown in Figure 7A by dividing the 0.5
`
`volts input signal by 8 (the combined gains of stage 1 and stage 2) to derive the
`
`value 0.0625 and mapping that value to the transform function of stage 3.
`
`27
`
`

`

`Converter stage 3 generates an output residue signal of 0 volts (i.e., a signal with
`
`no dither) by subtracting 0.5 volts fro