US007719452B2
`
`US 7,719,452 B2
`(10) Patent No.:
`az United States Patent
`Bardsleyetal.
`(45) Date of Patent:
`May18, 2010
`
`
`(54) PIPELINED CONVERTER SYSTEMS WITH
`ENHANCED LINEARITY
`
`(75)
`
`Inventors: Seott Gregory Bardsley, Gibsonville,
`NC (US); Bryan Scott Puckett,
`Stokesdale, NC (US); Michael Ray
`.
`.
`Elliott, Summerfield, NC (US); Ravi
`Kishore Kummaraguntla, Austin, TX
`(US), Ahmed Mohamed Abdelatty Ali,
`Oak Ridge, NC (US); Carroll Clifton
`Speir, Pleasant Garden, NC (US); James
`Carroll Camp, Greensboro, NC (US)
`(73) Assignee: Analog Devices, Inc., Norwood, MA
`(US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`US.C. 154(b) by 118 days.
`
`(21) Appl. No.: 12/284,672
`
`(22)
`
`(65)
`
`Filed:
`
`Sep. 23, 2008
`oe
`.
`Prior Publication Data
`US 2010/0073210 Al
`Mar. 25, 2010
`
`(51)
`
`Int. Cl.
`(2006.01)
`HO3M 1/20
`(52) US. CR veces 341/131; 341/118; 341/120;
`341/155; 341/161; 341/162
`(58) Field of Classification Search......... 341/118-122,
`341/131, 155, 161, 162
`See applicationfile for complete search history.
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`6/2002 Fetterman etal.
`........... 341/131
`6,404,364 B1*
`9/2002 Yuetal. oo... 341/161
`6,456,223 BL*
`
`eee 341/161
`5/2004 Galton oo...
`6,734,818 B2*
`
`
`8/2004 Nairet al. eee 341/118
`6,784,814 B1*
`
`2/2006 Galton seeeceeeeeeeeseeeeeeees 341/155
`7,006,028 Bo"
`
`....... seteteeteeenteeeneenes 341/162
`4/2006 Ali
`7,034,736 Bl .
`......0.... 702/126
`4/2006 Maloberti et al.
`7,035,756 B2
`9/2006 Maloberti et al.
`......... 702/126
`7,107,175 B2*
`3/2007 El-Sankary et al.
`......... 341/120
`7,187,310 B2*
`5/2009 Newmanetal.
`............ 341/131
`7,535,391 B1*
`7,602,324 B1* 10/2009 Huang etal. ...... 341/131
`2006/0227052 A1l* 10/2006 Tavassoli
`............. 343/700 MS
`* cited by examiner
`Primary Examiner—Linh V Nguyen
`(74) Attorney, Agent, or Firm—Koppel, Patrick, Heybl &
`Dawson
`
`(57)
`
`ABSTRACT
`
`Signal converter system embodiments are provided to sub-
`stantially reduce symmetrical and asymmetrical conversion
`errors. Signal-processing stages of these embodiments may
`include a signal sampler in addition to successively-arranged
`signal converters. In system embodiments, injected analog
`dither signals are initiated in response to a random digital
`code. They combine with a system’s analog input signal and
`the combined signal is processed down randomly-selected
`signal-processing paths of the converter system to thereby
`realize significant improvements in system linearity. Because
`these linearity improvements are realized by simultaneous
`processing ofthe inputsignal and the injected dither signal, a
`combineddigital codeis realized at the system’s output. A
`first portion of this combined digital code correspondsto the
`analog input signal and a secondportion corresponds to the
`injected analog dither signal. The final system digital code is
`realized by subtracting out the second portion with a back-
`end decoder that respondsto the random digital code.
`
`6,373,424 BI*
`
`4/2002 Soenen «ue 341/161
`
`20 Claims, 11 Drawing Sheets
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`U.S. Patent
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`May18, 2010
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`US 7,719,452 B2
`
`1
`PIPELINED CONVERTER SYSTEMS WITH
`ENHANCED LINEARITY
`
`BACKGROUNDOF THE INVENTION
`
`1. Field of the Invention
`Thepresent disclosure relates generally to pipelined signal
`converters.
`
`2. Description of the Related Art
`Pipelined analog-to-digital signal converter systems are
`often used in high-speed, high-resolution conversion appli-
`cations. These systems generally realize a desired number of
`conversion bits with a cascade (i.e., a pipeline) of lower-
`resolution converter stages and thus achieve high resolution at
`sampling speeds that are difficult to realize with other con-
`verter systems. Each stage of a pipelined system quantizes
`that stage’s input signal to a predetermined numberofdigital
`bits and forms an analog output signal whichis presented to a
`succeeding stage for further signal processing.
`The advantages of sampling speed may, however, be
`negated if conversion linearity is insufficient. For example,
`the multistage structure ofpipelined converter systems causes
`certain portions of the converter structure to be used repeti-
`tively as an analog input signal is swept over the system’s
`input range and converter nonlinearity in these portions can
`significantly degrade the conversion of low-level dynamic
`signals.
`Conversion linearity is generally characterized witha vari-
`ety of linearity parameters such as differential nonlinearity
`(DNL),
`integral nonlinearity (INL), signal-to-noise ratio
`(SNR), signal-to-noise-and-distortion ratio (SINAD), and
`spurious free dynamic range (SFDR). DNLerrorindicates the
`difference between an actual step width ofa least-significant
`
`bit and the ideal value while INL error measuresthe deviation
`
`
`
`of an actual transfer function from a straight linc. SNRC
`is
`computedby takingthe ratio ofthe rmssignalto the rms noise
`wherein the noise includesall spectral components minus the
`fundamental, the first four harmonics, and the DC offset.
`SINADisthe ratio (in dB) ofthe signal powerto the power of
`all spectral components minus the fundamental and the DC
`offset. Finally, SFDRis the ratio of the fundamental compo-
`nent to the rms valueof the next-largest spurious component
`(excluding DC offset).
`Although a variety of linearizing techniques have been
`proposed for pipelined converter
`systems,
`increasing
`demandson these systems continueto exert a needfor further
`improvementsin linearity.
`
`BRIEF SUMMARY OF THE INVENTION
`
`The present disclosure is generally directed to pipelined
`converter systems with enhancedlinearity. The drawings and
`the following description provide an enabling disclosure and
`the appended claims particularly point out and distinctly
`claim disclosed subject matter and equivalents thereof.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 is a diagram of a pipelined converter system;
`FIG.2 is a diagram ofa signal converter embodimentin the
`system of FIG. 1;
`FIG. 3 is a diagram of clock signals for use in the signal
`converter of FIG.2;
`FIG.41s a reference signal generator which may be used in
`the system of FIG.1;
`FIG.5 is a transfer-function diagram that corresponds to
`the signal converter of FIG. 2;
`
`2
`FIG.6 is a diagram of a converter system embodimentof
`the present disclosure;
`FIG. 7A illustrate transfer functions of signal-processing
`stages in the system of FIG. 6 and possible dither levels in
`these stages;
`FIG. 7B is similar to FIG. 7A andillustrates preferred
`dither levels;
`FIG. 7C illustrates comparator levels in a back-end stage
`that succeeds the stages of FIGS. 7A and 7B;
`FIGS. 8A, 8B and 8C are diagrams of a signal sampler
`embodiments for use in the system of FIG. 6;
`FIG.9 is a diagram of a signal converter embodiment for
`use in the system of FIG.6;
`FIG. 10 is a diagram of another converter system embodi-
`ment; and
`FIG. 11 is a diagramofa frontend signal converter embodi-
`mentfor use in the system of FIG. 10.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`FIGS. 1-11 introduce signal converter system embodi-
`ments which substantially enhance conversionlinearity. Sig-
`nal-processing stages of these embodiments may include an
`initial signal sampler in addition to successively-arranged
`signal converters. Typically, the signal sampler provides a
`respective analog output signal in the form of successive
`samples of a system’s analog input signal and all but a back-
`end one of the signal converters processes an analog output
`signal from a preceding oneofthe stages into a corresponding
`digital code and a respective analog output signal (i.e., a
`gained-up residue signal). The back-endsignal converter pro-
`cesses an analog output signal from a preceding one of the
`stages into a corresponding digital code but has no need to
`provide a respective analog output signal.
`In different system embodimentsof the disclosure, at least
`a selected one ofthe signal-processing stages is configured to
`simultaneously process two combined analog signals—the
`system’s analog input signal and an injected analog dither
`signal. The combined signal is thus processed down ran-
`domly-selected signal-processing paths of the converter sys-
`tem to thereby induce different magnitudes and signs of INL
`errors. The errors of these processing paths are averaged to
`therebyprovidesignificant improvements in system linearity.
`This processing, however, provides a combineddigital code
`in whicha first portion correspondsto the analog inputsignal
`and a secondportion correspondsto the injected analog dither
`signal. The final system digital code is realized by subtracting
`out the second portion.
`In particular, system embodiments of the present disclo-
`sure are directed to analog-to-digital converter systems such
`as the system 20 of FIG. 1 which is formed with M succes-
`sively-arranged signal-processing stages 22 that include a
`signal sampler 24 followed by M-1 successive signal con-
`verters 25. Except for a back-end signal converter 25B, each
`of the stages 22 generates a respective analog output signal
`and passes this signal to a succeeding stage for further pro-
`cessing.
`Signal conversion begins with the signal sampler 24 which
`captures samples of an analog input signal from a system
`input port 26 at a sample rate. These samples form the signal
`sampler’s respective analog output signal which is passed to
`the successive signal converters 25. All but the back-end one
`of these signal converters processes an analog output signal
`from a preceding one of the stages into a corresponding
`digital code C,,,, and a respective analog output signal which
`is passed to the succeeding converter stage. The back-end
`signal converter 25B processes an analog output signal from
`
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`US 7,719,452 B2
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`3
`apreceding one ofthe stages into a corresponding digital code
`Cagq but does not form a respective analog output signal.
`The system 20 includes an aligner/corrector 27 which
`receives and temporally aligns the digital codes C,,,,. Each
`sample from the signal sampler 24 is successively processed
`through the signal converters at the samplerate and, only after
`the aligner/corrector 27 has received the digital codes Cy.
`from all of the signal converters 25, does it provide a system
`digital code at an output port 28 that corresponds to the
`original sample. The signal converters 25 are generally con-
`figured to provide redundant code bits and the additional
`conversion information in these redundant codebits is used
`
`4
`apreceding stage anda succeeding stage are shifted as shown
`in FIG. 3. For example, 1 switches of the signal comparator
`41 and $2 switches of preceding and succeeding stages close
`at the same times. Although clock edges are shown to tem-
`porally coincide in FIG.3, this is for simplicity of illustration
`as these edges may be somewhatoffset in various converter
`embodimentsto facilitate proper operation.
`During each $2 operational phase of the signal converter
`40, the signal capacitor C, is switched to charge to a ladder
`comparator level (supplied by the ladder 48 as indicated by a
`broken-line arrow) and during each succeeding 1 opera-
`tional phase, the signal capacitor C, is switched to receive the
`analog output signal S,,,. from a precedingoneofthe signal-
`by the aligner/corrector 27 to correct conversion errors which
`processing stages. The signal at the input of the signal com-
`may occur when the analog input signal is near transition
`parator 46 thus represents a comparison ofthe signal S,,,y and
`points between analog regions that correspond to adjacent
`the comparatorlevel. In an early portion ofthe (1 operational
`digital codes.
`phase, the state of the signal comparatoris latched in accor-
`Example arrow 29 points to an exemplary embodiment30
`dance with this comparison.In responseto all of the latched
`of the signal converters 25. In this embodiment, an analog-
`signal comparators 46, the decoder 49 thus converts the ther-
`to-digital converter (ADC) 31 converts the respective analog
`mometer code of the comparators into the corresponding
`output signal of a preceding one of the stages 22 to a corre-
`digital code C,,,, and the set of decision signals D,-D,.
`sponding digital code C,,,. A digital-to-analog converter
`The MDACportion 42 of the signal converter 40 includes
`(DAC) 32 convertsthis digital code to a corresponding analog
`an amplifier 50 that provides the respective analog output
`signal which is differenced with the respective analog output
`signal S¢;.1) ofthis stage at the output port 45 and four signal
`signal in a summer33 to provide a residue signal. The residue
`capacitors C,-C, which are coupled to the amplifier. A feed-
`signal is then “gained up” in an amplifier 34 to provide the
`back capacitor C,is coupled about the amplifier 50 and 1
`respective analog output signal of the present stage. The gain
`switches groundthe input and output ofthe amplifier. A set of
`ofthe amplifier 34 provides an analog windowto the succeed-
`1 switches couple the signal capacitors to the inputport 44.
`ing stage that substantially matches the analog windowpre-
`In addition, a set of 2 switches couple the signal capacitors
`sented to the current stage.
`C,-C, to respectively receive subrange signals D,V,-D,V,
`Because of the above-described operation, a portion 36 of
`wherein the decision signals D,-D,, take on values +1, 0 and
`the signal converter embodiment30 is generally referred to as
`-1 andV,is a reference voltage.
`a multiplying digital-to-analog converter
`(MDAC). An
`In converter systems, itis generally advisable to use a set of
`embodiment 40 of one of the signal converters of FIG. 1 is
`stable reference signals throughout the system andthese are
`shown in FIG. 2. Although this embodiment could be
`preferably supplicd by a single MDACreference such as the
`arranged to convert an input signal to various numbers of
`reference 56 of FIG. 4. This reference provides stable and
`digital bits, the embodiment40 is shownas an 2.5 bit stage for
`accurate signals V,,,, and V,,,, which may, for example, be 1.5
`illustrative purposes. It should be understood that the con-
`and 0.5 volts. As shown in equations 58 in FIG.4, these basic
`cepts disclosed below maybe appliedto signal converters that
`signals may be used throughout the system (20 in FIG. 1) to
`provide different numbers ofdigital bits.
`40
`form the reference signals +V, and -V,. whereinafull scale
`The signal converter 40 includes a switched-capacitor
`MDAC embodiment 42 and also includes a switched-capaci-
`voltage V, is the difference between these reference signals.
`tor signal comparator embodiment 41. The signal converter
`The graph 60 of FIG.5 illustrates a transfer function 62 of
`40 is arranged to process an analog outputsignal S,,,, of a
`the MDACportion 42 ofthe signal converter 40 of FIG. 2 and
`preceding oneofthe signal-processing stages at an input port
`a correspondingtransfer function 63 ofthe signal sampler (24
`44 into a corresponding digital code Cy,,, and a respective
`in FIG.1) that precedes the signal converter. To better under-
`stand the converter transfer function, attention is now directed
`analog outputsignal S,,,,,) at an output port 45.
`The signal comparator portion 41 couples a 1 switch and
`to operation ofthe MDACportion 42 ofFIG. 2. It is first noted
`a signal capacitor C, between the input port 44 and one ofa set
`that the @1 switches close in the (1 operational phase so that
`the signal capacitors C,-C, receive charges from the analog
`of signal comparators 46. A ladder48 (e.g., a resistive ladder)
`output signal S,,,. In the 2 operational phase,
`the $2
`provides one of a plurality of comparator thresholdlevels to
`the signal capacitor C, through a 2 switch and another o2
`switches close and charges are transferred (via the gain ofthe
`amplifier 50) to the feedback capacitor C,to thereby develop
`switch couples the otherside ofthe signal capacitor to ground
`the analog output signal S,,,,,) at the output port 45.
`(similar switch, capacitor and ladderstructures are provided
`for each of the signal comparators 46 but are not shown to
`Assuming the gain of the amplifier 50 is sufficiently high
`enhance drawingclarity). Finally, a decoder 49(e.g., a latch-
`and that the signal capacitors C,-C, are sized equally to the
`feedback capacitor C, the gain of the MDACportion 42is
`able array ofdigital gates) provides the correspondingdigital
`code Cz,,, and a set of decision signals D, -D, in responseto
`foursince the chargesoffour signal capacitors are transferred
`the set of signal comparators 45. It is noted that the signal
`into a single feedback capacitor. This stage gain is indicated
`comparator 41 is sometimesreferred to as a flash comparator
`by an ideal reconstruct line 64 which coincides with the
`becauseall of the signal comparators operate in a common
`transfer function portion in a first converter subrange 65 in
`FIG.5.
`operational phase.
`As the analog outputsignal S,,,, of FIG. 2 decreases, the
`The signal converter 40 operates at a sample rate which is
`decision signals D,-D, in FIG. 2 successively change from 0
`defined by the number of clock periods that occur over an
`exemplary time interval. The timing diagram 55 of FIG. 3
`to +1 in response to the decoder 49 in the comparator portion
`showsthat the signal converter 40 of FIG. 2 operates infirst
`41. Accordingly,
`the transfer function 62 is successively
`and second operational phases $1 and $2 in each clock period.
`urged upward (away from the ideal reconstruct line 64) by the
`Withrespect to the stage of FIG. 2, the operational phases of
`reference signal V,. and this process generates the sawtooth-
`
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`US 7,719,452 B2
`
`5
`shaped portion of the transfer function 62 at the left side of
`FIG. 5. A similar sawtooth-shaped portion is generated in a
`similar manneratthe right side of FIG, 5 as the analog output
`signal S,,,, increases andthe decision signals D,-D, succes-
`sively change from 0 to -1. Thus, the MDACportion 42 of
`FIG. 2 generates the transfer function 62 which, as shown in
`FIG. 5, has an MDACgain of four and(as labeled in FIG. 5)
`varies over an output-signal window in each ofa plurality of
`converter subranges.
`As the analog output signal S,,,, of the preceding stage
`varies from a negative maximum to a positive maximum, the
`corresponding digital code C,,,, from the signal comparator
`portion 41 of FIG. 2 will change accordingly as the operating
`point passes into each converter subrange of FIG. 5. If no
`processing errors occur in the MDAC portion 42 ofFIG.2, the
`analog outputsignal S,,,,,) plus the corresponding onesofthe
`subrange signals D, V,-D,V, should exactly equal the analog
`output signal S,,,, ofthe preceding stage whenit is multiplied
`by the MDACgain of four. That is, the sum of the analog
`output signal S_.,,,) and corresponding ones ofthe subrange
`signals D,V,-D,,V, should producethe ideal reconstructline
`64 whichis initially formed by the analog outputsignal S,,;)
`multiplied by the MDAC gain offour.
`Fabrication errors in the MDACportion 42 will, however,
`cause the actual reconstructlineto differ from the ideal recon-
`struct line 64. If the feedback capacitor C,is smaller than
`intended, for example, MDACchargetransfer will bealtered
`and the gain in each ofthe converter subranges will be greater
`thantheir ideal value. This gain error is indicated in FIG. 5 by
`broken lines 66 which show how the transfer function sym-
`metrically tilts in each converter subrange. The sum of the
`analog outputsignal S,,,,,) and corresponding ones of the
`subrange signals D,V,-D,V, now produce an actual recon-
`struct line 68 in which symmetrically differs from the ideal
`reconstructline 64 in each converter subrange(for clarity of
`illustration in FIG. 5, the actual reconstruct line 68 is only
`shown in two of the converter subranges).
`The difference between the ideal reconstruct line 64 and
`the actual reconstruct line 68 are indicated by the integral
`nonlinearity (INL) 70 of the signal converter (40 in FIG. 2)
`whichis a measure of symmetricalerrors (e.g., errors due to
`the fabrication-error in the feedback capacitor C,). If the
`feedback capacitor C,is greater than intended or the gain of
`the amplifier 50 is significantly less than ideal, a similar INL
`will be introduced except that the slope in each converter
`subrangewill be reversed from that shown.
`In either case, the signal converter 40 of FIG. 2 will intro-
`duce undesirable symmetrical INL errors (e.g., as exempli-
`fied by segments 74 of the INL 70)into the transfer function
`of the converter system 20 of FIG. 1. Although these sym-
`metrical transfer function errors have been described above to
`originate from incorrect feedback capacitor C,size and insuf-
`ficient amplifier gain, they can also originate from other sys-
`tem errors (e.g., signal setting errors).
`In another type of typical MDACerrorthatis often termed
`“DACerror”, the signal capacitor C, may be smaller than the
`othersignal capacitors C,-C,, so that, for example,the transfer
`function in a converter subrange ontheleft side of the sub-
`range 65 is not urged upward as far as intended. This is
`indicated in FIG. 5 by the broken line 71 in this converter
`subranges. These asymmetrical types of MDACerrors will
`cause segments in the INL 70 to be urged up and downin
`different converter subranges so that both types of errors
`(symmetrical DAC errors and asymmetrical errors) combine
`to produce the INL 72. For example, the segment 74 in the
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`6
`INL 70 has been urged downward to the segment 75 in the
`INL 72 becauseofthetransfer function error indicated by the
`brokenline 71.
`
`To substantially reduce INL errors such as those indicated
`in FIG. 5, the converter system 20 of FIG.1 is altered to the
`system 80 of FIG. 6 which includes elements of FIG. 1 with
`like elements indicatedbylike reference numbers. In contrast
`to the system 20, however, the system 80 couples a pseudo-
`random (PN) generator 81, a DAC 82 andat least one asso-
`ciated dither capacitor 83 to the signal sampler 24 for injec-
`tion of dither signals.
`The PN generator 81 provides a random digital code
`wherein the numberof codes is sufficient to commandthe
`DAC82 andthe dither capacitor 83 to inject a corresponding
`numberof analog dither signals into an entry point A of the
`sampler 24. These injected dither signals combine with the
`input signal received at the inputport 26 and. Accordingly,the
`combined signal is processed down randomly-selected sig-
`nal-processing paths of the converter system which induce
`different magnitudes and signs of INL errors. The average
`error of these processing paths is reduced to thereby provide
`significant improvements in system linearity.
`these linearity
`It
`is important
`to note, however,
`that
`improvementsare realized by simultaneous processing oftwo
`combined analog signals—the input signal at the input port
`26 and the injected dither signal. As shown in FIG.6, this
`processing provides a combined digital code at the output of
`the aligner/corrector 27. A first portion of this combined
`digital code at the digital back-end of the signal converter
`corresponds to the analog input signal
`that was earlier
`received into the input port 26 but a second portion of the
`combined digital code corresponds to the injected analog
`dither signal. In the converter system 80, the final system
`digital code at the outputport 28 is realized by subtracting out
`the second portion in a differencer 90.
`As shown in FIG.6, the second portion is provided by a
`back-end decoder 84A which responds to the random digital
`code that was generated by the PN generator 81. The transfer
`function ofThe back-end decoder 84hasa transfer function
`whichis obtained from the transfer function of the DAC 82,
`the size of the dither capacitor 83, and the transfer function of
`the system 80 betweenthe entry point A and the outputof the
`aligner/converter 27.
`linearity
`similar
`In a different system embodiment,
`improvements are realized with dither signals that are
`injected in a selected downstream signal converter. For
`example, FIG. 6 also shows a PN generator 85, a DAC 86 and
`at least one associated dither capacitor 87 for insertion of
`analog dither signals into a signal comparator portion of a
`selected one of the signal converters. This figure also shows
`another DAC 88 andat least one associated dither capacitor
`89 for insertion ofdither signals into an MDACportion ofthe
`selected signal converter.
`Theresidue signal from the preceding signal converter and
`the injected dither signal are simultaneously processed along
`randomly-selected signal-processing paths that begin at the
`selected converter stage. As previously described, this pro-
`cessing provides a combineddigital code. A second portion of
`this combined digital code is removed in the differencer 90
`whereinthe secondportionis provided in this embodiment by
`a back-end decoder 84B that respondsto the random digital
`code of the PN generator 85. The transfer function of the
`back-end decoder 84B is determinedbythe transfer function
`of the DACs 86 and 88, the sizes of the dither capacitors 87
`and 89, andthetransfer function ofthe system 80 between the
`selected signal converter and the output ofthe aligner/correc-
`tor 27.
`
`Page 15
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`

`

`US 7,719,452 B2
`
`7
`Advantageous operation of these additional structures is
`investigated in FIGS. 7A-7C. In FIG. 7A,it is assumed that
`the signal converters 25 of FIG. 6 comprise an initial 2.5 bit
`stage followed by successive 1.5 bit stages and, accordingly,
`this figure shows a graph 100 which plots the analog output
`signal 101 of the 2.5 bit stage followedbyplots of the analog
`output signals 102-105 of the 1.5 bit stages. It is important to
`observethat this is an exemplary embodimentas other system
`embodiments may include stages that convert various other
`combinations of code bits.
`
`8
`Atthis point, attention is temporarily redirected to FIG. 5 to
`therebybetter review the definition of some important trans-
`fer function terms. Thefive dithered operating points (of FIG.
`7B) are showncollectively as a set 122 in one ofthe converter
`subranges of FIG. 5. As mentioned previously, the transfer
`function of this stage movesover an output-signal window in
`each of a plurality of converter subranges. The output-signal
`windowis sufficiently reduced(e.g., it spans V,,/2) from the
`full scale voltage V,, to establish correction ranges which
`accommodate extensions of the transfer function when its
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`amplide alters because of various conversion errors (e.g.,
`As shown,a converter subrange of the 2.5 bit stage spans
`threshold errors in flash comparators). As shown in FIG.5,the
`oneof the converter subranges ofthe succeeding 1.5 bit stage
`total span of the set 122 of operating points is now slightly
`and one half of each adjacent converter subrange. Similarly,
`reduced from the output-signal window. This span is defined
`each converter subrangeof oneofthe 1.5 bit stages spans one
`15
`
`ofthe converter subrangesof the succeeding 1.5 bit stage and in FIG.5as a dither range and is apparentthatthe dither range
`one half of each adjacent converter subrange. As exemplified
`is somewhatless than the output-signal window.
`in FIG.5, the output-signal window ofeachstage spans V,,/2.
`Returning attention to FIG. 7B, the vertical broken lines
`Thetransfer function of each succeeding stage is thus limited
`116 again identify operating points in the successive stages.
`to this span which leads to the arrangement of stage transfer
`To further aid in understanding operationsin the succeeding
`functions shown in FIG. 7A.
`stages, someofthe operating points on the lines 116 have also
`In FIG.7A,it is assumedthat the analog input signalat the
`been reflected inward to equivalent operating points in the
`input port 26 of FIG. 6 is positionedso that the current analog
`central converter subrange. In the third stage, for example,
`output signalis at the middle point 113 ofanalog outputsignal
`operating points 124 and 125 have been reflected inward to
`101. It is further assumed that the PN generator 81, DAC 82
`respective operating points in the central converter subrange
`and at least one capacitor 83 are configured to dither this
`as indicated by respective reflection arrows 126 and 127.
`operating point overfive operating points 111, 112, 113, 114
`These are equivalent operating points in that their output
`and 115 (in FIG. 8A,each operating point is indicated by an
`voltageslie at the samelevel in the output-signal range even
`oblong marker) wherein operating points 111 and 115 coin-
`though they occupy different converter subranges.
`cide with the ends of the converter subrange.
`Similar reflections have been performedin the analog out-
`Because the analog outputsignal ofthis converter subrange
`put signals of the fourth and fifth stages so that equivalent
`spans oneofthe converter subrangesofthe succeeding 1.5 bit
`operating points are now shownin the central converter sub-
`stage and one half of each adjacent converter subrange, the
`range in all of the stages in FIG. 7B. Inspection ofthe central
`corresponding operating pointsin this stage lie directly below
`converter subranges observesthat the dither range in each of
`the operating points in the first stage. This relationship fol-
`the stages now coversa substantial portion oftheir respective
`lows through succeeding stages so that the dithered operating
`output-signal windows. This is an important contrast to the
`situation in FIG. 7A in which there was an absenceofdither
`points are positioned as shown in FIG. 7A (visualization of
`this relationship is facilitated by vertical broken lines 116).
`Inspection of the central converter subranges observesthat
`the operating point in stage 1 is dithered over this subrange to
`thereby establish different signal processing paths through
`this stage and a lesser numberofdifferent signal processing
`paths through stage 2. Signal processing randomly flows
`along these different signal processing paths in stages 1.
`These paths will induce different magnitudes of INL errors
`having one sign and similar magnitudes of INL errors having
`a different sign. The average error of these processing paths
`will thus be substantially reduced to thereby realize signifi-
`cant
`improvements in system linearity and substantially
`improve the system’s INL. As subsequently described, the
`disturbing effects of the dither signal are removed at the
`summer 90
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`range in the third, fourth and fifth stages. The applied dither
`now establishes different signal processing paths throughout
`all stages of FIG. 7B.
`It is clear from FIG. 5,